JPH06259959A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a self-refresh operation by an external signal, and to facilitate a system design by automatically performing a refresh operation with the essentially same cycle with the normal cycle after the completion of a battery backup operation. CONSTITUTION:A battery backup operation completion judgment circuit 15 is provided in a self-refresh circuit 30. After the completion of a battery backup operation, the first cycle signal REFS1 with a long cycle at the time of a battery backup, is changed over to the second refresh cycle signal REFS2 with a short cycle, and a refresh is automatically and successively performed by the whole memory. Thus the completion of a refresh by the whole memory cell is detected by a counter 17 in m stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a self-refresh function, and more particularly to an improvement of an internal cycle signal generation circuit of a semiconductor memory device which performs a self-refresh operation using an internal cycle generated in the semiconductor memory device. It is about.

[0002]

2. Description of the Related Art In a dynamic random access memory (hereinafter referred to as "DRAM"), one memory cell is composed of one switching transistor and one data storage capacitor. It is widely used as a semiconductor memory suitable for high performance. In the DRAM, since the data signal is held by the capacitor, the "refresh operation" of periodically amplifying the data signal stored in the capacitor is required. Most of DRAMs in recent years have a function (generally called a "self-refresh function") capable of performing a refresh operation without requiring refresh control internally or externally.

FIG. 18 is a block diagram showing a conventional semiconductor memory device. Referring to FIG. 18, this DRAM 21
Is a memory cell array 22 having 4,718,592 memory cells arranged in rows and columns, and a row decoder 2 for selecting a word line in the memory cell array 22.
4, a row decoder 25 for selecting a column of memory cells to be accessed, a row decoder 25 for selecting a column of memory cells to be accessed, and an address signal externally applied in a time division manner. It includes a receiving address buffer 23, and a sense refresh amplifier input / output control circuit 26 for selectively connecting the bit line in memory cell array 22 to input buffer 27 and output buffer 28. In FIG. 16, the line 21 also indicates the semiconductor substrate.

The clock generation circuit 29 is a circuit for generating an internal clock, and the self-refresh circuit 30 is
It is a circuit that operates according to a row address strobe signal / RAS and a column address strobe signal / CAS to control a self refresh operation.

In operation, the address signals A _{0 to} A ₁₀ externally input to the DRAM 21 pass through the row and column address buffer 23 and the row or column decoders 24, 25.
Entered in. The memory cells of the memory cell array 22 corresponding to the address signals A _{0 to} A ₁₀ decoded by the row or column decoders 24 and 25 are selected, and the sense refresh amplifier input / output control 26 and the input / output buffers 27 and 2 are selected.
Input / output data D and Q are written and read out through 8. These operation timings are controlled by the column address strobe signal / CAS, the row address strobe signal / RAS, the write signal W, and the like.

Next, the self-refresh operation will be described. The self-refresh circuit 30 is / CAS bef
Although the self-refresh operation starts from the ore / RAS cycle, FIG. 19 shows the row address strobe signal / RAS and the column address strobe signal / C when this operation is performed.
FIG. 7 is a timing waveform chart of AS and a control signal BBU.

As shown in FIG. 18, the column address strobe signal / CAS is lowered to "L" before the row address strobe signal / RAS falls to "L", and the row address strobe signal / RAS is set to "L". 100 after falling to
By holding the column address strobe signal / CAS and the row address strobe signal / RAS at "L" for μs or more, the self refresh operation is started. At this time, the control signal BBU requesting the self-refresh operation
Becomes "H". And the row address strobe signal /
The self-refresh operation is continued until the RAS and the column address strobe signal / CAS are raised to "H".

The self-refresh operation is performed by, for example, incrementing the refresh address with an internal cycle signal REFS generated internally. With this self-refresh function, it is possible to retain internally written data with low current consumption, which will be an essential function in future semiconductor memories.

Next, referring to FIG. 20, / CAS before
Generation of control signal BBU in the self-refresh circuit in the / RAS cycle will be described.

FIG. 20 is a block diagram showing an outline of the self-refresh circuit 30 as viewed from the operation side.

Referring to FIG. 20, self-refresh circuit 30 determines the timing of / CAS before / RAS and the timing of self-refreshing / C.
The ASbefore / RAS determination circuit 12 (hereinafter referred to as the CBR determination circuit 12), the ring oscillator circuit 13 that outputs an internal period signal in response to the determination result of the CBR determination circuit 12, and the period signal of the ring oscillator circuit 13 are counted. And a counter 14 that outputs a signal at a cycle that is an integral multiple of that
Including and

In operation, / CAS before / RAS
Row address strobe signal / RAS
A signal is transmitted from the CBR determination circuit 12 to the ring oscillator circuit 13 and the counter 14 when
Oscillation of the external periodic signal REFS and its counting start.
When the counter 14 counts n internal cycles, the counter outputs the control signal BBU. Therefore, the control signal BBU is output at a cycle n times as long as the internal cycle signal REFS.

The control signal BBU is the substrate potential generation circuit 31.
Given to. The substrate potential generation circuit 31 controls the control signal BB.
When U is at "H" level, that is, it is inactivated at the time of self-refresh, and the generation of substrate potential VBB is stopped.

This is because the substrate potential generating circuit 31 shown in FIG.
The block diagram of FIG. With reference to FIG. 21, substrate potential generation circuit 31 includes a NAND gate 31a, an inverter 31b, a ring oscillator circuit 31c, and a charge pump circuit 31d. NAND gate 31a includes two input terminals, one input terminal receives an internal / RAS signal from clock signal generating circuit 29 (FIG. 18) through inverter 31e, and the other input terminal controls through inverter 31f. The signal PBU is input.

In operation, when the control signal BBU is "H", the output of the NAND gate 31a is at "H" level and the ring oscillator 31c is inactive. As a result, the generation of the substrate potential VBB can be stopped during the battery backup operation, so that the power consumption can be reduced. However, since the output of the NAND gate 31a does not become the low level until the internal / RAS signal becomes the "L" level again after the completion of the self-refresh operation, there is a problem that the substrate potential cannot be generated during this period.

[0016]

By the way, it is necessary to refresh all the memory cells once before the transition from the battery backup operation to the normal cycle refresh operation (normal operation mode).

However, since the conventional semiconductor memory device is configured as described above, before the transition from the battery backup operation to the normal cycle refresh operation, the user externally gives a signal to enter the normal operation mode. I was doing the transfer operation of. This external signal is a command signal for refreshing all the memory cells by inputting / RAS only refresh 1024 times, for example. Since such an external operation is required, there is a problem that it becomes a constraint in designing the system.

Further, as described above, there is a problem that the substrate potential VBB cannot be generated until the internal / RAS signal becomes "H" level again after the self refresh operation is completed.

One object of the present invention is to eliminate the system design restriction in a semiconductor memory device having a self-refresh function by automatically shifting from the end of the battery backup operation to the normal operation mode.

Another object of the present invention is to provide a semiconductor memory device having a self-refresh function,
It is to reduce the power consumption and to generate the substrate potential immediately after the battery backup operation is completed.

[0021]

A semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device having a self-refresh function, the detecting means, a first periodic signal generating means, and a second periodic signal. It includes generating means and self-refresh operation stopping means. The detection means detects a battery backup operation start instruction and a battery backup operation stop instruction based on the logical state of a state control signal for controlling the storage state of the semiconductor memory device. The first periodic signal generating means generates a first periodic signal for holding the data of the memory cell in response to the detected start command of the battery backup operation. The second periodic signal generating means generates a second periodic signal having a shorter period than the first periodic signal in response to the detected stop command of the battery backup operation. The self-refresh operation stopping means counts the cycle of the generated second periodic signal, and stops the self-refresh operation when the cycle of the second periodic signal reaches the number of times of refreshing all the memory cells.

According to another aspect of the semiconductor memory device of the present invention,
Similar to the semiconductor memory device of the first aspect, the semiconductor memory device includes a detection unit, a first periodic signal generation unit, and a second periodic signal generation unit, and further includes a self refresh operation stop unit and an output unit. Self refresh operation stop means
Counting the period of the second periodic signal generated by the second periodic signal generating means, and stopping the self-refresh operation when the period of the second periodic signal reaches the number of times of refreshing all the memory cells, And a self-refresh end signal is generated. The output means detects completion of the self-refresh operation based on the logic state of the generated self-refresh end signal and the logic state of the data output from the memory cell, and outputs it to the outside of the semiconductor memory device.

According to another aspect of the semiconductor memory device of the present invention,
The invention according to claim 1 or claim 4 further includes an active state control means. The active state control means deactivates a circuit not involved in the battery backup in response to the battery backup start command detected by the detection means and responds to the battery backup operation stop command detected by the detection means. The inactivated circuit is activated.

[0024]

In the semiconductor memory device according to the first aspect of the present invention, the detecting means detects the stop command of the battery backup operation, and the second periodic signal generating means responds to the detecting means by a period shorter than the first periodic signal. Automatically generate the second periodic signal of. Then, the self-refresh operation stopping means counts the second periodic signal, and when the cycle of the second periodic signal reaches the number of times of refreshing all the memory cells, the self-refresh operation is stopped. As a result, the operation of inputting an external signal when shifting to the normal operation mode can be eliminated, and restrictions in system design can be eliminated.

According to another aspect of the semiconductor memory device of the present invention, after the refresh operation in the second cycle is performed on all the memory cells by the output means, the completion of the refresh operation is detected to detect the outside of the semiconductor memory device. Can be output to. Thereby, the external system can use the completion information of the refresh operation in the second cycle as the ready / busy signal.

In the semiconductor memory device according to the fifth aspect of the present invention, the substrate generating circuit,
A circuit that is not involved in battery backup, such as a circuit that does not cause a problem in data retention of the memory cell, can be deactivated to reduce current consumption. In addition, the circuit that has been deactivated during the battery backup operation is activated so that the normal operation state is immediately obtained after the battery battery backup operation is completed. As a result, the transition to the normal operation mode can be smoothly performed.

[0027]

【Example】

First Embodiment FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. FIG. 2 is a block diagram of the self-refresh circuit of the semiconductor memory device shown in FIG. FIG. 3 is a timing chart of the self-refresh circuit shown in FIG.

The semiconductor memory device 100 shown in FIG.
The semiconductor memory device 21 is different from the semiconductor memory device 21 shown in FIG. 1 in that the first periodic signal generating circuit 30a and the second periodic signal generating circuit 30
That is, the self-refresh circuit 30 including b.

First periodic signal generating circuit 30a is connected to receive row address strobe / RAS and column address strobe signal / CAS, and / RAS before
/ CAS and the row address strobe signal RAS becomes 1
When the “L” level is maintained for 00 μsec or more, the control signal BBU1 for performing the battery backup control is generated and the refresh cycle signal REFS1 is generated.

Second periodic signal generating circuit 30b is connected to receive control signal BBU1 and row address strobe signal / RAS, and is controlled when control signal BBU1 falls and row address strobe signal / RAS rises. Signal BBU2 and refresh cycle signal REF
S2 is generated.

The circulation cycle of the refresh cycle signal REFS1 is as long as possible (for example, 128 μs) within a range in which the data signal held in the memory cell is not lost.
The circulation cycle of the fresh cycle signal REFS2 set to ec) is set to a cycle (for example, 200 nsec) substantially the same as that in the normal operation mode.

Referring to FIG. 2, the first periodic signal generating circuit 30a includes a CBR generating circuit 12, a ring oscillator circuit 13 and an n-stage counter 14. The second periodic signal generation circuit 30b includes a battery backup operation end determination circuit 15, a ring oscillator circuit 16 and an m-stage counter 17.

Next, the operation of the self-refresh circuit 30 shown in FIGS. 1 and 2 will be described with reference to FIG. First, the CBR determination circuit 12 uses / CAS before / RAS
And row address strobe signal / RAS is 100μ
CBR is detected when it is at "L" level for more than sec
A signal is generated and applied to the ring oscillator circuit 13. Ring oscillator circuit 13 generates an internal signal φS1 in response to the CBR signal and applies it to counter 14.
This internal signal φS1 corresponds to the cycle of the self-refresh cycle signal REFS1 in the battery backup operation. The counter 14 counts the cycle of the internal signal φS1 by an integral number of times n, generates a control signal BBU1 for performing a battery backup operation, and uses the internal signal φS1 generated by the ring oscillator circuit 13 as a refresh cycle signal REFS1 as a clock signal. It is given to the generation circuit 29. In this way, the refresh operation for battery backup by the long cycle signal can be performed.

Next, row address strobe signal / RAS
By raising the column address strobe / CAS, a battery backup operation stop command is externally applied, and the CBR determination circuit responds to the row address strobe signal / RAS and the column address strobe signal / CAS in response to the state change. 12 sets the CBR signal to "L" level, and the counting operation of the counter 14 is stopped.
In response, the counter 14 sets the control signal BBU1 to "L".
The level is set and the output of the refresh cycle signal REFS1 is stopped. The control signal BBU1 is also given to the battery backup operation end determination circuit 15. The battery backup operation end determination circuit 15 controls the control signal BBU1.
Of the control signal BBUE
Is generated and applied to the ring oscillator circuit 16.
The ring oscillator circuit 16 generates a refresh cycle signal REFS2 for refreshing in the same cycle as the normal operation mode in response to the control signal BBUE. The counter 17 counts the cycle of the refresh cycle signal REFS2 generated by the ring oscillator circuit 16 and refreshes all memory cells (m).
Output of the control signal BBU2 is stopped (B
BU2 is set to "L" level). As a result, self-refreshing is completed, and then any normal operation can be performed. As shown in FIG. 3, the period during which the control signal BBU2 is “L” → “H” → “L”, that is, the internal refresh cycle by the refresh cycle signals REFS1 and REFS2 does not accept the operation from the outside.
Even if no operation is requested during this period, the semiconductor memory device can automatically perform refresh in substantially the same refresh cycle as the refresh cycle in the normal operation mode.

FIG. 4 is a circuit diagram of the CBR judging circuit 12 shown in FIG.
FIG. 5 is a circuit diagram showing an example, and FIG.
3 is a timing chart showing the operation of FIG. Referring to FIG. 4, the CBR determination circuit 12 includes inverters 12a and 12b.
And 12c, and NAND gates 12d and 12e forming a latch circuit.

The operation of the CBR determination circuit 12 will be described with reference to FIG. Inverter 12a inverts column address strobe signal / CAS and applies it to one input terminal of NAND gate 12d, and inverter 12b inverts row address strobe signal / RAS and applies it to one input terminal of NAND gate 12e. As shown in FIG. 5A, when the column address strobe signal / CAS falls earlier than the row address strobe signal / RAS, the output signal B of the NAND gate 12d becomes "L" level and the NAND gate 12e. Output signal becomes "H" level. Therefore, the output signal CBR signal of the CBR determination circuit 12 becomes "H" level. After that, even if the row address strobe signal / RAS falls, the CBR signal maintains "H" level as long as the column address strobe signal / CAS is "L" level.

On the other hand, as shown in FIG. 5B, when the row address strobe signal / RAS falls first,
The output signal A of the NAND gate 12e becomes "L" level and the output signal B of the NAND gate 12d becomes "H" level. After that, even if / CAS falls, the CBR signal is maintained at "L" level. In this way, CB
The R determination circuit 12 can determine / CAS before / RAS.

FIG. 6 is a circuit diagram showing an example of the ring oscillator circuit 13 shown in FIG. FIG. 7 is a timing chart showing the operation of the ring oscillator circuit 13. Ring oscillator circuit 1 with reference to FIGS. 6 and 7.
3 is a multi-stage inverter 13a and a NAND gate 1
3b and. NAND gate 13b has its input terminal connected to receive the CBR signal, and the other input terminal connected to receive output signal S7 of final stage inverter 13a. The output terminal of the NAND gate 13b is connected to the input of the cycle counter 14 and the inverter 1 of the first stage.
It is connected to the input of 3a. By connecting a plurality of inverters 13a in cascade between the output terminal and the input terminal of the NAND gate 13b, the refresh cycle signal RE
The cycle of FS1 can be set to a predetermined cycle. Also,
The NAND gate 13b can start an oscillation operation in response to the CBR signal.

The n-stage counter 14 is a ring oscillator.
2 of the cycle of the output signal S1 of the circuit 13 ^n-1Detect up to twice
be able to. For example, in the ring oscillator circuit 13,
If one cycle of the output signal S1 is 8 μs, the counter 14
The refresh cycle signal REF
S1 can be generated every 128 μs,
A resh period of 128 μs is satisfied.

FIG. 8 is a circuit diagram showing an example of one stage of the n-stage counter circuit 14 shown in FIG. Figure 9
FIG. 9 is a timing chart for one stage of the counter circuit shown in FIG. Referring to FIG. 8, this counter circuit is
The NMOS transistors 14a to 14e and the inverter 1
4n, 14m and 14p.

Referring to FIG. 9, CBR and / CBR are C
The output signal of the BR determination circuit 12, S1 and / S1
Is an output signal of the ring oscillator circuit 13. IT
N and TN are outputs of the first stage of the counter circuit 14.

In operation, when the CBR signal and the / CBR signal are at "H" and "L" levels, respectively, N
An "H" level signal is applied to the gate electrodes of MOS transistors 14a, 14g and 14h. On the other hand, N
An "L" level signal is applied to the gate electrodes of the MOS transistors 14b, 14f, 14e. When both the node and the signal S1 are at "H" level, the nodes are NMOS transistors 14k, 14i and 14g.
Is connected to the ground node and is pulled out to the "L" level. On the other hand, when both the node and the signal / S1 are at the "H" level, the node is the NMOS transistor
It is connected to the ground node by j and 14k and pulled to the "L" level. Since the force for extracting the "H" level to the "L" level is designed stronger than the latch circuit formed by the inverters 14m and 14n in FIG. 8, when the node becomes the "L" level, the node also becomes When the node goes to "H" level and goes to "L" level,
The node is set to "H" level. Since the counter at the first stage does not invert the latched signal even when the output / S1 of the ring oscillator becomes "H" when the nodes and are at "L" level, the counter outputs TN and ITN
Has a cycle twice that of the input signals S1, / S1.

By using the outputs TN and ITN of this counter as inputs to the counter of the next stage, the output is further increased by 2.
It can be counted as double, 4 times, 8 times.

In this way, the control signal BBU1 is once output at an arbitrary cycle (set to "H" level), and thereafter the control signal BBU1 is output until the self refresh mode is exited.
With BU1 kept at "H" level, the refresh cycle signal REFS1 can perform refresh of a fixed cycle.

The m-stage counter 7 shown in FIG. 1 has the same structure as the counter shown in FIGS. 8 and 9. However, the number of steps is different.

FIG. 10 is a circuit diagram of the battery backup operation end determination circuit 15 shown in FIG. 2, and FIG.
6 is a timing chart showing the operation of the battery backup operation end determination circuit 15. Referring to FIG. 10, determination circuit 15 includes inverters 15a and 15d and N
AND gates 15b and 15c are included.

In operation, the output signal B of the counter 14
When BU1 is at the "H" level (during battery backup operation), the NAND gate 15c outputs "L". Therefore, control signal BBUE is at "L" level regardless of the state of row address strobe signal / RAS. When the control signal BBU1 becomes "L" level, NA
The output of the ND gate 15c becomes "H" level, and the NAN
Since the output of the D gate 15b becomes "L" level, the control signal BBUE becomes high level. This control signal BBUE
Is the battery backup operation end signal.

In the semiconductor memory device shown in FIG.
Although the internal refresh cycle is switched by external / RAS, it may be switched by other means (for example, external / CAS), and the same effect can be obtained.

Embodiment 2 FIG. 12 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention. The difference between the self-refresh circuit shown in FIG. 2 and the self-refresh circuit shown in FIG. 1 is that the ring oscillator circuit 16 is deleted.
The ring oscillator circuit 13 is connected to the first ring oscillator 1
31 and the second ring oscillator 132. That is, the signal φS2 extracted from a part of the ring oscillator circuit 13 is counted by the counter 17.

In operation, the battery backup operation end determination circuit 15 provides the output signal φS2 of the first ring oscillator 131 to the m-stage counter 17 in response to the control signal BBU1. The counter 17 counts the cycle of the signal φS2 input through the CBR determination circuit 15, counts the number of times (m times) in which this cycle refreshes all the memory cells, and then the control signal BBU2 for shifting to the normal operation mode. Is output.

Embodiment 3 FIG. 13 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention. FIG. 14 is a circuit diagram showing an example of output buffer 28 'shown in FIG.
The semiconductor memory device shown in FIG. 13 is different from the semiconductor memory device shown in FIG. 1 in that an output for outputting information indicating that the refresh operation is completed by a refresh cycle signal REFS2 having a short cycle in response to a control signal BBU2. That is, the buffer 28 'is provided.

Referring to FIG. 14, output buffer 28 '.
Includes an OR gate 41 and NMOS transistors 42 and 43. The OR gate 41 has one input terminal connected to receive the data output signal D from the sense refresh amplifier input / output control circuit 26, the other input terminal connected to receive the control signal BBU2, and the output terminal thereof. It is connected to the gate electrode of the NMOS transistor 42. The source electrode of the NMOS transistor 42 is connected to the power supply terminal Vcc, and the drain electrode thereof is connected to the output terminal Q together with the drain electrode of the NMOS transistor 43. The NMOS transistor 43 has a gate electrode connected to receive the data output signal / D, and a source electrode connected to the ground terminal GND.

Next, the operation will be described. When the self-refresh operation is performed, both data output signals D and / D are set to "L" level. Therefore, the control signal BBU
When 2 is at "L" level, the NMOS transistor 4
Both 2 and 43 are turned off, and the output terminal Q is in a high impedance state. Control signal BBU2 is "L" →
Since the NMOS transistor 42 is turned on from the time of becoming "H", the signal appearing at the output terminal Q becomes "H" level, and becomes "H" level until the signal BBU2 changes from "H" to "L" level. Retained. As a result, whether or not refreshing has been performed for all memory cells can be performed by monitoring the output signal of the output terminal Q. That is, it can be seen that the self-refresh operation is completed when the signal appearing at the output terminal Q changes from "H" level to high impedance. Further, when the control signal BBU2 is at the "L" level, when the data is read, the data output signal D is "H", and when the inverted signal / D thereof is "L", the signal at the output terminal Q is "H". Becomes Control signal BBU
When 2 is the "L" level, the data output signal D is "L", and when the inverted signal / D is "H", the output terminal Q
The signal appearing at is "L". When the output is prohibited as in the write cycle, both the data output signal D and its inverted signal / D are set to the "L" level to put the output terminal Q in the high impedance state.

Embodiment 4 FIG. 15 shows another example of the output buffer 28 'shown in FIG.
It is a circuit diagram which shows one example. The difference between the output buffer 28 'shown in FIG. 15 and the output buffer shown in FIG. 14 is that the output terminal of the OR gate 41 is connected to the gate electrode of the NMOS transistor 43.

That is, the output buffer 2 shown in FIG.
8'knows the end of the refresh operation by the refresh cycle signal REFS2 when the level of the output terminal Q changes from "H" to high impedance.
The output buffer 28 'shown in FIG. 15 can know the end of the refresh operation by the refresh cycle signal REFS2 when the level of the output terminal Q becomes "L" high impedance.

In the embodiment shown in FIGS. 14 and 15,
Although the data output terminal Q is used, it is also possible to use an input / output terminal which is not used during the self refresh operation. Examples of this input / output terminal are address signal input terminals A0 to A10, write control signal input terminal / W,
There is an output control signal input terminal / OE.

Embodiment 5 FIG. 16 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention. FIG. 17 is a circuit diagram of the logic circuit 32 shown in FIG.

The semiconductor memory device shown in FIG. 16 and FIG.
2 is different from the conventional semiconductor memory device shown in FIG. 1 in that the substrate potential generating circuit 31 is controlled by the control signals BBU1 and BBU2.
That is, a logic circuit 32 is provided for controlling by.

Referring to FIG. 17, logic circuit 32 includes an inverter 321 for inverting internal row address strobe signal / RAS, an inverter 322 for inverting control signal BBU2, and an OR gate 323. OR gate 3
One input terminal of 23 is connected to the output of the inverter 321, the other input terminal is connected to receive the control signal BBU1, and the output terminal thereof is connected to the substrate potential generating circuit 31. The output terminal of the inverter 322 is connected to the substrate potential generation circuit 31.

Next, the operation of the logic circuit 32 will be described. When the battery is backed up, the control signal BBU1 is "H".
Then, the OR gate 323 outputs "L" level to deactivate the substrate potential generating circuit 31. Thereby, the power consumption can be reduced.

Next, when the battery backup operation is completed and the control signal BBU1 becomes "L" level, the control signal BBU2 becomes "H" level at the same time, and the substrate potential generating circuit 31 is activated. As a result, the transition from the battery backup operation end to the normal operation mode can be smoothly performed.

In the conventional semiconductor memory device, the substrate potential generation circuit 31 cannot be activated until the row address strobe signal / RAS becomes "L" level again after the self-refresh operation at the time of battery backup. It was

Next, the reason why there is no problem even if the substrate potential generating circuit 31 is deactivated during battery backup will be described. The substrate potential generation circuit 31 generates a substrate potential for the following purpose.

Prevention of destruction of memory cell data caused by injection of electrons from the input terminal to the substrate due to undershoot of the input waveform, speeding up the circuit by reducing the PN junction capacitance formed at each activation of the substrate and the internal circuit. Speeding up and stabilizing the operating circuit by reducing the substrate effect of the threshold voltage Vth of the transistor During self-refresh, since the DRAM is in the non-operating state and the current consumption is low, the input does not change, so that the above-mentioned undershoot problem occurs. Does not occur. Further, especially for speeding up, since refresh is internally performed in a long cycle, there is no particular problem with respect to and above. In addition, since circuits relating to high-speed access are not involved in the battery backup operation, there is no problem even if these circuits are deactivated to reduce power consumption.

[0065]

According to the first aspect of the invention, the first periodic signal is generated during the battery backup operation, and is shorter than the first periodic signal when the battery backup operation is completed and the normal operation mode is entered. Since the second cycle signal of the cycle is automatically generated, it is not necessary to apply an external signal such as / RAS only refresh before shifting to the normal operation mode as in the conventional example. As a result,
System design restrictions can be eliminated.

According to the fourth aspect of the present invention, since the completion information of the self-refresh operation can be output to the outside of the semiconductor memory device, the external device can use this information as a ready / busy signal.

According to the fifth aspect of the invention, during the battery backup operation, the power consumption can be reduced by deactivating the circuits not involved in the battery backup operation. Further, the circuit inactivated during the battery backup operation is immediately activated so that the normal operation state is immediately obtained after the battery backup is completed.
As a result, the transition to the normal operation mode can be smoothly performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a self-refresh circuit of the semiconductor memory device shown in FIG.

3 is a timing chart of the self-refresh circuit shown in FIG.

4 is a circuit diagram showing an example of a CBR determination circuit 12 shown in FIG.

5 is a timing chart showing an operation of the CBR determination circuit shown in FIG.

FIG. 6 is a circuit diagram showing an example of the ring oscillator circuit shown in FIG.

7 is a timing chart showing an operation of the ring oscillator circuit shown in FIG.

8 is a circuit diagram of one of the n-stage and m-stage counter circuits shown in FIG.

9 is a timing chart of one stage of the counter circuit shown in FIG.

10 is a circuit diagram showing an example of a battery backup operation end determination circuit shown in FIG.

11 is a timing chart showing the operation of the battery backup operation end determination circuit shown in FIG.

FIG. 12 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 13 is a block diagram showing still another embodiment of the semiconductor memory device according to the present invention.

14 is a circuit diagram showing an example of the output buffer shown in FIG.

FIG. 15 is a circuit diagram showing another example of the output buffer shown in FIG.

FIG. 16 is a block diagram showing still another embodiment of the semiconductor memory device according to the present invention.

17 is a circuit diagram showing an example of the logic circuit shown in FIG.

FIG. 18 is a block diagram of a conventional semiconductor memory device having a self-refresh function.

19 is a timing chart for explaining the self-refresh operation of the semiconductor memory device shown in FIG.

20 is a block diagram of the self-refresh circuit shown in FIG. 18, viewed from the operation side.

21 is a block diagram showing an example of a substrate potential generation circuit 31 shown in FIG.

[Explanation of symbols]

 12 CBR determination circuit 13 ring oscillator circuit 14 n-stage counter 15 battery backup operation end determination circuit 16 ring oscillator circuit 17 m-stage counter 30 self-refresh circuit 30a first periodic signal generation circuit 30b second periodic signal generation circuit 28 'output Buffer 32 logic circuit

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[Procedure amendment]

[Submission date] May 18, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 18 is a block diagram showing a conventional semiconductor memory device. Referring to FIG. 18, this DRAM 21
Is a memory cell array 22 having 4,194,304 memory cells arranged in rows and columns, and a row decoder 2 for selecting a word line in the memory cell array 22.
4, a column decoder 25 for selecting a column of memory cells to be accessed, an address buffer 23 receiving an address signal provided by dividing manner when the external input and the bit line in the memory cell array 22 buffer 27 And a sense refresh amplifier input / output control circuit 26 for selectively connecting to and output buffer 28.
In FIG. 16, the line 21 also indicates the semiconductor substrate.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

In operation, / CAS before / RAS
Row address strobe signal / RAS
A signal is transmitted from the CBR determination circuit 12 to the ring oscillator circuit 13 and the counter 14 when
Oscillation of the internal periodic signal REFS and the count begins.
When the counter 14 counts n internal cycles, the counter outputs the control signal BBU. Therefore, the control signal BBU of the ring oscillator circuit is
It is output at a cycle that is n times the oscillation cycle .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

Further, as described above, there is a problem that the substrate potential VBB cannot be generated until the internal / RAS signal becomes the " L " level again after the self refresh operation is completed.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

The first periodic signal generating circuit 30a is connected to receive the row address strobe / RAS and the column address strobe signal / CAS, and / C AS before
/ R AS and row address strobe signal RAS becomes 1
When the “L” level is maintained for 00 μsec or more, the control signal BBU1 for performing the battery backup control is generated and the refresh cycle signal REFS1 is generated.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

The circulation cycle of the refresh cycle signal REFS1 is as long as possible (for example, 128 μs) within a range in which the data signal held in the memory cell is not lost.
is set to ec), the circulation period of the refresh cycle signal REFS2 is set to the normal operation mode is substantially the same period (for example, 200 nsec).

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

Next, the operation of the self-refresh circuit 30 shown in FIGS. 1 and 2 will be described with reference to FIG. First, the CBR determination circuit 12 uses / CAS before / RAS
And row address strobe signal / RAS is 100μ
CBR is detected when it is at "L" level for more than sec
A signal is generated and applied to the ring oscillator circuit 13. Ring oscillator circuit 13 generates an internal signal φS1 in response to the CBR signal and applies it to counter 14.
This internal signal φS1 corresponds to the cycle of the self-refresh cycle signal REFS1 in the battery backup operation. The counter 14 counts the cycle of the internal signal φS1 by an integer number of times n, generates a control signal BBU1 for performing a battery backup operation, and n times the internal signal φS1 generated by the ring oscillator circuit 13.
To the clock signal generation circuit 29 as the refresh cycle signal REFS1. In this way, the refresh operation for battery backup by the long cycle signal can be performed.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

In operation, when the CBR signal and the / CBR signal are at "H" and "L" levels, respectively, N
An "H" level signal is applied to the gate electrodes of MOS transistors 14a, 14g and 14h. On the other hand, N
An "L" level signal is applied to the gate electrodes of the MOS transistors 14b, 14f, 14e. When both the node and the signal / S1 are at the "H" level, the node becomes the NMOS transistors 14k, 14i and 14
It is connected to the ground node by g and pulled to the "L" level. On the other hand, when both the node and the signal / S1 are at the "H" level, the nodes are the NMOS transistors 141 and 1
Connected to the ground node by 4j and 14k, and "L"
Be drawn to a level. Since the force for extracting the "H" level to the "L" level is designed stronger than the latch circuit formed by the inverters 14m and 14n in FIG. 8, when the node becomes the "L" level, the node also becomes When the node goes to "H" level and goes to "L" level,
The node is set to "H" level. Since the counter at the first stage does not invert the latched signal even when the output / S1 of the ring oscillator becomes "H" when the nodes and are at "L" level, the counter outputs TN and ITN
Has a cycle twice that of the input signals S1, / S1.

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (6)

[Claims] 1. A semiconductor memory device comprising a memory cell array in which volatile memory cells are arranged in an array, and having a self-refresh function for refreshing data held in the memory cells by a periodic signal generated internally. Detecting means for detecting a battery backup operation start instruction and a battery backup operation stop instruction based on a logical state of a state control signal for controlling a storage state of the semiconductor memory device; and the detected battery backup operation start instruction. In response to the first cycle signal generating means for generating a first cycle signal for holding the data in the memory cell, the first cycle in response to the detected backup operation stop command. Second periodic signal generating means for generating a second periodic signal having a shorter period than the signal; It is characterized by including self-refresh operation stopping means for counting the cycle of the second periodic signal and stopping the self-refresh operation when the cycle of the second periodic signal reaches the number of times of refreshing all the memory cells. Semiconductor memory device. 2. The state control signal includes a row address strobe signal and a column address strobe signal, and the start command of the battery backup operation is such that the column address strobe signal falls prior to the row address strobe signal. 2. The semiconductor memory device according to claim 1, wherein the stop command for the battery backup operation is a state in which a row address strobe signal and a column address strobe signal that have fallen once rise. 3. The semiconductor memory device according to claim 1, wherein the period of the second periodic signal is substantially the same as the refresh period in the normal operation mode. 4. A semiconductor memory device comprising a memory cell array in which volatile memory cells are arranged in an array, and having a self-refresh function for refreshing the data held in the memory cells with a periodic signal internally generated, Detecting means for detecting a battery backup operation start instruction and a battery backup operation stop instruction based on a logical state of a state control signal for controlling a storage state of the semiconductor memory device; and through the detected battery backup operation start instruction , A first for holding data of said memory cell
And a second periodic signal generating means for generating a second periodic signal having a shorter period than the first periodic signal in response to the detected battery backup operation stop command. Cycle signal generating means for counting the cycle of the generated second cycle signal, and when the cycle of the second cycle signal reaches the number of times of refreshing all the memory cells, the self-refresh operation is stopped and self-refresh operation is performed. Refresh operation stopping means for generating a refresh end signal; detecting completion of the self refresh operation based on a logical state of the generated self refresh end signal and a logical state of data output from the memory cell array; A semiconductor memory device comprising: output means for outputting a signal to the outside of the semiconductor memory device. 5. The semiconductor memory device according to claim 1, wherein in response to a battery backup start command detected by said detection means, a circuit not involved in battery backup is deactivated and said detection is performed. A semiconductor memory device comprising: an active state control means for activating the inactivated circuit in response to a battery backup operation stop command detected by the means. 6. The semiconductor memory device according to claim 5, wherein the circuit not involved in the battery backup includes at least a substrate potential generation circuit.