JPH0622274B2 - Semiconductor integrated circuit device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a bipolar transistor and a complementary MIS.
It relates to the technology of forming FET and the same substrate,
For example, it relates to a technique effective in forming a bipolar transistor and a CMOS element on the same silicon substrate.

[Background Art] A semiconductor integrated circuit device (hereinafter referred to as an IC) having a complementary MISFET is excellent in that the operation time is shortened and the power consumption is reduced, while it is used for driving another IC. There is a drawback that the driving ability is low.

Therefore, as a method for solving such a problem, there is known a method of mixing complementary MISFETs and bipolar transistors on the same substrate (for example, Japanese Patent Laid-Open No. Sho 5).
4-131887). In this type of mixed type IC, each element is formed in a second conductive type semiconductor layer, for example, an N type silicon layer epitaxially grown on a first conductive type semiconductor substrate, for example, a P type silicon substrate. To be done.

By the way, the epitaxially grown semiconductor layer is generally formed to have a thickness of, for example, about 5 to 6 μm or more from the viewpoint of reducing the drain capacitance of the MISFET and preventing so-called punch-through. Therefore, the performance of the bipolar transistor in the mixed type IC, in particular, the cutoff frequency f _T is lower than that of the IC in which only the bipolar element is formed,
The inventor has found that the operating speed is reduced.

On the other hand, in this type of IC, in order to improve the reliability of each element, it is necessary to completely electrically separate the bipolar transistor from the complementary MISFET on the same substrate and to improve the latch-up breakdown voltage. Is considered to be.

[Object of the Invention] An object of the present invention is to provide a bipolar transistor and a complementary M
It is an object of the present invention to provide a technique for improving the integration degree of a semiconductor device in which ISFETs are formed on the same substrate.

Another object of the present invention is to provide a technique for increasing the cut-off frequency f _T of a bipolar transistor and increasing the operating speed of an element in an IC having a bipolar transistor and a complementary MISFET on the same substrate.

Another object of the present invention is to provide a technique capable of completely isolating elements from each other in an insulator isolation region in a similar IC and reliably preventing latch-up.

Another object of the present invention is to provide a technique for improving the α-ray resistance strength in the same IC.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed herein will be briefly described as follows.

That is, a bipolar transistor and a complementary MI are provided in an epitaxially grown semiconductor layer provided on one surface of a semiconductor substrate.
In an IC that forms an SFET, a high-concentration semiconductor region that forms a collector region of a bipolar transistor is provided at an interface between an epitaxially grown semiconductor layer and a semiconductor substrate in a region where a bipolar transistor is formed, and an N-channel type MISFET is formed. that provided a high-concentration semiconductor region of the P ⁺ -type interface between the P-type well region and the semiconductor substrate, N ⁺ -type interface between the N-type well region and the semiconductor substrate of the MISFET of P-channel type is formed A high-concentration semiconductor region, an insulator isolation region having a depth reaching the semiconductor substrate is provided at the boundary of each region where these elements are formed, and the region where the collector contact portion of the bipolar transistor is formed and the base. An isolation region having a depth reaching the high-concentration semiconductor region at the boundary with the region where the region is formed Provided, it is intended to terminate the collector, a base junction with the separation region and the insulator isolation region.

[Embodiment] FIG. 1 is a sectional structural view showing a most preferred embodiment of the present invention.

On one surface of the P-type silicon semiconductor substrate 1, the N ⁻ -type epitaxially grown silicon semiconductor layer 2 (as described above,
The thickness of the semiconductor layer 2 is close to the thickness of the epitaxial layer in a normal bipolar type IC, for example, 1 to 2 μm.
m) is formed on the semiconductor layer 2.
Impurities are introduced by the formation of the N-type well region 3 and the P-type well region 4. These well regions 3,
Reference numeral 4 is a portion where a complementary MISFET, for example, a CMOS device is to be formed. A P-channel type MOSFET is formed in the N-type well region 3, and an N-channel type MOSFET is formed in the other P-type well region 4. Prior to the epitaxial growth, an N ⁺ -type impurity semiconductor region 5 is formed in advance in a high concentration of an N-type impurity such as antimony in a portion of the surface of the semiconductor substrate 1 where a bipolar transistor is to be formed. ing. The N ⁺ -type impurity semiconductor region 5 constitutes the collector region of the bipolar transistor.

Insulator isolation regions 6 are formed at the portion where the N ⁺ -type impurity semiconductor region 5 is present and at each boundary between the N-type well region 3 and the P-type well region 4. The insulator isolation region 6 is composed of a groove 7 and an insulator 8 filling the groove 7,
The width of the groove 7 is, for example, about 3 μm. Further, the depth of the groove 7 penetrates the epitaxial growth layer 2 and reaches the substrate 1, and the insulator isolation region 6 is the N ⁺ -type impurity semiconductor region 5.
(And the area above it), and each well area 3, 4
Are completely separated. For formation of the groove 7, it is preferable to use reactive ion etching which hardly causes side etching. Moreover, polysilicon, silicon dioxide, or the like can be used as the insulator 8, and in particular, the insulation is completed by forming an oxide film 9a by thermal oxidation on the inner surface of the groove 7. When polysilicon is used as the insulator 8, silicon nitride is used as the buffer layer.
It is preferable to interpose the (Si ₃ N ₄ ) film 9b. The groove 7
And after forming the oxide film 9a, a chemical vapor deposition method (CV
It is also possible to form a P ⁺ -type region (not shown) as a channel stopper at the bottom of the groove 7 by ion implantation before the filling process of the insulator 8 by the (D method) or the like.

In each of the regions separated as described above, the bipolar transistor 10, the P-channel type MOSFET 11 and the N-channel type MOSF are formed by the same technique as the conventional technique.
ET12 is formed respectively. The bipolar transistor 10 includes a P-type base region 13 and an N ⁺ -type emitter region 14 in addition to a collector region composed of an N ⁺ -type impurity semiconductor region 5, and each region is ohmic-contacted with an electrode (not shown) through an opening. ing. In this case, the base region 13 and the N ⁺ -type collector contact portion 15 are separated by the isolation region 60 having the same structure as the insulator isolation region 6, so that the breakdown voltage between the collector and the base is improved. There is. Further, a polysilicon layer 16 is provided as an electrode underlayer on the emitter region 14 so as to make the emitter shallow.

On the other hand, MOSFETs 11 and 12 are P ⁺ type or N ⁺ type source and drain regions 17 and 18, respectively;
0 and gate electrodes 21 and 22 respectively. Each of the gate electrodes 21 and 22 is located on a thin gate oxide film (SiO ₂ film) 23 having a thickness of about 35 nm, and is composed of the lower polysilicon layers 21a and 22a and the upper molybdenum silicide (MoSi ₂ ) layers 21b and 22b. Become. Although not shown, a passivation film of phosphosilicate glass or the like is formed on the surface of each such element, and then a predetermined hole is formed in the film to form a metal wiring of aluminum or the like. Finally, a final passivation film is formed to complete the device.

According to this method, the epitaxially grown semiconductor layer 2 can be formed thin, the f _{T of the} bipolar transistor can be increased, the speed can be increased, and at the same time, since the U groove is formed, element isolation is complete and latch-up can be prevented. Together with this, the degree of integration is improved.

In the embodiment described above, an example was mainly focused on improving the performance of the bipolar transistor 10. However, as shown by a chain double-dashed line in the figure, the lower part of the N-type well region 3, that is, the substrate 1 It is possible to form the N ⁺ -type high-concentration impurity semiconductor region 50 and the P ⁺ -type high-concentration impurity semiconductor region 40 at the interface with the epitaxial layer 2. The high-concentration region 50 may be formed at the same time as the N ⁺ type region 5 in the bipolar transistor portion, and the region 40 may be formed in self-alignment with the regions 5 and 50. A new mask is added only by changing the mask. Can be easily formed without. Then, the P-channel and N-channel MOSFETs have a so-called degenerate structure, the α-ray resistance can be increased, the soft error due to the α-rays can be prevented, and the reliability of the IC can be increased.

[Effect] Since the epitaxially grown semiconductor layer 2 of the bipolar transistor can be formed thin and f _T is increased, high speed operation is improved.

Since the respective elements are completely separated by the insulator separation region, latch-up can be surely prevented. Moreover, since the insulating material isolation region has a groove-buried structure, the area occupied by that portion can be reduced and the degree of integration can be greatly improved.

The high-concentration impurity semiconductor region of the N ⁺ type at the bottom of the N-type well region, providing a high concentration impurity semiconductor regions of P ⁺ type in the lower part of the P-type well region, since taking a so-called degeneration structure, The strength of α-ray resistance is improved, and a highly reliable device can be obtained. Further, the same structure also improves latchup.

By terminating the collector / base junction of the bipolar transistor in the isolation region and the insulator isolation region, the breakdown voltage can be improved.

Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. For example, molybdenum silicide 21b, 2
2b may be another silicide (platinum silicide or the like).

[Brief description of drawings]

The accompanying drawings are cross-sectional structural views showing an embodiment of the present invention. 1 ... Semiconductor substrate, 2 ... Epitaxial growth semiconductor layer, 3 ... N-type well region, 4 ... P-type well region, 4
0 ... P ⁺ type high-concentration impurity semiconductor region, 5, 50 ...
... N ⁺ -type high-concentration impurity semiconductor region, 6, 60 ... Insulator isolation region, 7 ... Groove, 8 ... Insulator, 9a ... Oxide film, 9b ... Silicon nitride (Si ₃ N ₄ ) Membrane, 1
0 ... Bipolar transistor, 11 ... P-channel type MISFET (MOSFET), 12 ... N-channel type MISFET (MOSFET), 13 ... P-type base region, 14 ... Emitter region, 15 ... N-type collector Contact part, 16 ... Polysilicon layer, 17, 18 ... P
⁺ Type source / drain layers, 19, 20 ... N ⁺ type source / drain layers 21, 22 ... Gate electrodes, 21a,
22a ... Polysilicon layer, 21b, 22b ... Molybdenum silicide layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication part H01L 29/73 (72) Inventor Shinji Nakajima 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Device In the development center (72) Inventor Katsumi Ogigami 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Inside the device development center, Hitachi, Ltd. (56) Reference JP-A-56-169359 (JP, A) JP-A-57-180146 (JP, A) JP-A-57-204144 (JP, A)

Claims (2)

[Claims] 1. A semiconductor integrated device comprising a first-conductivity-type semiconductor substrate provided on one surface thereof with a second-conductivity-type epitaxial growth semiconductor layer of the opposite conductivity type, and a bipolar transistor and a complementary-type MISFET formed in the epitaxial-growth semiconductor layer. In the circuit device, a high-concentration semiconductor region of a second conductivity type, which constitutes a collector region of the bipolar transistor, is provided at an interface portion between the epitaxial growth semiconductor layer and the semiconductor substrate in a region where the bipolar transistor is formed, and the complementary type semiconductor device is provided. A high-concentration semiconductor region of the first conductivity type is formed at the interface between the well region of the first conductivity type in which the second conductivity type MISFET is formed and the semiconductor substrate of the epitaxially grown semiconductor layer in the region for forming the MISFET. And a second conductivity type wafer on which a first conductivity type MISFET is formed. A second-conductivity-type high-concentration semiconductor region is provided at an interface between the region and the semiconductor substrate, and a region where the bipolar transistor is formed, a region where the first-conductivity-type MISFET is formed, and the second-conductivity type M
An insulator isolation region including a trench having a depth that penetrates the high-concentration semiconductor region and reaches the semiconductor substrate and an insulator that fills the trench is provided at each boundary of regions where ISFETs are formed, and A groove having such a depth as to reach the high-concentration semiconductor region is formed at a boundary portion between a region where the collector contact portion is formed and a region where the base region is formed in the region where the bipolar transistor is formed. Providing a separation region consisting of an insulator to be buried,
A semiconductor integrated circuit device characterized in that the collector and base junctions are terminated by the isolation region and the insulator isolation region. 2. The semiconductor integrated circuit device according to claim 1, wherein the epitaxially grown semiconductor layer has a thickness of about 1 to 2 μm.