JPH06222099A - Load abnormality detection circuit - Google Patents

Abstract

PURPOSE:To miniaturize a surge absorption means of a load abnormality state detection circuit for detecting an abnormality state of load power-energized by connecting it to a power source and with conduction of a drive switch. CONSTITUTION:Voltage VL produced at both ends of load 2 at the time when a drive switch 3 is shut off is used as an object at the time of open detection. First constant current I13 and second constant current I12 are allowed to flow in detection lines L1, L2 separately, a first detection level V11 and a second detection level V12 are produced on the basis of potential differences R13, R13, given to a differential input circuit 14, the second detection level V12 are lowered and an open state of the load 2 is detected by means of the state where the voltage VL is more than reference voltage R13.I13. Treatment can be performed for invasion surge in an input clamp circuit 8 of a small capacity by surge attenuation action of first resistance R1 and second resistance R2 and miniaturization and cost reduction can be contrived.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load abnormal state detecting circuit, and more particularly to a load abnormal state detecting circuit for detecting an open state or a short state of a load.

[0002]

2. Description of the Related Art For example, loads such as various actuators and motors of automobiles are driven by turning on / off a drive switch connected in series with the load. Normally, these loads are connected to each other via a wiring harness, which is the wiring inside the vehicle.However, in addition to the long wiring section, stress such as vibration and temperature is applied, the load including the above wiring becomes open, and an accident occurs. It may develop into a trouble to be connected. Therefore, in order to prevent such troubles, a load abnormal state detection circuit for detecting that the load is in an open state is provided.

A typical prior art is shown in FIG.
A series circuit including a load 51 such as an actuator to be detected and a drive switch 52 is connected between the power supply line L51 and the ground line L52. The power supply line L51 is connected to the positive electrode of the in-vehicle battery BAT via the ignition switch IGSW, and the negative electrode is the ground line L
It is connected to 52. A detection line L53 is connected to a connection point between the load 51 and the drive switch 52, and the detection line L53 is connected to a load abnormal state detection circuit (hereinafter referred to as a detection circuit) via the detection input terminal A of the load abnormal state detection circuit 61. It is connected to the inverting input terminal of the comparator 62 which constitutes 61. The power supply line L51 is connected to the power supply terminal B of the detection circuit 61, the ground line 52 is connected to the ground terminal G, and the detection circuit 61 is supplied from the battery BAT via the terminals B and G. Power supply voltage V
Powered by b.

A detection resistor R is connected between the detection line L53 and the ground line L52. Since the detection resistor R is connected in series with the load 51 when the drive switch 53 is cut off, the power supply voltage Vb is divided into the voltages V51 and V52 by the load 51 and the detection resistor R. The voltage V51 is input to the inverting input terminal of the comparator 62, and the reference voltage Vref is applied to the non-inverting input terminal. Reference voltage Vre
f is a threshold level for discriminating the voltage V51 and is realized by, for example, a resistor and a constant current circuit (not shown). If the load 51 is normal when the drive switch 52 is in the cutoff state, the normal V51 is changed to V51 (N).
And

[0005]

[Equation 1]

It is constant. Generally, the detection resistor R is a load 51.
Since the resistance value of RL is set to R >> RL, V51 (N) ≈0 (2).

Here, if the reference voltage Vref is set to a value (Vref> V51 (N)) to be determined to be abnormal in advance, the output of the differential amplifier 52 is 0 level when the load 51 is normal, and thus the load 51 is set. Is judged to be normal. On the other hand, if the load 51 is in an open state or a high resistance state for some reason, V51> Vref, and the differential input circuit 62 outputs a high level detection output V
out is derived. As a result, the open state of the load 51 is detected.

[0008]

However, in the above-described detection circuit 61 according to the prior art, since the detection line L53 is directly connected to the detection circuit 61 from the load 51, the surge occurs via the power supply line L51 and the detection line L53. There is a problem that noise enters and the integrated circuit element and the semiconductor element are destroyed. In addition, there are many inductive loads such as solenoids and motors in the load, and the load and the drive switch are generally arranged apart from each other, and a wire harness composed of many wiring bundles and the like are interposed between them over a long section. The wiring path is inductive, and positive and negative surge noises such as load dump and field decay easily occur with the opening and closing of the load, and the generated surge easily enters the detection circuit 61 without being attenuated, and the withstand voltage is increased. Destroy low circuit elements. In order to prevent such a surge failure, a method of connecting a surge absorption element such as a Zener diode to the power supply line has been adopted, but it requires a large power element such as a power Zener diode, which reduces the cost. Problems such as upsizing and large-scale configuration are occurring.

The present invention has been made in view of the above problems, and its purpose is to prevent a failure due to a surge,
It is to realize and provide a load abnormal state detection circuit capable of detecting an open state of a load with a new configuration.

[0010]

SUMMARY OF THE INVENTION The present invention provides a circuit for detecting an abnormal state of a load, one end of which is connected to one end of a power supply and the other end of which is connected to the other end of the power supply via switching means. A first resistor whose one end is connected to one end of the load, a second resistor whose one end is connected to the other end of the load, and an emitter which is connected to the other end of the first resistor and whose base is predetermined. A first transistor set to one potential and an emitter connected to the other end of the second resistor, and a second base different from the first potential by a reference voltage determined in advance by the base.
A second transistor set to a potential, wherein an abnormal state of the load is detected when the voltage across the load becomes equal to or higher than the reference voltage when the switching means is cut off. It is a detection circuit.

Further, the present invention provides a circuit for detecting an abnormal state of a load, one end of which is connected to one end of a power source and the other end of which is connected to the other end of the power source through a switching means. A first resistor having one end connected to the second resistor, a second resistor having one end connected to the other end of the load, a third resistor having one end connected to the other end of the first resistor, and one input A differential input circuit connected to the other end of the third resistor, the other input connected to the second resistor, and energized with electric power via the first resistor, the third resistor and the differential input. A first constant current circuit connected between one input connection point of the circuit and the other end of the power supply, a connection point of the other input of the second resistor and the differential input circuit, and the other end of the power supply. A second constant current circuit connected between the switching means and An abnormal state of the load is detected when a product of a resistance value of the third resistor and a current value of the first constant current circuit is used as a reference voltage and a potential across the load becomes equal to or higher than the reference voltage. It is a load abnormal state detection circuit.

Further, according to the present invention, when the switching means is turned on, the potential of the disconnecting means for disconnecting the second constant current circuit, and the potential at the connection point between the other end of the second resistor and the other input of the differential input circuit, It is characterized by including a comparing means for detecting an abnormal state of the load when the potential at the connection point is higher than or equal to the reference potential as compared with a predetermined reference potential.

[0013]

The load abnormal state detection circuit according to the present invention is a detection circuit for detecting an abnormality of the load, one end of which is connected to one end of the power supply and the other end of which is connected to the other end of the power supply through the switching means. The detection circuit is formed by a pair of transistors, and the first resistance and the second resistance are interposed between the load and the detection circuit.
The first resistor has both ends connected to one end of the load and the emitter of the first transistor, and the second resistor has both ends connected to the other end of the load and the second end.
Each is connected to the emitter of the transistor. First
The base potential of the transistor is set to a predetermined first potential, and the base potential of the second transistor is set to a second potential different from the base potential of the first transistor by a predetermined reference voltage. When the voltage across the load becomes equal to or higher than the reference voltage when the switching means is cut off, it is detected that the load opens and becomes in an abnormal state. Therefore, the first interposing between the load to be detected and the detection circuit
Attenuating surges entering by the resistance and the second resistance,
Further, since the emitter potentials of the first transistor and the second transistor are fixed, intrusion surge can be clamped.

Further, in the load abnormal state detection circuit according to the present invention, the detection circuit is formed by a differential input circuit, the first resistance and the second resistance are interposed between the detection circuit and the load, and one end of each resistance is connected. The load is individually connected to each end, the other end of the first resistor is connected to one input terminal of the differential input circuit through the third resistor, and the other end of the second resistor is connected to the other end of the differential input circuit. Connect to the input terminal. Further, a voltage generated by flowing a first constant current by the first constant current circuit to the third resistor via the first resistor,
A reference voltage is applied to the one input terminal of the differential input circuit. The second constant current from the second constant current circuit is passed through the load to the second resistor, and the generated voltage is applied to the other input terminal. When the load is normal and the switching means is cut off, the potentials applied to both input terminals are kept equal. When the voltage across the load becomes equal to or higher than the potential of the one input terminal of the differential input circuit, the abnormal state due to the open of the load is detected. The first resistance and the second resistance interposed between the load and the detection circuit serve as an attenuation resistance against an inrush surge, and the surge absorption means of the detection circuit can have a small capacity.

Further, according to the present invention, the potential at the connection point between the other end of the second resistor and the other input terminal of the differential input circuit is compared with a predetermined reference potential when the switching means is conducting, and the connection point Since the comparison means for detecting the abnormal state of the load when the electric potential becomes equal to or higher than the reference potential is provided, the abnormal state due to the short circuit of the load can be detected together with the abnormal state due to the open state. Furthermore, since the disconnecting means is provided to disconnect the second constant current circuit, it is possible to improve the detection accuracy when detecting the abnormal state.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing the configuration of an abnormal load state detection circuit according to an embodiment of the present invention. A power supply voltage Vbat of an on-vehicle battery (not shown) is applied between the power supply line L0 and the ground line L8. The load 2 has one end connected to the power supply line L0 and the other end connected to a drive switch 3 which is a switching means, and the drive switch 3 is turned on to energize the power. One ends of a first resistor R1 and a second resistor R2 having the same resistance value are connected to both ends of the load 2, respectively. The other ends of the first resistor R1 and the second resistor R2 are connected to the first detection input terminal T1 of the load abnormality state detection circuit 1.
And the first detection line L via the second detection input terminal T2
It is individually connected to the first and second detection lines L2. The first detection line L1 is a PNP type and has the same characteristics,
The second detection line L2 is connected to the emitter of one of the paired first transistors Q1 and is connected to the other second transistor Q1.
2 emitters respectively connected. Detection line L1,
The pair of input clamp circuits 8 and 8 connected to L2 will be described later.

The base of the first transistor Q1 is connected via a line L3 to the positive side of a bias power source Ea realized by a constant voltage circuit or a voltage divider circuit (not shown), and a voltage Va, which is a predetermined first potential, is applied. Is being applied. A series circuit of a resistor R3 and a constant current circuit 4 is connected between both electrodes of the bias power source Ea, and a constant voltage drop R3 · I3 is generated across the resistor R3 by the constant current I3. As is apparent from FIG. 1, the resistor R3 is connected between the bases of the first transistor Q1 and the second transistor Q2,
A base voltage V3, which is a second potential different from the base voltage Va of the first transistor Q1 by V3 = Va−R3 · I3 (3), is applied to the base of the second transistor Q2.

A current mirror circuit 5 including a pair of NPN transistors Q3 and Q4 is connected to the collector of the first transistor Q1 and the collector of the second transistor Q2, and the transistor Q4 on the second transistor Q2 side is connected.
Is diode-connected, so transistor Q3
Collector current follows the collector current I2 flowing through the second transistor Q2.

The collector of the first transistor Q1 is connected to the base of the first-stage transistor Q5 of the amplifier circuit 6 via the line L4. The collector of the output transistor Q6 in the subsequent stage, which is generated from the power supply voltage Vb via a regulator (not shown) and is energized by the second power supply voltage Vcc, is connected to the detection output terminal T3 via the output line L5. ing.

The load abnormal state detection circuit 1 of the present embodiment configured as described above forms an open state detection circuit of the load 2 (hereinafter referred to as an open detection circuit), and its operation will be described below. . If the load 2 is not in the open state and is normal, the second current I2 expressed by the following equation flows from the second resistor R2 to the emitter of the second transistor Q2 through the second detection line L2.

I2 = {Vb−VL− (Va−R3 · I3 + Vbe)} / R2 (4) where Vbe is the base-emitter voltage of the transistor Q2. VL is a voltage generated across the load 2 by the second current I2 when the load 2 is normal. The second current I2 flows through the transistor Q4, and the current mirror circuit 5 causes the same current as the second current I2 to flow through the collector of the transistor Q3. On the other hand, the first detection line L1 has a first
The current I1 flows in via the first resistor R1. First current I
1 is I1 = {Vb− (Va + Vbe)} / R1 (5) This detection circuit detects an abnormality and the detection output logic is inverted when I1 = I2. Therefore, (4), (5 ), VL = R3 · I3 (6) That is, when the load voltage VL becomes equal to or higher than the reference voltage R3 · I3, the output becomes high level.

Here, when the load 2 is opened,
Since the level V2 of the second detection line decreases, the voltage VL
Rises to VL> R3 · I3. The operation of the detection circuit 1 at this time is such that when the load 2 is in the open state, the second current I2 is cut off, the transistor Q3 forming the current mirror circuit 5 is cut off, and the line L4 connected to the collector of the transistor Q3. The level rises and the amplification circuit 7
The transistor Q5 in the first stage is turned on and the output transistor Q6 in the next stage is turned off. Therefore, the load open detection output terminal T3 outputs the high level load open detection output Vout from the collector of the transistor Q6 through the detection output line L6, and it is detected that the load 2 is in the open state.

When Vb rises due to the surge of the power supply line, I1 and I2 increase from (4) and (5). The surge currents I1 (S) and I2 (S) are generated by the resistors R1 and R.
By increasing the value of 2, it can be suppressed to a small value, and it is not necessary for the transistors Q1 and Q2 that also serve as surge absorption to have a large capacity.

In this embodiment, the first resistor R1 is connected to the load 2.
And the second resistor R2 are interposed to compare the level difference between the detection levels V1 and V2 with the reference voltage R3 · I3, the resistors R1 and R2 can be operated without any trouble in the operation of the transistors Q1 and Q2. It can be set to a high value that can attenuate the inrush surge in the range. The inrush surge is attenuated by the first resistor R1 and the second resistor R2, and the positive surge of the intruded surge has the levels of the first detection line L1 and the second detection line L2 fixed as described above. , And can be absorbed by the first transistor Q1 and the second transistor Q2. On the other hand, the negative surge is absorbed by the negative input clamp circuit of the input clamp circuit 8 inserted in the first and second detection lines L2 and L3, but the capacitance can be made as small as possible.

FIG. 2 is a circuit diagram showing the configuration of the negative input clamp circuit 8a of the input clamp circuit 8 used in this embodiment. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals. The transistor Q11 is a transistor for clamping a negative input, and its collector is the second power supply Vcc.
In addition, the emitter is connected to the first detection input line L1, and the bias voltage V4 set to, for example, 0.7 V is applied to the base from the bias power supply Ex formed by a voltage divider circuit (not shown). When a negative surge enters and the level of the first detection line L1 swings to the negative side, the transistor Q11 conducts to clamp the surge level and prevent the circuit breakdown due to the negative surge. Although FIG. 2 shows the negative input clamp circuit 8a on the first transistor Q1 side,
The same circuit may be inserted on the second transistor Q2 side as well, whereby the clamp function can be enhanced. In the present embodiment, since the negative input clamp circuit 8a only needs to correspond to the surge level attenuated by the first resistor R1 and the second resistor R2 shown in FIG. 1, the clamp transistor Q11 and the like may have a small capacitance. Therefore, cost reduction and size reduction can be achieved.

FIG. 3 is a circuit diagram showing the configuration of the positive input clamp circuit 8b of the input clamp circuit 8. As described above, the positive surge can be absorbed by the damping action of the first resistor R1 and the second resistor R2 and the clamping action of the first and second transistors Q1 and Q2. However, as shown in the figure, a plurality of Zener diodes Zd are connected in series. Connected second
By inserting between the detection line L2 and the ground line L8 and setting the combined Zener voltage Vz appropriately, a positive surge exceeding the voltage Vz is clamped, and destruction of the semiconductor element or the like is prevented. Also in this case, since the Zener diode used does not need to have a large capacity, cost reduction and downsizing can be achieved similarly to the above-mentioned negative input clamp circuit 8a. Although FIG. 3 shows an example in which it is connected to the second transistor Q2 side, it may be inserted also to the first transistor Q1 side. In the embodiment of FIG. 1, the positive input clamp circuit 8b may be replaced by the first and second transistors Q1 and Q2 and not used.

FIG. 4 is a block diagram showing a circuit configuration of a load abnormality state detection circuit according to another embodiment of the present invention. 4, parts corresponding to those in FIG. 1 described above are denoted by the same reference numerals. One end of a first resistor R1 and one end of a second resistor R2 are connected to both ends of a load 2 to be detected, and the other end is a first detection line via a first detection input terminal T1 and a second detection input terminal T2. L1 and the second detection line L2 are respectively connected. The resistance values of the first and second resistors R1 and R2 may not be equal. The above-mentioned input clamp circuits 8 and 8 are connected to the first detection line L1 and the second detection line L2 to absorb the invading surge. In the circuit of FIG. 4, both clamp circuits 8 shown in FIG. 2 and FIG.
a and 8b are required.

What should be noted in this embodiment is that the open detection circuit 11 is constructed by using the differential input circuit 14. The non-inverting input terminal of the two input terminals of the differential input circuit 14 is connected to the first detection line L via the third resistor R13.
1 and the inverting input terminal is connected to the second detection line L2. This is a connection point P between the load 2 and the first resistor R1.
From the perspective, the series circuit of the first resistor R1 and the third resistor R13 is connected to the non-inverting input terminal of the differential input circuit 14, and the series circuit of the load 2 and the second resistor R2 is connected to the non-inverting input terminal. Has been done.

The first detection line L1 is connected to the third resistor R13 and the third constant current circuit 15. Third constant current circuit 1
5 flows out a third constant current I14 for energizing the differential input circuit 14. The third resistor R13 is connected in series with the first constant current circuit 13, and the first constant current I13 flowing therethrough is connected.
The voltage R13 · I13 generated by the product of is used as the reference voltage necessary for the detection operation, and is applied to the non-inverting input terminal of the differential input circuit 14. The second constant current circuit 12 is connected to the other second detection line L2, and the second constant current I12 is caused to flow to the ground line L8. As a result, the first detection line L
1 is the sum of the first constant current I13 and the third constant current I14 (I
13 + I14) current flows from the power line L0 to the first resistor R1
Of the second constant current I flowing into the second detection line L2.
12 flows in along the path of the power supply line L0 → the load 2 → the second resistor R2. Here, the second constant current circuit 12 is provided to equalize the voltage drops in the first resistor R1 and the second resistor R2, and R2 · I12 = R1 · (I13 + I14) (7) Is set as follows.

Next, the operation of this embodiment will be described. The non-inverting input terminal of the differential input circuit 14 has the first constant current I13,
The third constant current I14 applies the first detection level V11 of V11 = Vbat−R1 (I13 + I14) −R13 · I13 (8), and V12 = Vbat−VL is applied to the inverting input terminal by the second constant current I12. The second detection level V12 represented by −R2 · I12 (9) is applied. Vba
t is a power supply line L generated by an in-vehicle battery (not shown)
This is the power supply voltage applied between 0 and the ground line L8. The level between the two input terminals of the differential input circuit 14 is V11-V12 = VL + R2.I12-R1 (I13 + I14) -R13.I13 (10).

The second constant current circuit 1 is connected to the second detection line L2.
2 is connected, so R2 ・ I12 and R1 (I1
3 + I14) is erased and V11−V12 = VL−R13 · I13 (11) When V11 = V12, the differential input circuit 14
Is inverted, the detection level becomes VL = R13 · I13 (12). Here, when the load 2 is in the open state, the second detection level V12 decreases, and V11> V12, and the differential input circuit 14 outputs the high level open detection signal V1.
3 is led to the line L4, and the high level load open detection output Vout is output to the open detection output line L5 via the amplifier circuit 15.

In the present embodiment, in order to detect the open state of the load 2, the first detection level V11 and the second detection level V12, which are generated by using this potential difference R13.I13 as a reference voltage, are compared. If the load 2 is open,
The second detection level V12 is lowered and the voltage V across the load 2 is increased.
When L becomes equal to or higher than the level of the reference voltage R13.I13, the open state of the load 2 is detected.

As described above, in this embodiment, the resistance values of the first resistor R1 and the second resistor R2 interposed between the load 2 and the open detection circuit 11 can be set to values effective for attenuating the surge. .

In the present embodiment, in order to energize the amplifier circuit 16 with power, a voltage regulator PS is connected to the power supply line L0 and the power supply voltage Vbat is stepped down to generate a second power supply voltage Vcc.
(In the present embodiment, for example, 5V) is generated and supplied to the amplifier circuit 16 via the line L7. Since the power source of the amplifier circuit 16 is obtained from a circuit different from the differential input circuit 14 as described above, the current flowing through the first detection line L1 is the differential input to the first constant current I13 as described above. Only the current I14 that energizes the circuit 14 is present. If the power supply of the amplifier circuit 16 is also supplied from the first detection line L1, the current flowing through the first resistor R1 increases and the voltage drop in the first resistor R1 becomes large. There is no choice but to lower the resistance value of the resistor R1. If the resistance value of the first resistor R1 is lowered, the surge withstand capability decreases,
The surge current that enters the first detection input terminal B increases, and a large-capacity input clamp circuit is required to cope with this. For this reason, in the present embodiment, the power of the amplifier circuit 16 is supplied from the regulator PS to reduce the capacity of the input clamp circuit 8.

FIG. 5 is a block diagram showing a circuit configuration of a load abnormal state detection circuit 21 according to still another embodiment of the present invention. FIG. 5 is similar to FIG. 4, corresponding parts are designated by the same reference numerals, and the input clamp circuit and the voltage regulator are not shown. It should be noted in this embodiment that, in addition to the open detection circuit 22 having the same configuration as that of FIG.
The short circuit detection circuit 23) is provided.

In the present embodiment, the second detection line L2 is commonly connected to the inverting input terminals of the first differential input circuit 14 and the second differential input circuit 26, and the first differential input circuit 14 performs open detection. Is detected by the second differential input circuit 26. Below, open detection output is Vout
1, the short-circuit detection output is represented as Vout2, and the reference mark related to the short-circuit detection is appended with a lower case s, and the one related to the open detection is lower-cased o.
Are added to distinguish. The open detection circuit 22 has been described above with reference to FIG.

The inverting terminal of the second differential input circuit 26 forming the short detection circuit 23 is connected to the second detection line L2 as described above, and the non-inverting terminal has a voltage dividing circuit and a constant voltage element (not shown). Is connected to the reference power source Er and the reference voltage Vr is applied. Reference voltage Vr
Is preset to Vr> VS. VS is a voltage generated across the drive switch 3 by a current flowing through the switch when the load 2 is in a normal state when the drive switch 3 is conducting. In this way, the short-circuit detection of the load 2 is performed when the drive switch 3 is conducting, contrary to the open detection, and the voltage VS across the drive switch is compared with the reference voltage Vr.

In FIG. 5, when the load 2 is normal, the voltage generated at both ends of the drive switch 3 when the drive switch 3 is conductive is almost 0, and the second detection level V12s derived to the second detection line L2 is the reference value. Lower than voltage Vr, Vr> V
It will be 12s. Therefore, in this case, the output V24 of the second differential input circuit 26 is maintained at the high level. On the other hand, when the load 2 is short-circuited, the voltage VS is generated across the drive switch 3 due to the large short-circuit current and is led to the second detection line L2, the second detection level V12s rises, and Vr <V12s. Then, the second differential input circuit 26
The output V24 derived from the line L9 is inverted to the low level. The second amplifier circuit 17 corresponds to the output of the differential input circuit 26 and outputs a low level short circuit detection output Vout2.
To the short-circuit detection output terminal T4. As a result, it is detected that the load 2 is short-circuited.

As described above, in this embodiment, the open state of the load 2 is detected when the drive switch 3 is cut off, and when it is detected that the load 2 is in the open state, the open detection output Vout1 of high level is detected as open. It is output to the output terminal T3. The short-circuit state is detected when the drive switch 3 is conducting, and when it is detected that the load 2 is short-circuited, the low-level short-circuit detection output V
Out2 is output to the short-circuit detection output terminal T4.

However, in the present embodiment shown in FIG. 5, when the load 2 is short-circuited, the shunt I12s to the second constant current circuit 12 connected to the second detection line L2 is detected.
As a result, an error occurs due to the voltage drop R2 · I12 in the second resistor R2, and the short-circuit detection accuracy is degraded. Without the second constant current circuit 12, such a problem does not occur. For this reason, the inventor of the present invention has further improved the circuit shown in FIG. 5 to detect the open state and the short state individually, and further, to eliminate the above-described error in the detection of the short circuit. Realized the circuit. Hereinafter, this will be described with reference to the embodiment shown in FIG.

FIG. 6 is a block diagram showing the circuit configuration of a load abnormality state detection circuit 31 according to another embodiment of the present invention. FIG. 6 is similar to FIG. 5, and the corresponding parts bear the same reference numerals. In the circuit of FIG. 5, since the second constant current circuit 12 is present, an error occurs when detecting a short circuit. The inventor has found that the second constant current circuit 12 is necessary for open detection of the load 2 but not necessary for short detection, and that the operation mode of the drive switch 3 is opposite between open detection and short detection. Focusing attention, a changeover switch 17 which is a disconnecting means that operates in response to the operation of the drive switch 3 is provided, and the changeover switch 17 is operated at the same time as the operation of the drive switch 3, and when the short circuit is detected, the second switch is used.
The constant current circuit 12 is separated from the second detection line L2.

Specifically, in order to operate the changeover switch 17 together with the drive switch 3 by the switch changeover signal Sw input through the line L11, the line L1 is activated.
1 is extended and connected to the drive terminal T6 of the changeover switch 17. As a result, the drive switch 3 and the changeover switch 17 are simultaneously operated by the switch changeover signal Sw. However, in FIG. 6, the operations of the drive switch 3 and the changeover switch 17 are opposite to each other as shown in Table 1.

[0043]

[Table 1]

As described above, the second constant current circuit 12 is set to the second constant current circuit 12 in response to the open detection or the short detection of the load 2.
Since it is connected to or disconnected from the detection line L2, the second constant current circuit 12 is disconnected and the voltage VS generated at both ends of the drive switch 3 is transmitted without error when a short circuit is detected. It is possible to improve the short-circuit detection accuracy. Next, a load abnormal state detection circuit realized based on the embodiment shown in FIG. 6 will be described with reference to FIG.

FIG. 7 is a circuit diagram showing the configuration of a load abnormality state detection circuit according to another embodiment of the present invention. FIG. 7 shows FIG.
The contents of the blocks of the embodiment shown in FIG. 3 are concretely shown, and corresponding parts are designated by the same reference numerals. The load abnormal state detection circuit 31 includes blocks of an open detection circuit 22, a short detection circuit 23, and an input clamp circuit 8, and a power supply voltage Vbat from a vehicle battery (not shown) or the like is applied between the power supply line L0 and the ground line L8. The second power supply voltage Vcc reduced by the voltage regulator PS is applied between the second power supply line L7 and the ground line L8.

At both ends of the load 2 such as an actuator,
One ends of the first resistor R1 and the second resistor R2 are connected to each other, and the other ends thereof are connected to the first detection line L1 and the second detection line L2 via the first detection input terminal T1 and the second detection input terminal T2, respectively. Individually connected. An input clamp circuit 8 including a negative input clamp circuit 8a and a positive input clamp circuit is connected to the second detection line L2 to absorb an inrush surge. The second detection line L2 connected to the second detection input terminal T2 includes a second detection line L2o for open detection and a second detection line L for short detection.
It is divided into 2 seconds. The PNP transistor Q12 provided at the bisection point of the second detection line L2 is the PNP transistor Q23 inserted on the first detection line L1 side.
This is for causing a voltage drop equal to the voltage drop of 2 to occur also on the second detection line L2o side. Open detection circuit 2
2 is formed by the first differential input circuit 14 and the first current mirror circuit 32. The first differential input circuit 14 includes a differential pair composed of a pair of PNP transistors Q21 and Q22, and a differential amplifier having the base of the transistor Q21 as a non-inverting input terminal and the base of the transistor Q22 as an inverting input terminal is formed. ing. The first detection line L1 is connected to the base of the transistor Q21 via a third resistor R13, and the second detection line L12o is connected to the base of the transistor Q22. First detection circuit L1
A first constant current I13 predetermined by the first constant current circuit 13 flows out from one transistor Q23 of the first current mirror circuit 32 connected to the third current mirror circuit 32, and a potential difference R13. I13 is occurring. In this embodiment, the potential difference R13 · I13 is used as a reference voltage to generate the first detection level V11 and compare it with the second detection level V12o to detect the open state of the load 2.

The third constant current circuit 15 is formed by the other transistor Q24 of the first current mirror circuit 32,
A third constant current I14 corresponding to the first constant current I13 flows out to energize the first differential input circuit 14. Due to the two constant currents I13 and I14, a voltage drop R1 (I13 + I14) occurs in the first resistor R1 on the first detection line L1 side.
The second constant current circuit 12 is provided on the second detection line L2o side in order to cause a voltage drop equal to this in the second resistor R2, and the first constant current I13 and the third constant current I13.
The second constant current I12o set to be equal to the sum of the constant currents I14 flows out to the ground line L8. In the present embodiment, the second constant current circuit 12 is formed by the second current mirror circuit 33, and the constant current source 34 connected to the second power supply line L7 supplies a current Io equal to the second constant current I12o. The current flows into the NPN transistor Q25 of the two-current mirror circuit 33, so that the second constant current I12o flows out from the opposing NPN transistor Q26. The NPN transistor Q31 connected in parallel with the transistor Q25 forms a changeover switch 17 for shutting off the second constant current circuit 12 at the time of short-circuit detection which will be described later, and originally, the short-circuit detection circuit 23.
It is included in, but is drawn in this position for the convenience of drawing.

Thus, when the load is normal and the voltage across the load is smaller than the reference voltage R13.I13, the level of the output line L4 of the first differential input circuit 14 is low, but the load 2 Is opened, the level of the output line L4 is inverted to a high level, and the first amplifying circuit 16 in the subsequent stage outputs the detected output line L5,
The high level load open detection output Vout1 is led to the open detection output terminal T3. In this way, when the drive switch 3 is cut off, the output Vout1 derived to the load open detection output terminal T3 is inverted from low to high, whereby it is detected that the load 2 is in the open state.

The short-circuit detection circuit 23 is composed of a second differential input circuit 26 which is a comparison means, a second amplifier circuit 27, and a changeover switch 17 which is a disconnection means. The voltage VS at both ends when the drive switch 3 is turned on is equal to the load 2
Is almost 0 level when is normal, but rises due to a large short-circuit current when the load 2 is short-circuited. The voltage VS across the drive switch 3 is set to the second value when the short circuit is detected.
It is guided to the detection line L2s and compared with the reference voltage Vr preset by the second differential input circuit 26 to detect the short-circuit state of the load 2. The short-circuit detection operation is performed when the drive switch 3 is conductive in this way,
In the following description, unless otherwise specified, it is assumed that the contacts of the drive switch 3 are closed and electrically connected when a short circuit is detected.

The second differential input circuit 26 forming the short circuit detection circuit 22 includes a pair of PNP transistors Q32, Q.
33 to form a differential amplifier including a differential pair including
Electric power is supplied from the second power supply line L7 via the constant current source 36. The base of one transistor Q33 of the second differential input circuit 26 has a reference voltage V from the reference power source Er.
r is applied. The level of the reference voltage Vr is the load 2
Is set to a higher level than the voltage generated across the switch due to the current flowing through the switch 3 in the normal state. When the load 2 is short-circuited, the voltage VS across the load 2 rises, and the second detection level V2s becomes equal to or higher than the reference voltage Vr, the output line L9 of the second differential input circuit 26.
Is inverted from high to low and is input to the second amplifier circuit 27, whereby the low level load short-circuit detection output Vou is output from the collector of the output transistor Q35.
t2 is led to the second output terminal T3 via the short circuit detection output line L10. Thus, when the drive switch 3 is conducting, the output Vout2 led to the load short-circuit detection output terminal T4 is inverted from high to low, whereby it is detected that the load 2 is in the short-circuited state.

When a short circuit is detected, the switch switching signal Sw for controlling the conduction / shutoff of the drive switch 3 is switched to the switching terminal T.
6 through line L11, switching element NP
It is input to a changeover switch 17 formed by an N-transistor Q31 and a voltage dividing circuit R31 composed of a plurality of resistors. The transistor Q forming the changeover switch 17
The second switch 31 is connected in parallel with the drive switch 3 by the switch switching signal Sw and is connected in parallel.
The collector-emitter of one transistor Q25 of the current mirror circuit 33 is short-circuited to deactivate the second current mirror circuit 33. Therefore, the second constant current circuit 1
2 is separated from the second detection line L2, and an error factor at the time of detecting a short circuit is removed. In this embodiment, the drive switch 3
Is controlled by the switch changeover signal Sw, but the changeover switch 1 is operated by the operation of the drive switch itself.
It is also possible to control the interruption of the conduction of No. 7.

The input clamp circuit 8 is composed of a negative input clamp circuit 8a and a positive input clamp circuit 8b. The negative input clamp circuit 8a includes an NPN transistor Q11.
, A diode D11, D12, a resistor R11, and a diode dropper D13 including a plurality of diodes. The collector of the transistor Q11 has a second power supply line L7 via a backflow prevention diode D11.
The emitter is connected to the second detection line L2.
By the diode dropper D13, for example, Vd1≈1.
A level of 4V is obtained and this level Vd1 is applied to the base of the transistor Q11 via the diode D12. Therefore, a level obtained by subtracting the junction voltage Vd2 of the diode D12 is applied to the base of the transistor Q11, and when the level of the second detection line L2 swings to the negative side due to the negative surge, the transistor Q11 becomes conductive and the surge occurs due to the clamp action. Absorbs. The positive input clamp circuit 8b is realized by, for example, a Zener diode array Zd formed by connecting a plurality of Zener diodes in series, and clamps an inrush surge by setting the Zener voltage Vz lower than the withstand voltage level of the semiconductor element used. As described above, the first detection line L passes through the power supply line L0.
The surge entering the first and second detection lines L2 is attenuated by the first resistor R1 and the second resistor R2, and the attenuated surge is further detected by the first differential input circuit 14 in the first detection line L1 and the second detection line L2. Since the level of the line L2 is absorbed by being fixed, the Zener diode array Zd does not need to have a large capacity, and the cost and the size can be reduced. Although the illustration of the input clamp circuit on the first detection line L1 side is omitted in FIG. 7, the same configuration is connected to further improve the surge absorbing function. Although a plurality of Zener diodes are used in this embodiment, other surge absorbing elements may be used, and the number is not limited, as a matter of course.

[0053]

As described above, the load abnormality state detection circuit according to the present invention detects an abnormality in the load, one end of which is connected to one end of the power supply and the other end of which is connected to the other end of the power supply via the switching means. In the detection circuit, the detection circuit is formed of a pair of transistors, and a first resistance and a second resistance are interposed between the load and the detection circuit, and the first resistance is connected to one end of the load and the emitter of the first transistor. The two resistors are respectively connected to the other end of the load and the emitter of the second transistor, the base potential of the first transistor is set to a predetermined first potential, and the base potential of the second transistor is set to be higher than the base potential of the first transistor. Is also set to a second potential that differs by a predetermined reference voltage, so that when the voltage across the load exceeds the reference voltage when the switching means is shut off, the load is opened. It was to detect that it has become a normal state. Therefore, the first interposition between the load and the detection circuit
The inrush surge can be clamped by damping the inrush surge by the resistance and the second resistance and fixing the emitter potential of the first transistor and the second transistor, so that the capacity of the surge absorption circuit can be increased. The cost can be reduced and the size can be easily reduced.

Further, according to the present invention, the detection circuit is formed by a differential input circuit, and one ends of the first resistance and the second resistance interposed between the detection circuit and the load are individually connected to each end of the load. Then
The other end of the first resistor is connected to one input terminal of the differential input circuit via the third resistor, and the other end of the second resistor is connected to the other input terminal of the differential input circuit. The first constant current from the current circuit is applied to the one input terminal of the differential input circuit by using the voltage generated by flowing the first constant current through the third resistor to the third resistor as the reference voltage, and the second constant current from the second constant current circuit is applied. By applying a voltage generated by flowing a current through the second resistance through the load to the other input terminal, an abnormal state due to the open of the load is detected when the voltage across the load becomes equal to or higher than the reference voltage. Therefore, the first resistance and the second resistance interposed between the load and the detection circuit serve as damping resistance against an inrush surge, and the surge absorption means having a small capacity absorbs the surge to prevent destruction of the semiconductor element or the like. it can.

According to the present invention, the potential at the connection point between the other end of the second resistor and the other input terminal of the differential input circuit is compared with a predetermined reference potential when the switching means is conducting.
Since the comparison means for detecting that the potential at the connection point is equal to or higher than the reference potential is provided, the short-circuit state of the load can also be detected, and the disconnection means is provided to disconnect the second constant current circuit when a short-circuit is detected. As a result, it is possible to improve the detection accuracy when detecting an abnormal state due to a short circuit.

As described above, according to the present invention, since the surge that enters from the power source or the like is attenuated by interposing the resistor between the detection circuit and the load, the destruction of the circuit element is prevented, and the surge of large capacity is also provided. Since no absorbing means is required, cost reduction and size reduction can be achieved, and the industrial effect thereof is great.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a load abnormal state detection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a negative input clamp circuit used in an embodiment of the present invention.

FIG. 3 is a circuit diagram of a positive input clamp circuit used in an embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit configuration of a load abnormal state detection circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration according to an embodiment in which the circuit shown in FIG. 4 is improved.

FIG. 6 is a block diagram showing a circuit configuration of still another embodiment of the present invention.

FIG. 7 is a circuit diagram of the embodiment shown in FIG.

FIG. 8 is a block diagram showing a circuit configuration of a load abnormal state detection circuit according to a conventional technique.

[Explanation of symbols]

 1, 21, 31 Load abnormal state detection circuit 2 Load 3 Drive switch 4,22 Load open state detection circuit 8 Input clamp circuit 8a Negative input clamp circuit 8b Positive input clamp circuit 12 Second constant current circuit 13 First constant current circuit 14 First differential input circuit 16 First amplification circuit 17 Changeover switch 23 Load short-circuit state detection circuit 26 Second constant current circuit 27 Second amplification circuit I12 Second constant current I13 First constant current I14 Third constant current L1 First detection Line L2 Second detection line L2o Open detection second detection line L2s Short detection second detection line R1 First resistance R2 Second resistance R3, R13 Third resistance Sw Switch switching signal T1, T2 Detection input terminal T3, T4 Load Abnormal condition detection output terminal V11 1st detection level V12 2nd detection level V12o Open Second detection level for detection V12s Second detection level for short circuit detection Zd Zener diode array Er Reference power supply

Claims (3)

[Claims] 1. A circuit for detecting an abnormal state of a load, one end of which is connected to one end of a power supply and the other end of which is connected to the other end of the power supply via a switching means, wherein one end of the load has one end thereof A first resistor connected to the load, a second resistor having one end connected to the other end of the load, an emitter connected to the other end of the first resistor, and a base set to a predetermined first potential. A second transistor having an emitter connected to the other end of the second resistor and a base set to a second potential different from the first potential by a predetermined reference voltage; An abnormal load state detection circuit for detecting an abnormal state of the load when the voltage across the load becomes equal to or higher than the reference voltage. 2. A circuit for detecting an abnormal state of a load, one end of which is connected to one end of a power supply and the other end of which is connected to the other end of the power supply via a switching means, wherein one end of the load is connected to the one end thereof. A first resistor connected to the load, a second resistor having one end connected to the other end of the load, a third resistor having one end connected to the other end of the first resistor, and one input having the third resistance One of the third resistor and the differential input circuit, which is connected to the other end of the resistor, the other input of which is connected to the second resistor and which is energized via the first resistor A first constant current circuit connected between the other end of the power supply and the input connection point of, and a connection point between the other input of the second resistor and the differential input circuit and the other end of the power supply. A second constant current circuit connected to the first constant current circuit, A load abnormality in which an abnormal state of the load is detected when the product of the resistance value of the resistor and the current value of the first constant current circuit is used as a reference voltage and the potential across the load becomes equal to or higher than the reference voltage. State detection circuit. 3. The potential of the disconnecting means for disconnecting the second constant current circuit when the switching means is conducting, and the potential at the connection point between the other end of the second resistor and the other input of the differential input circuit is a predetermined reference. The load abnormal condition detection circuit according to claim 2, further comprising: a comparing unit that detects an abnormal condition of the load when the potential at the connection point is equal to or higher than the reference potential as compared with a potential.