JPH0622556A - Pwm pattern generator circuit - Google Patents

Abstract

PURPOSE:To lessen the increase of the operations of a CPU and to obtain smooth output voltage, by causing a voltage command to change linearly instead of changing in steps. CONSTITUTION:Variation command of a PWM command is written in a fourth register R22, and it supplies data to a latch circuit DQ1 by the output from an N-nary counter NCO. And the output of this circuit DQ1 is given to an adder circuit ADD2, and it is added to the output of a third resistor Q1 with the adder circuit ADD2. After that, it changes the value of the third register Q1 through the medium of a selector switch S25. The output of the third register Q1 is compared with the output of an up-down counter UDC by a comparator circuit CP1, and a PWM pattern is obtained as its output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM pattern generation circuit for controlling an inverter used in a variable speed drive device.

[0002]

2. Description of the Related Art Conventionally, among the PWM pattern generation methods for inverters, as a method for generating a PWM pattern in an analog circuit, the magnitude of a triangular wave carrier and a voltage command are compared to determine the pattern. The calculation method is generally used. By using the count value of the up / down counter instead of the triangular wave and comparing the count value with the value of the register written from the CPU or the like by the digital comparator, a similar circuit can be realized by a digital circuit. 5 is a block diagram thereof. In FIG. 5, the central processing unit CPU sets the upper limit value of the triangular wave to the carrier counter upper limit command write register R.
1 and the voltage command of each phase is written in the PWM command write registers R2 and R3. The up / down counter UDC repeats up / down to the upper limit value set in the register R1 and performs up / down switching at the apex of the upper or lower limit of the triangular wave shown in FIG. 6 by the up / down switching unit UDS. This up / down switching unit UD
S outputs a data latch signal A for reading the next carrier amplitude through the switch S1.

Q1 and Q2 are PWM comparator registers, and the registers Q1 and Q2 have variations in the data writing time for each phase of the PWM command written in the registers R2 and R3 by the central processing unit CPU. Is a buffer register for. The registers R2 and R3 transfer data to the registers Q1 and Q2 at the time of each triangular wave apex of the data latch signal A at the time of each phase cooperation. By transferring in this way, the three-phase command changes simultaneously. CP1,
CP2 is a size comparison circuit. These comparison circuits CP1 and CP2
Compares the PWM command values (Q1 and Q2 values) of each phase with the output (carrier value) of the up / down counter UDC to generate a PWM pulse pattern of each phase at the output. In the case of polyphase, registers R1, R2, Q1, Q2,
This can be realized by increasing Q1, Q2, CP1, CP2, S2, S3.

[0004]

Recently, IGBTs and FEs have been proposed.
With the development of T, the carrier frequency of PWM can be increased. However, the PWM voltage command time cannot be calculated in the half cycle of the PWM carrier due to the limit of the calculation capability of the central processing unit CPU. Therefore, FIG.
As shown in FIG. 5, a circuit in which an N-ary counter NCO, a register R10 and a switch S10 are added to FIG. 5 has been put into practical use. In FIG. 3, a register R10 sets the count division value of the N-ary counter NCO. N
The advance counter NCO counts the triangular wave vertex pulse output from the up / down switching unit UDS, and the switch S10
Thus, the next divided N value is loaded simultaneously with the output of the divided pulse of the N-ary counter NCO. This is obtained by replacing the timing at which the switches S2 and S3 are turned on and loaded into the registers Q1 and Q2 in FIG. 5 with a data latch signal B for outputting once to the N frequency division value.

As a result, as shown in FIG. 4, the PWM carrier and the PWM command change every N times the PWM half cycle, and the same PWM pattern can be repeatedly output during that period. Therefore, the PWM calculation cycle may be performed before the data latch signal B is output, and the central processing unit CPU used for the conventional transistor or the like can be used as it is. This means that no fast CPU is needed. Moreover, the calculation method of PWM may be almost the same. But,
Since the voltage command changes every time the data latch signal B is output, the output voltage changes stepwise for each cycle of the data latch signal B. In order to output this state more smoothly, there is a problem that the CPU must be operated at a high speed to shorten the period of the data latch signal B.

The present invention has been made in view of the above circumstances, and an adding circuit and a voltage data change data register or the like are provided in the PWM generation circuit so that the voltage command changes from a stepwise shape to a linear shape. PW that reduces the increase in the CPU calculation amount and obtains a smooth output voltage.
An object is to provide an M pattern generation circuit.

[0007]

In order to achieve the above object, the present invention provides a first register in which an upper limit value of a triangular wave carrier from a CPU is written, and a PW of each phase.
A second register in which the M voltage command is written,
An up / down counter that repeats up / down to the upper limit value set in the register, an up / down counter switching unit that switches the up / down counter to obtain a triangular wave vertex pulse at the output, and counts the triangular wave vertex pulse obtained by this switching unit. A PWM repetition N-ary counter, a PWM repetition number command register that is written from the CPU and that sets the count division value of the N-ary counter, and a PWM instruction according to the count division value from the N-ary counter. In a PWM pattern generation circuit including a third register for writing and a comparison circuit for comparing the output of the third register with the output of the up / down counter, a fourth register for writing the change amount of the PWM command And the output of this fourth register is sent out by the counter frequency division value from the N-ary counter. A latch circuit for writing the value of the latch circuit, an adder circuit for adding the values of the output of the latch circuit and the output of the third register, and an output of the adder circuit and an output of the second register from the N-ary counter. It is characterized in that it is constituted by a selector that selects according to a counter frequency division value and a switch that updates the value of the third register for the output selected by this selector every half cycle of the carrier wave. .

According to a second aspect of the present invention, a fifth register in which the change amount of the carrier wave is written, a sixth register in which the output of the first register is written, and a fifth register in which the output of the sixth register and the change amount of the carrier wave are written. An adder circuit for adding the output of the register, a selector for selecting the output of the adder circuit according to the counter frequency division value from the N-ary counter, and an output selected by the selector for each half cycle of the carrier wave. A switch for updating the value of the sixth register, and the up / down counter is changed by the value of the sixth register.

[0009]

The first invention is the PWM written in the fourth register.
Write the command change in the latch circuit. The output of the latch circuit is added to the third register and then supplied to the third register via the selector to update the value of the register. The output of the third register is compared with the output of the up / down counter in a comparison circuit to obtain a pattern output. The output of the third register integrates the value of the fourth register while the second register remains selected as the input. In the second invention, after the change amount of the carrier written in the fifth register and the output of the sixth register are added, they are supplied to the sixth register via the selector to update the value of the register.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. The same parts as those in FIG. In FIG. 1, R22 is a register (fourth register) in which the change amount of the PWM command is written from the CPU.
In 22, the values corresponding to the symbols D1 and ΔD1 shown in FIG. 2 are written. On the other hand, the N-ary counter NCO displays the N frequency division value signal D
When (shown in FIG. 2) is output, the value of the register R2 is sent to the switch S27 through the selector switch S25.
The value of the register R2 is the comparator register Q as it is.
1 (third register).

During the PWM half cycle (the period of the apex signal C), the PWM pattern is created with the value of the register Q1. Both the apex signal C and the N-divided value signal D have a width of one clock of the PWM carrier counter, and each switch is turned off immediately after data transfer. When the PWM carrier is counted and the N frequency division value signal D is not output when the next vertex signal C is generated, the value of the latch of the register Q1 and the value of the latch register DQ1 are added to the adder circuit ADD2.
The output resulting from the addition in step S25 is selected by the selector switch S25. Since the switch S27 also outputs the N divided value signal D at the apex of the triangular wave of the counter, the apex signal C (shown in FIG. 2) also closes the switch S27, so that (D1 + ΔD1) in the next half cycle. ) Is set in the register Q1. This ΔD1 is N every PWM half cycle
Since the addition is performed every time until the frequency-divided signal D is output, the command changes with a constant slope as in the section indicated by the symbol a in FIG.

As a result, the output voltage, which has changed stepwise, changes linearly. If the value of ΔD1 can be positive or negative, the slope of the PWM command can be set to either positive or negative. Similarly, the carrier cycle can be changed every PWM half cycle, as in the section indicated by reference character d in FIG. This circuit is shown below. R20 is a register (sixth register) for setting the upper limit value of the up / down counter for creating a carrier wave, R21 is a register (fifth register) for writing the change amount of the carrier wave, and ADD1 is an adder circuit. Further, S21 is a selector switch, S2
2, S23, S24 are switches, and selector switch S
21 and the switch S22 are controlled by the N frequency division value signal D, and the switches S23 and S24 are controlled by the vertex signal C.

In the above circuit, the PWM calculation is N
Do this once for each signal cycle of the frequency division value signal D, compare it with the previous setting value, calculate the value of ΔD, and reach the PWM calculation value this time before the next N frequency division value signal is generated. PWM
The calculation time may be increased only by the calculation of ΔD.

[0014]

As described above, according to the present invention,
By providing the adder circuit, the register for writing the change amount of the PWM command, the latch circuit, and the like, it becomes possible to change the voltage command from stepwise to linear.
There is an advantage that the increase of the PWM calculation amount is small, a smooth output voltage can be obtained, and the change of the PWM command is realized by the hardware, so that the load of the software of the CPU is significantly reduced.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is a structural explanatory view of a conventional example.

FIG. 4 is an operation explanatory diagram of FIG. 3;

FIG. 5 is an operation explanatory diagram of a conventional example.

6 is an explanatory diagram of the operation of FIG.

[Explanation of symbols]

CPU ... Central processing unit R1 ... Register (first register) R2 ... Register (second register) Q1, Q2, R20 ... Comparator register (third register) R22 ... Register (fourth register) R21 ... Register (first) 5 register) DQ1 ... Latch circuit ADD1, ADD2 ... Addition circuit UDC ... Up-down counter UDS ... Up-down switching unit NCO ... N-ary counter CP1, CP2 ... Comparison circuit S21, S25 ... Selector switch S10, S22, S23, S24, S26 , S27 ... switch

Claims (2)

[Claims] 1. A first register to which an upper limit value of a triangular wave carrier from the CPU is written, and a second register to which a PWM voltage command of each phase is written are provided, and the upper limit value set in the first register is increased. An up-down counter that repeats down, an up-down counter switching unit that switches the up-down counter to obtain a triangular wave apex pulse at the output, a PWM repeating N-ary counter that counts the triangular wave apex pulse obtained by the switching unit, CP
A PWM repetition number command register which is written from U and sets the count division value of the N-ary counter;
A PWM pattern including a third register for writing a PWM command according to the count division value from the advance counter and a comparison circuit for comparing the output of the third register with the output of the up / down counter. In the generation circuit, a fourth register for writing the change amount of the PWM command, a latch circuit for writing the output of the fourth register when the counter frequency division value from the N-ary counter is sent, an output of the latch circuit and the An adder circuit for adding the value of the output of the 3 register, a selector for selecting the output of the adder circuit and the output of the second register according to the counter frequency division value from the N-ary counter, and the selector And a switch for updating the value of the third register for each half cycle of the carrier wave.
Pattern generation circuit. 2. A fifth register in which a change of the carrier wave is written, a sixth register in which an output of the first register is written, and an output of the sixth register and a fifth register in which the change of the carrier wave is written. An adder circuit for adding the output, a selector for selecting the output of the adder circuit according to the counter frequency division value from the N-ary counter, and an output selected by the selector for each half cycle of the carrier wave. The PWM pattern generation circuit according to claim 1, further comprising a switch for updating the value of the 6th register, and changing the up / down counter by the value of the 6th register.