JPH06224932A - Packet converter - Google Patents

Abstract

PURPOSE:To eliminate the need for execution of exceptional processing in other processing by executing the exemption processing for a processing by applying conversion processing to a packet whose input processing is finished and starting output processing after the conversion processing is finished. CONSTITUTION:An input processing section 11 executes required input processing prior to the conversion processing by a conversion processing section 12. The conversion processing section 12 references a routing tag table 2 with respect to a received packet whose input processing is finished to execute the conversion processing thereto. An output processing section 13 applies output processing to the packet whose conversion processing is executed. Thus, since the conversion processing is applied to a packet whose input processing is finished and the output processing is started after the conversion processing is finished, even when a processing such as exemption processing is executed in the input processing, it is not required to execute the exceptional processing in other processing such as the conversion processing. Thus, the timing design is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet conversion device for performing a predetermined conversion process on an input packet in a packet switching system, and more specifically, routing for fixed length packets such as ATM cells. The present invention relates to a packet conversion device that adds tags and deletes routing tags.

[0002]

2. Description of the Related Art Information and communication systems have become an important infrastructure in the present information society, and it is certain that their importance will increase in the future. Conventionally, various information communication systems have been proposed in order to provide advanced and various services. Among other things, ATMs that exchange information in the form of fixed-length packets called cells.
(Asynchronous Transfer Mode) A communication system is considered to be a favorite of the next-generation communication system and is under active development.

The ATM switching system used in the ATM communication system is generally constructed as shown in FIG. When a fixed length packet (cell) as shown in FIG. 2A arrives at the switching system from the ingress side interface point, the input cell is first inputted to the routing tag addition unit 1.
The routing tag addition unit 1 uses the logical channel identifier (VPI, VCI) written in the header of the input cell.
The logical cell number is calculated from the above, and the routing tag table 2 is referred to by using this as a key to convert the input cell into a cell with a routing tag as shown in FIG. 2B and output it. The cell with a routing tag is input to the self-routing switch 3 and autonomously switched to a desired outgoing route according to the information of the routing tag.

The cell with a routing tag exchanged by the self-routing switch 3 is input to the routing tag deleting unit 4. The routing tag deletion unit 4 deletes the routing tag and the like from the cell with the routing tag, and uses the output side physical VCI in the cell header of the cell with the routing tag as a key to convert the header conversion table 5
The logical channel identifier is updated from the value at the input side interface point to the value at the output side interface point by referring to.

As described above, the routing tag addition section 1 has a packet conversion function of converting an input cell into a cell with a routing tag. Similarly, the routing tag deletion unit 4 also has a packet conversion function of converting a cell with a routing tag into a cell without the routing tag.

The routing tag addition unit 1 is conventionally shown in FIG.
It is configured as shown in. Of the input cells arriving at the input processing unit 91, the logical channel identifiers (VPI, VCI, that is, the input side physical VCI) present in the header are transferred to the conversion processing unit 92, and other information such as the payload is selected by the selector. It is transferred to and stored in a cell buffer 94 composed of a RAM via 93. The conversion processing unit 92 refers to the routing tag table 2 based on the logical channel identifier within the period in which the payload and the like are accumulated in the cell buffer 94, and creates the routing tag and the like. After all the payloads and the like are stored in the cell buffer 94, the routing tags and the like output from the conversion processing unit 92 are transferred to and stored in the cell buffer 94 via the selector 93. In this way, the cells with routing tags are accumulated in the buffer 94. The cell with a routing tag accumulated in the cell buffer 94 is read and output by the output processing unit 95.

The routing deleting unit 4 is also constructed in the same manner as in FIG. However, the routing tag table 2 is replaced with the header conversion table 5. In this case, a cell with a routing tag is input to the input processing unit 91, and the outgoing physical VCI, which is the logical channel identifier existing in the header portion of the cell, is transferred to the conversion processing unit 92, and the routing tag and the like are removed. Other information such as the payload is transferred to and accumulated in the cell buffer 94 via the selector 93. The conversion processing unit 92 refers to the header conversion table based on the outgoing physical VCI within the period in which the payload and the like are accumulated in the cell buffer 94, and creates a new header including the VPI and VCI at the outgoing interface point. To do. After all the payloads are stored in the cell buffer 94, the new header output from the conversion processing unit 92 is transferred to the cell buffer 94 via the selector 93 and stored therein. In this way, the cell having the new header is accumulated in the buffer 94. The cell having the new header accumulated in the cell buffer 94 is output by the output processing unit 9
It is read out by 5 and output. The packet conversion device such as the routing tag addition unit and the routing tag deletion unit according to the above-described conventional configuration method has the following problems.

The first problem is that when the input processing unit 91 performs exceptional processing, the conversion processing unit 92 must also perform exceptional processing accordingly. An example of an exceptional process in the input processing unit 91 is a process called "cell discard" that discards a cell having an abnormal length when it is input. When a cell with an abnormal length is input in this way, the conversion processing unit 91 must prohibit the increment operation of the passing cell number counter in the routing tag table 2 as an exception process, as the cell is discarded.

However, for example, when the length of the input cell is shorter than the specified value, the increment operation is aborted midway.
When the length is longer than the specified value, it is found that the cell length is abnormal after the increment operation. Therefore, it is necessary to consider various states such as decrementing the value of the passing cell number counter. Becomes complicated.

The second problem is that, in addition to the input processing unit 91 accumulating the input cells in the cell buffer 94 within the period for inputting one cell, the routing tag and the like created in the conversion processing unit 92 are also added. Since it is necessary to write data in the same cell buffer 94, it is not easy to design the timing of writing cells in the cell buffer 94. In particular, in the routing tag addition unit 1, since the length of the cell with the routing tag written in the cell buffer 94 is longer than the length of the input cell (for example, the former is 53 octets, the latter is 64 octets), the synchronization with the input cell is performed. It is difficult to write.

[0011]

As described above, in the conventional packet conversion device, when the input processing unit performs exceptional processing, the conversion processing unit must also perform exceptional processing, which makes timing design difficult. Within the period of inputting one packet, in addition to the input processing unit accumulating the input packet in the buffer, the routing tag etc. created in the conversion processing unit must be written in the same buffer. There is a problem that it is not easy to design the packet write timing.

A first object of the present invention is to provide a packet conversion device in which timing conversion is easy because the conversion processing unit does not need to perform exceptional processing even when the input processing unit performs exceptional processing.

A second object of the present invention is that the conversion processing unit does not need to perform exceptional processing even when the input processing unit performs exceptional processing, the timing design is easy, and the timing of writing the packet to the buffer is improved. It is to provide a packet conversion device that is easy to design.

[0014]

In order to achieve the first object of the present invention, a predetermined output packet is generated after performing a predetermined conversion process on a predetermined input packet with reference to a table. In the packet conversion device for outputting the input packet, the input processing means for performing the necessary input processing on the input packet prior to the conversion processing, and the table for the input packet for which the input processing is completed by the input processing means. And a conversion processing means for performing the conversion processing, and an output processing means for generating and outputting the output packet by performing output processing on the packet subjected to the conversion processing by the conversion processing means. Is characterized by.

Further, in order to achieve the second object of the present invention, the input packet consisting of the header part and the data part is subjected to a predetermined conversion process with reference to a table, and then a predetermined output packet is processed. A packet conversion device for generating and outputting, in response to the input packet, outputting a first part including at least the header part of the input packet and a second part including at least the data part of the input packet. Input processing means for performing input processing, first storage means for storing the first portion of the input packet, and second storage means for storing the second portion of the input packet
Storage means, conversion processing means for extracting a part or all of the first portion of the input packet from the first storage means and performing the conversion processing, and conversion processing performed by the conversion processing means. A third accumulating means for accumulating the result, a part or all of the second portion from the second accumulating means, and a part or all of the result of the conversion processing from the third accumulating means. Output processing means for performing output processing of generating and outputting an output packet by performing output processing of taking out and combining each.

[0016]

As described above, according to the present invention, the conversion processing is performed on the packet for which the input processing by the input processing means is completed, and the output processing means starts the output processing after the conversion processing is completed. However, even if a certain processing unit such as an input processing unit performs an exception process, another processing unit such as a conversion processing unit does not need to perform an exception process, and therefore, the timing design may have an influence on the other processing unit. And the timing design becomes easier.

Further, when the input packet is composed of a header part and a data part following the header part like a cell in an ATM switching system, a first part including the header part and a first part including the payload part from the input processing means. The second part is output, the first part and the second part are stored in the first and second storage means, respectively, and the converted packet is stored in the third storage means, A part or all of the second part extracted from the second accumulating unit and a part or all of the packet extracted from the third accumulating unit are combined by the output processing unit and output, whereby all the parts of the packet are output. Compared with the conventional technique of writing in one storage means, the design of the timing of writing a packet into the storage means becomes easier.

Moreover, since the input processing means, the conversion processing means, and the output processing means are loosely coupled to each other through the storage means, the functions of these processing means can be designed independently and the design is easy. Becomes

Further, by providing the input processing means and the output processing means with independent clock input terminals and operating them asynchronously via the second storage means, a routing tag addition section or a routing tag in the ATM switching system can be provided. Even when the lengths of the input packet and the output packet are different as in the deleting unit, by appropriately selecting the frequency ratio of the clocks supplied to the input processing unit and the output processing unit, the input processing unit and the output processing unit can be selected. The processing throughput can be made equal. By positively utilizing the fact that the input processing means and the output processing means are asynchronous, the inside of the switching system from the routing tag addition section to the routing tag deletion section through the self-routing switch in the ATM switching system is operated at a speed higher than the line speed. By doing so, it is possible to increase the processing capability of the exchange function.

Furthermore, if the conversion processing in the conversion processing means is divided into a plurality of stages and is executed by the pipeline processing, it is possible to execute a plurality of kinds of conversion processing within the time for inputting the same one packet. It is possible to improve processing efficiency and enhance functionality.

[0021]

EXAMPLE An example in which the packet switching apparatus of the present invention is applied to the routing tag addition unit 1 in the ATM switching system shown in FIG. 8 will be described below.

FIG. 1 is a block diagram showing a configuration of a packet conversion device (hereinafter referred to as a routing tag addition unit 1) according to an embodiment of the present invention, and it is assumed that it is configured by one integrated circuit. This routing tag addition unit 1
Has three processing units, that is, an input processing unit 11, a conversion processing unit 12, and an output processing unit 13. In order to transfer cells between these processing units, a header input buffer 14 is provided between the input processing unit 11 and the conversion processing unit 12, and a payload is provided between the input processing unit 11 and the output processing unit 13. A header output buffer 16 is provided between the conversion buffer 15, the conversion processing unit 12, and the output processing unit 13.

The functions of these units will be briefly described. The input processing unit 11 responds to an input cell as shown in FIG. 2A as a necessary input process prior to the conversion process in the conversion processing unit 12, and includes a first input cell including at least a header of the input cell.
Is output (hereinafter referred to as the header part) and a second part (hereinafter referred to as the payload part) including at least the data part of the input cell is output. The header input side buffer 14 stores the header portion input from the input processing unit 11.

The conversion processing unit 12 takes out a part or all of the header part accumulated in the header input side buffer 14 and refers to the routing tag table 2 to convert it into a header pattern with a routing tag. The header output side buffer 16 stores the routing tag-attached header pattern obtained by the conversion processing unit 12. The payload buffer 15 stores the payload portion input from the input processing unit 11.

The output processing unit 13 takes out a part or all of the payload portion accumulated in the payload buffer 15 and a part or all of the routing tag-attached header pattern accumulated in the header output buffer 16.
These are combined by combining them, and a cell with a routing tag as shown in FIG. 2B is generated and output as an output cell.

Further, an input buffer management unit 17, a conversion unit buffer management unit 18, and an output unit buffer management unit 19 are provided for managing the buffers 14 to 16. The functions of these buffer management units 17 to 19 will be described in detail later.

FIFO (first-in first-out) memory 1
0 is provided as a pre-processing unit on the input side of the input processing unit 11 as required. This FIFO memory 10
The reason for providing is as follows. In order to facilitate data sampling, when transmitting a cell, a bit clock and a signal indicating the beginning of the cell may be run in parallel with the cell data signal. At this time, considering the insertion / removal of the cable forming the transmission line, the bit clock input to the routing tag addition unit 1 via the transmission line is the input processing unit 11
Not necessarily suitable for use as a clock. Therefore, a stable clock having the same frequency as the bit clock is supplied to the input processing unit 11, and the signal indicating the beginning of the cell and the cell data signal, which are synchronized with the bit clock running in parallel, are transmitted via the FIFO memory 10. Input processing unit 1
By supplying this to 1, the clock is synchronized with the clock of the input processing unit 11. This has an advantage that the processing operation of the input processing unit 11 can be stably continued even if an abnormality occurs in the clock on the transmission path.

Next, the operation of the routing tag addition unit 1 according to this embodiment will be described. A cell as shown in FIG. 2A is input to the routing tag addition unit 1. This input cell has a header portion composed of VPI (virtual path identifier) and VCI (virtual channel identifier), which are logical channel identifiers for identifying the logical channel at the input side interface point in FIG. 8, and other header information,
It consists of a payload part as a data part following this.

The input section buffer management section 17 prepares for inputting cells to the input processing section 11 by preparing buffers 14 and 15 for preparation.
The output buffer management unit 19 is inquired whether or not there is a free space. As a result of this inquiry, buffers 14 and 1
If there is a vacancy in 5, the input processing unit 11 separates the input cell into a header portion and a payload portion and outputs the input cell according to an instruction from the input portion buffer management unit 17. The bed part is written in the header input side buffer 14, and the payload part is written in the payload buffer 15.

Here, it is assumed that the input processing unit 11 separates the input cell into the header part and the payload part. However, the boundary at the time of the separation is within the range where the processing in the conversion processing unit 12 is unsupported. The write / read timing may be set so as to be convenient for the design. For example, the beginning part of the payload part may be included in a part of the header part to be separated. Further, the end portion of the header portion may be included in a part of the payload portion to be separated. Further, the separated header part and payload part may partially overlap each other, or the data that may be deleted in the header part may not be written in either of the buffers 14 and 15. Good. Further, for convenience in designing the write timing of the buffers 14 and 15, it is possible to add empty data and then write the header part and the payload part to the buffers 14 and 15, respectively. The payload part may be a part of the data part.

After the storage of the header input side buffer 14 and the payload buffer 15 is completed, the input section buffer management section 17 sets a flag to that effect. The conversion unit buffer management unit 18 is inspecting the flag of the input unit buffer management unit 17 for cell input and buffer 1
It is determined whether or not the storage in 4, 15 is completed. When the conversion unit buffer management unit 18 determines that the storage in the buffers 14 and 15 has been completed, the conversion processing unit 12 takes in the header part from the header input side buffer 14 before the conversion process. The VPI and V included in this header section
Identifying the logical channel number from the CI, determining the routing tag and the like by referring to the area of the routing tag table 2 corresponding to the logical channel using the logical channel number as a key, and adding the routing tag and the like to the header section. A header pattern with a routing tag is configured by. In this way, the header portion from the input processing unit 11 is converted into a header pattern with a routing tag by the conversion processing unit 12 and stored in the header output side buffer 16. After the conversion process is completed, the conversion unit buffer management unit 18
Sets a flag to that effect.

FIG. 3A shows an example of the structure of the area corresponding to one logical channel of the routing tag table 2, and an entry valid flag indicating whether the table is set valid or not, should be added to the cell. Routing tag,
It comprises a logical channel identifier (hereinafter referred to as the outgoing physical VCI) on the outgoing route to be added to the cell, and a passing cell number counter.

The output section buffer management section 19 checks the flag of the conversion section buffer management section 18, and the conversion processing section 1
In step 2, it is determined whether or not the conversion processing of the header portion into the header pattern with the routing tag is completed. When the output buffer management unit 19 determines that the conversion processing of the conversion processing unit 12 is completed, the output processing unit 13 causes the converted routing tag-added header pattern accumulated in the header output buffer 16 and the payload. Buffer 1
The payload part stored in 5 is linked and combined,
A cell with a routing tag as shown in FIG. 2B is generated and output as an output cell.

Although the routing tag adding section 1 has been described here, the routing tag deleting section 4 in FIG.
Can be realized with basically the same configuration. In that case,
The routing tag table 2 may be replaced with the header conversion table 5. Utilizing the fact that the routing tag addition unit 1 and the routing tag deletion unit 4 may have the same configuration as described above, the routing tag addition unit is configured by switching the mode of the packet conversion device including one integrated circuit having the configuration shown in FIG. 1 and the routing tag deleting unit 4 can be used in a time division manner.

FIG. 3B shows an example of the structure of the area corresponding to one logical channel in the header conversion table, which includes an entry valid flag indicating whether the table is set valid, a new VPI, a new VCI, and the like. It consists of new header information including and a passing cell number counter.

Next, operation algorithms of the input buffer management unit 17, the conversion buffer management unit 18, and the output buffer management unit 19 will be described. The header input side buffer 14, the payload buffer 15 and the header output side buffer 16 in FIG. 1 have cell information of the number of cells necessary for the routing tag addition section 1 or the routing tag deletion section 4 to realize a desired operation. Can accumulate
Each area is divided into a plurality of cells. The buffer management units 17 to 19 have the processing units 11 to 1 respectively.
3 writes the cell information to which area of the buffer,
It also manages a buffer pointer that indicates whether to read.

First, the operation algorithm of the input buffer management section 17 will be described with reference to the flowchart shown in FIG. The input processing unit 11 includes a buffer pointer PI for the input buffer 14 for header and a buffer 15 for payload, and a valid flag P of the buffer pointer.
IE is set. Further, a flag array FLAGI made up of a plurality of flags corresponding to a plurality of areas for accumulating cells of the buffers 14 and 15 in a 1: 1 ratio manages a flag indicating whether or not the input processing is completed. As initial settings, the buffer pointer PI is set to 0, the valid flag PIE is set to 1, and the flag array FLAGI is set to 0 (S10).

Before the input processing, the input processing section 11 first refers to the PI-th content of the flag array FLAGO of the output processing section 13 and stores it in the valid flag PIE (S17). If the PI-th content of the flag array FLAGO is 1, the header input side buffer 14 and the payload buffer 15
Indicates that there is a free area for accumulating cells, and 0 indicates that there is no free area for accumulating cells in both buffers 14 and 15.

Next, the value of the valid flag PIE is determined (S11). If PIE is 0, buffer 14 or 1
Since the empty area 5 does not exist, the header input side buffer 14 and the payload buffer 15 are not stored (S12). If PIE is 1, it is continuously determined whether or not the input cell is an allocation cell that provides transmission of significant information (S13), and if it is an allocation cell, cell input processing is performed (S15). That is, the header part of the input cell is stored in the position indicated by the buffer pointer PI of the header input side buffer 14, and the payload part of the input cell is stored in the position indicated by the buffer pointer PI of the payload buffer 15. If the input cell is not the allocated cell, the accumulation in the buffers 14 and 15 is stopped (S14).

When the allocation flag arrives as an input cell when the valid flag PIE is 1, and the cell input processing is completed in step S15, the input buffer management section 17 stores the PIth contents of FLAGI in the cell. Is set to 1, which is a value indicating that
The conversion unit buffer management unit 18 is notified that the input processing is completed, and the flag array F of the output processing unit 13 is notified.
The PIth contents of LAGO are reset to 0, and the header input side buffer 14 and the payload buffer 15
It is stored that the area for accumulating the cell is no longer empty, and the buffer pointer PI is incremented by 1 to indicate the position where the next input cell should be accumulated (S16).
After that, the above operation is repeated from step S17.

Similarly, the conversion processing unit 12 and the output processing unit 13 similarly include a buffer pointer, a valid flag, and a set of flag arrays (PC, PCE, FLAGC) and (PO, PO).
E, FLAGO), and the input processing unit 1 according to the algorithm represented by the flowcharts shown in FIGS.
The operation is performed in the same procedure as 1.

Referring to FIG. 5, conversion unit buffer management unit 18
The operation algorithm of the conversion processing unit 1
In 2, a buffer pointer PC and a valid flag PCE of the buffer pointer are set. In addition, a flag array FLAGC composed of a plurality of flags corresponding to the plurality of areas for accumulating cells of the header output buffer 16 in a one-to-one correspondence,
It manages a flag indicating whether or not the conversion process is completed. Initially, the buffer pointer PC is set to 0, the valid flag PCE is set to 0, and the flag array FLAGC is set to 0 (S20).

Before the conversion processing, the conversion processing unit 12 first refers to the PC-th content of the flag array FLAGI and stores it in the valid flag PCE (S25). Flag array FLAG
If the PC-th content of I is 1, it indicates that there is a cell that has been input and has a conversion process in the header input side buffer 12, and if it is 0, it does not exist.

Next, the value of the valid flag PCE is determined (S21). If PCE is 0, there is no cell that has been input and waits for conversion processing, so conversion processing is not performed (S2
2). If the valid flag PCE is 1, the header portion is read from the position indicated by the buffer pointer PC of the header input side buffer 14 and conversion processing is performed, and the obtained header pattern with a routing tag is output to the header output side buffer 1
The data is stored in the position indicated by the buffer pointer PC 6 (S23).

When the conversion processing is completed in step S23, the PC of the flag array FLAGC of the conversion processing unit 12 is
1 that is the value indicating that the conversion process for the th content has been completed
To the output buffer management unit 19
Is notified that the conversion processing is completed, and the contents of the PC-th of the flag array FLAGI of the input processing unit 11 are reset to 0 to store that the input-completed cells having the conversion processing have been converted. Further, the buffer pointer PC is incremented by 1 to indicate the storage position of the next converted cell (S24). After this, step S2
The above operation is repeated from 5.

Next, the operation algorithm of the output buffer management section 19 will be described with reference to FIG. 6. A buffer pointer PO and a buffer pointer valid flag POE are set in the output processing section 13. In addition, 1: 1 is set in a plurality of areas for accumulating cells of the payload buffer 15.
Array FLAGO consisting of multiple flags corresponding to
In addition, a flag indicating whether or not the output process is completed is managed. Initially, the buffer pointer PO is set to 0, the valid flag POE is set to 0, and the flag array FLAGO is set to 1 (S30).

Before the output processing, the output processing section 13 first refers to the PO-th content of the flag array FLAGC of the conversion processing section 12 and stores it in the valid flag POE (S35). If the PO-th content of the flag array FLAGC is 1, the payload buffer 15 and the header output side buffer 1
6 shows that cells that have undergone conversion processing are accumulated,
A value of 0 indicates that no data has been stored. Next, the value of the valid flag POE is determined (S31), and if the POE is 0, the cells having undergone the conversion process are not stored in the buffers 15 and 16, so the output process is not performed (S32). If the valid flag POE is 1, the header pattern with routing tag and the payload portion are read from the positions indicated by the buffer pointers PO of the buffers 15 and 16, respectively, and combined to output the allocated cell (S33).

When the output of the allocated cell is completed in step S33, the POth contents of the flag array FLAGO is set to 1 which is a value indicating that the output of the allocated cell is completed, so that the input buffer management section 17 is set. Notifying that the output processing is completed, the PO-th content of the flag array FLAGC is reset to 0, and it is stored that the area of the header output buffer 16 is empty. The PO is incremented by 1 to indicate the accumulated position of the cell to be output-processed (S2
4). Then, the above operation is repeated from step S35.

In this way, the input buffer management unit 17, the conversion buffer management unit 18, and the output buffer management unit 1
9 performs the cooperative operation by referring to the respective flags, whereby the areas of the header input side buffer 14, the payload buffer 15, and the header output side buffer 16 can be managed, whereby the input processing unit is managed. 11, the conversion processing unit 12, and the output processing unit 13 perform cooperative operation.

In the present embodiment, the input processing section 11 and the output processing section 13 are provided with independent clock input terminals, and clocks are supplied to these clock input terminals individually, whereby the input processing section 11 and the output processing section are individually supplied. 13 may be configured to operate asynchronously via the payload buffer 15. As a result, the following advantages can be expected.

In the routing tag addition unit 1, the input cell is 53 octets, whereas the output cell with the routing tag is, for example, 64 octets, and in the routing tag deletion unit 4, conversely, the input cell is 64 cells with a routing tag that is
In contrast to the octet, the output cell has 53 octets, and the lengths of the input cell and the output cell are different in each case. Therefore, unless the input processing unit 11 and the output processing unit 13 are operated asynchronously, the processing throughput per unit time of cells cannot be made equal. In order to make the processing throughputs equal, the frequency ratio of the clocks supplied to the input processing unit 11 and the output processing unit 13 may be set to, for example, 53:64.

Since the routing tag adding section 1 and the routing tag deleting section 4 input one cell having the above two kinds of clock frequencies and output the other cell, the frequency ratio of these two kinds of clocks is abnormal. It is also possible to have a means for detecting

By positively utilizing the fact that the input processing unit 11 and the output processing unit 13 are asynchronous, the routing tag addition unit 1 to the routing tag deletion unit 4 via the self-routing switch 3 in FIG. By operating the inside of the switching system at a speed higher than the line speed, the processing capability of the switching function can be increased. Since the input processing unit 11 and the output processing unit 13 are loosely coupled only by the payload buffer 15, the input unit buffer management unit 17, and the output unit buffer management unit 19, even when clocks that are not synchronized with each other are supplied. It is easy to exchange data between the processing units 11 and 13 that are operating asynchronously.

On the other hand, the conversion processing unit 12 may be designed to supply the same clock as either the input processing unit 11 or the output processing unit 13, but may be designed to supply a different clock from either of them. Input processing unit 1 to conversion processing unit 12
When a clock different from both the 1 and the output processing unit 13 is supplied, there is an advantage that a clock frequency convenient for the conversion processing can be selected.

According to the configuration of the routing tag addition unit or the routing tag deletion unit which is the packet conversion device of the present embodiment described above, there are the following excellent advantages over the prior art.

First, after the input processing in the input processing unit 11 is completed, the conversion processing unit 12 starts the conversion processing, and after the conversion processing is completed, the output processing unit 13 starts the output processing. Exception processing of one processing unit does not affect other processing units in timing design.

Specifically, for example, in consideration of the input of a cell having an abnormal length, which has been a problem in the conventional technique, the input buffer management unit 1 is provided only when a cell having a normal length is input.
It is sufficient to update the flag of No. 7 and notify the conversion processing unit 12 of the end of the input processing. The conversion processing unit 12 updates the passing cell number counter area in the routing tag table 2 by inputting an abnormal length cell. Is not affected by exception handling for.

That is, when a cell having an abnormal length is input, it is necessary to discard the cell in the input processing unit 12 as an exceptional process. Due to this cell discard, in the prior art, when the input cell is short, the conversion processing unit cancels the increment operation of the passage cell number counter in the routing tag table 2 on the way, and when it is long, the value of the passage cell number counter is incremented once. It was necessary to perform complicated control such as decrementing. On the other hand, in the embodiment, since the updating operation of the passing cell number counter is not started for the input of the cell having an abnormal length, such a complicated control in the conversion processing unit 12 becomes unnecessary.

Secondly, the input cell is divided into a header part and a payload part in the input processing part 11, the header part is stored in the header input side buffer 14, the payload part is stored in the payload buffer 15, and they are stored in different buffers. As a result, the amount of data written to each buffer 14 and 15 is smaller than that in the conventional technique in which all the cells are written into one buffer, and the timing can be easily designed.

Thirdly, the input processing section 11 and the conversion processing section 12
Since the output processing units 13 and the output processing units 13 are loosely coupled via the buffer, the functions of the processing units 11 to 13 can be designed independently, which facilitates the design.

Next, another embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of a packet conversion device according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and only the differences from the embodiment of FIG. 1 will be described. In this embodiment, the conversion processing unit 12 of FIG. 1 is independent of the other processing units, that is, the input processing unit 11 and the output processing unit 13 via the header input side buffer 14 and the header output side buffer 16, respectively. Focusing on this, the conversion processing unit 12 is divided into two parts 12a and 12b, and the conversion process is divided into two stages and executed by the pipeline process. Accordingly, the conversion unit buffer management unit 18 is also divided into two, 18a and 18b.

In this way, the processing time of conversion processing is
It is not necessary to be limited to the period for inputting one cell, and various functions can be incorporated. Specifically, for example, the first conversion processing unit 12a is provided with a traffic monitoring function for monitoring cells violating the traffic parameters declared by the user for the ATM switching system, and the second conversion processing unit 12b is provided. A configuration having a function of creating a routing tag can be adopted as in the previous embodiment.

In this case, by adopting the pipeline processing, the processing time up to the time required for inputting one cell can be allocated to each of the first and second conversion processing units 12a and 12b, so that the total processing time can be allocated. It is possible to extend the processing time up to the time of inputting 2 cells. And, nevertheless, the throughput of the cell conversion processing can be set to a throughput of one cell at the time of inputting at least one cell by the pipeline processing. The information as to whether or not to discard the packet, which is determined by the traffic monitoring function, is transferred to the output processing unit 13 via the inter-header conversion unit buffer 20 and the header output-side buffer 16, and when discarding the output processing unit 13. The cell can be discarded by replacing the cell with a non-allocated cell.

The packet converter according to the present invention may further include various error detection functions, cell number counting functions, interfaces with a processor for controlling and monitoring the packet converter as listed below. .

(1) The tables required for the conversion processing, such as the routing tag table 2 and the header conversion table 5, are generally RAMs connected to the outside of the packet conversion device.
It is composed of In order to detect the storage error in the RAM, redundant bits such as parity are stored in the RAM in addition to the original table information necessary for the conversion process, and when the conversion processing unit 12 reads the table information from the RAM, Detect the error in that information.

(2) A redundant bit such as parity is added to a cell with a routing tag to detect a transmission error, and when the packet conversion device inputs the cell, the redundant bit is used to transmit the cell. Check the reliability of.

(3) An entry valid flag indicating that a logical channel is set is provided in a table required for conversion processing such as the routing tag table 2 and the header conversion table 5 to correspond to the logical channel established by call setting. By setting only the entry valid flag in the area of the table, the packet conversion device identifies the input of the cell having the logical channel identifier other than the established logical channel. (4) A counter for counting the number of all cells (the number of packets) passing through the converter is provided inside the packet converter.

(5) In the RAM connected to the inside or the outside of the packet converter, (a) the number of passing cells, (b) the number of cells violating traffic parameters, and (c) the throughput of cell processing are exceeded for each logical channel. A table is provided with a counter for counting the number of cells discarded due to the arrival of cells (buffer overflow cell number).

(6) Since the processor reads the counter for each logical channel in the tables of (6) and (5), the packet conversion device has two registers that the processor can read and write. One of these registers is a request register that stores a request flag, a read counter type, and a logical channel designation value, and the other is a general-purpose counter display register.

When the processor reads the counter,
Specify the read counter type and logical channel in the request register and set the request flag.
With the request flag set, the packet conversion device loads the counter value from the designated counter area in the table into the general-purpose counter display register. After the load is completed, the packet conversion device immediately resets the request flag to notify the processor that the counter value has been loaded, and clears the designated counter area in the table.

The processor can confirm the end of the counter value when the request bit of the request register is reset by the packet conversion device, and can read the desired counter value by reading the general-purpose counter display register.

(7) The packet conversion device has a register which the processor can read / write, and the packet conversion device stores the table storage error of (5), the transmission line error of the cell transmission line, the unset logical channel cell error, and the traffic. When a parameter violation, a buffer overflow error, etc. are detected, the item in which the error occurred and the logical channel information of the cell in which the error occurred are displayed in the register.

(8) The packet conversion device has a register which the processor can read / write, and error information such as a cell length error detected by the packet conversion device and a clock frequency ratio error between the input processing part and the output processing part. Alternatively, the total number of cells that have passed through the packet converter is displayed in the register. (9) The error information in (8) is cleared by the packet conversion device when the processor reads the information regarding the error.

(10) Occurrence of the error shown in (7),
When the traffic parameter is violated, the packet conversion device discards the cell causing the corresponding error, but does not discard the error, or does not discard even if the error is detected, according to the instruction from the processor via the register. To do.

(11) When the packet converter outputs the allocated cell, the flow control signal from the receiving side of the cell output from the packet converter is input, and the output of the allocated cell is temporarily output according to the value of the flow control signal. Stop.

(12) A flow control signal is output to the side that sends cells to the packet conversion device, the buffer area inside the packet conversion device is all in use, and the newly arrived cells are stored inside the packet conversion device. If there is no buffer area, it is instructed to temporarily suppress the output of the allocated cell.

(13) A mode in which all input cells are discarded, a mode in which all output cells are replaced by non-allocation, a mode in which the parity of the output routing tag cell is an even parity, and an output routing tag cell When the operation mode of the packet conversion device can be selected, such as a mode in which the parity of is an odd parity, a mode in which the flow control input is replaced with a certain fixed value, etc.
The mode is switched by the instruction from the processor via the register.

By incorporating the functions as described above into the integrated circuit constituting the packet conversion device, the packet conversion device can be made to have a higher function without impairing the gist of the present invention.

In the above-mentioned embodiment, an example in which the packet conversion device according to the present invention is applied to the routing tag addition unit or the routing tag deletion unit in the ATM switching system has been described. However, the present invention is applicable to a general fixed length packet switching system and a variable It can also be applied to a long packet switching system.

[0080]

As described above, according to the present invention, the conversion processing is performed on the packet for which the input processing is completed, and the output processing is started after the conversion processing is completed. Even if an exception process is performed in a process such as an input process, it is not necessary to perform an exception process in another process such as a conversion process, which facilitates the timing design.

When the input packet is composed of the header part and the data part following the header part like a cell in the ATM switching system, the input processing part includes the first part including the header part and the first part including the payload part. 2 part and outputs the first part and the second part as the first and second parts, respectively.
Part of the second part extracted from the second buffer and a part of the packet extracted from the third buffer by accumulating the converted packet in the third buffer. Alternatively, by synthesizing and outputting all of them by the output processing unit, it becomes easier to design the timing of writing the packet to the storage means, as compared with the conventional technique of writing all the portions of the packet in one buffer.

Moreover, since the input processing unit, the conversion processing unit, and the output processing unit are loosely coupled to each other via the buffer, the functions of these processing units can be designed independently, which facilitates the design. Become.

Further, the input processing section and the output processing section are provided with independent clock input terminals, and both are operated asynchronously via the second storage means, whereby the routing tag addition section and the routing tag in the ATM switching system are operated. Even when the input packet and the output packet have different lengths like the deletion unit, by appropriately selecting the frequency ratio of the clocks supplied to the input processing unit and the output processing unit, the input processing unit and the output processing unit can be selected. The processing throughput can be made equal. By positively utilizing the fact that the input processing unit and the output processing unit are asynchronous, the inside of the switching system from the routing tag addition unit to the routing tag deletion unit through the self-routing switch in the ATM switching system operates faster than the line speed. By doing so, it is possible to increase the processing capability of the exchange function.

Furthermore, if the conversion processing in the conversion processing unit is divided into a plurality of stages and is executed by the pipeline processing, a plurality of kinds of conversion processing can be executed within the time for inputting the same one packet. It is possible to improve processing efficiency and enhance functionality.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which a packet conversion device according to the present invention is applied to a routing tag addition unit in an ATM switching system.

FIG. 2 is a diagram showing a cell format in an ATM switching system.

FIG. 3 is a diagram showing an example of a routing tag table and a header conversion table used in the ATM switching system.

FIG. 4 is a flowchart for explaining an operation algorithm of an input buffer management unit in FIG.

5 is a flowchart for explaining an operation algorithm of a conversion unit buffer management unit in FIG.

6 is a flowchart for explaining an operation algorithm of an output buffer management unit in FIG.

FIG. 7 is a block diagram showing another embodiment in which the packet conversion device according to the present invention is applied to a routing tag addition unit in an ATM switching system.

FIG. 8 is a block diagram showing a configuration of a communication path system of an ATM switching system.

FIG. 9 is a block diagram showing a configuration of a conventional routing tag addition unit.

[Explanation of symbols]

1 ... Routing tag addition unit 2 ... Routing tag table 3 ... Self-routing switch 4 ... Routing tag deletion unit 5 ... Header conversion table 10 ... FIFO memory 11 ... Input processing unit 12 ... Conversion processing unit 12a ... First conversion processing unit 12b ... second conversion processing unit 13 ... output processing unit 14 ... header input side buffer 15 ... payload buffer 16 ... header output side buffer 17 ... input section buffer management section 18 ... conversion section buffer management section 19 ... output section buffer Management Department

Claims (2)

[Claims] 1. A packet conversion device for generating and outputting a predetermined output packet after performing a predetermined conversion process on a predetermined input packet with reference to a table. Input processing means for performing necessary input processing prior to the conversion processing; conversion processing means for performing the conversion processing by referring to the table for the input packet whose input processing has been completed by the input processing means; A packet conversion device, comprising: output processing means for generating and outputting the output packet by performing output processing on the packet subjected to the conversion processing by the means. 2. A packet conversion device for generating and outputting a predetermined output packet after performing a predetermined conversion process on an input packet composed of a header part and a data part by referring to a table. Input processing means for performing input processing for outputting a first portion including at least the header portion of the input packet and a second portion including at least the data portion of the input packet in response to the packet; First storage means for storing the first portion of the input packet, second storage means for storing the second portion of the input packet, and the first storage means for storing the first portion of the input packet from the first storage means. Conversion processing means for extracting a part or all of the portion and performing the conversion processing; third storage means for storing a result of the conversion processing performed by the conversion processing means; Output by performing an output process of extracting a part or all of the second part from the second accumulating unit and a part or all of the result of the conversion process from the third accumulating unit and then combining them. An output processing unit that performs an output process of generating and outputting a packet.