JPH06213679A - Counter circuit of position pusle generator - Google Patents

Abstract

PURPOSE:To provide high resolving power and high highest response rotating speed in the counter circuit of a position pulse generator. CONSTITUTION:A position pulse generator 20 generates two phases of position pulses in answer to a clock pulse. A memory circuit 7 stores the two phases of position pulses synchronizing with the clock pulse. A memory circuit 8 stores output of the memory circuit 7, synchronizing with the clock pulse. A direction memory means 18 discriminates and stores the moving direction based on the patterns of respective stored values in the memory circuits 7, 8. A counter means 19 performes countup and countdown based on the patterns of respective value stored in the direction memory means 18, the memory circuit 7, and the memory circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit of a position pulse generator used for a servo motor of a machine tool.

[0002]

2. Description of the Related Art As a counter circuit of a position pulse generator that is pulse-excited and has a high resolution and is capable of high-speed rotation, there is a counter circuit that uses an exciting voltage as a sin wave and counts by using both positive and negative voltages. FIG. 5 is a block diagram showing an example of a counter circuit of a conventional position pulse generator,
FIGS. 6A and 6B are truth tables of the logic circuit 6, and FIG.
(A), (B), (C) are truth tables of the logic circuit 9, FIG.
(A)-(r) is a timing chart. The position pulse generator 20 comprises a clock pulse generator 1, an excitation circuit 2, a resolver 3, comparison circuits 4 and 5, and a logic circuit 6. As shown in FIGS. 9A and 9B, the clock pulse generator 1 generates a clock pulse C and a pulse signal C1 synchronized with the clock pulse C. The excitation circuit 2 is shown in FIG.
As shown in (c), sin synchronized with the pulse signal C1
A wave-shaped excitation voltage Ve is created. The resolver 3 is shown in FIG.
As shown in (d) and (e), the detection signals Va and V which are excited by the excitation voltage Ve and whose amplitude changes depending on the rotational position.
b is generated. The comparison circuits 4 and 5 are shown in FIGS.
, The detection signals Va and Vb are changed to the reference voltage Vr.
By comparing with ef, it is converted into signals A and B which are binary signals of "H" level and "L" level. Logic circuit 6
Are signals A, B as shown in FIGS. 9 (h) and 9 (i).
Then, the pulse signal C1 is logically operated according to the truth table of FIGS.

As shown in FIGS. 9 (j) and 9 (k), the memory circuit 7 latches the signals A'and B'at the rising edge of the clock pulse C to generate signals A0 and B0. As shown in FIGS. 9L and 9M, the memory circuit 8 latches the signals A0 and B0 at the rising edge of the clock pulse C to obtain the signals A1 and B1. That is, signal A
1 and B1 indicate past rotational positions by the time of the cycle of the clock pulse C with reference to the time when the signals A0 and B0 are latched. The logic circuit 9 is shown in FIG.
As shown in (q), in order to create a condition for counting up and down of the up-down counter 10 from the current rotation position and the past rotation position, the signal A1,
The signals U, D, P1 and P0 are logically operated from A0, B1 and B0 according to the truth table of FIGS. 7A, 7B and 7C. The up / down counter 10 counts up at the rising edge of the signal U, counts down at the rising edge of the signal D, and outputs the integrated count value CNT. With such a configuration, P0 is set to the 0th bit and P1 is set to
It is possible to obtain the position detection value with the first bit as the count value CNT and the second and subsequent bits.

[0004]

In the counter circuit of the position pulse generator having such a configuration, there are four combinations of the signals A0 and B0 as shown in FIG. 8, and the area names are I, II, III, respectively. IV means I-II-II at normal rotation
Repeat I-IV in sequence, and IV-III-when reversing.
Repeat II-I consecutively. And the area is IV
The condition for counting up when changing from I to IV is the condition for counting down when changing from I to IV. However, when the number of rotations is high, the sampling rate of the clock pulse C is too late to be discontinuous. For this reason, the count-up and count-down conditions as described above cannot be made, and a count error occurs. At times t0 to t2 in FIG. 9, the count-up signal U should originally rise due to such a phenomenon, but because it is not, a count error occurs.

Here, assuming that the axis multiplication angle of the resolver 3 is X and the cycle of the clock pulse C is T, the maximum response rotation speed Rmax of the counter circuit of this position pulse generator is as shown in equation 1.

[Equation 1] Rmax <1 / (4 · X · T) Today, a counter circuit for a position pulse generator with high resolution and high maximum response rotation speed is required.
In order to increase the maximum response rotational speed Rmax from the present value, it is necessary to reduce the shaft multiplication angle X or shorten the period T of the clock pulse C. But,
If the axis multiplication angle X is reduced, the resolution is reduced, and the cycle T of the clock pulse C is limited due to the characteristics of the resolver 3 and the electric circuit, and it is not easy to shorten the cycle T. Therefore, the counter circuit of the conventional position pulse generator has a problem that the maximum response rotation speed cannot be increased any further. The present invention has been made from the above circumstances,
An object of the present invention is to provide a counter circuit for a position pulse generator having high resolution and high maximum response rotation speed.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a counter circuit of a position pulse generator used for a servomotor of a machine tool, and the above object of the present invention is to provide a clock pulse from the position pulse generator. A first for storing the responded two-phase position pulse in synchronization with the clock pulse
Based on a storage means, a second storage means for storing the output of the first storage means in synchronization with the clock pulse, and a pattern of respective stored values stored in the first storage means and the second storage means. Based on the pattern of the stored values stored in the direction storing means, the first storing means, and the second storing means, and the moving direction is determined and stored in synchronization with the clock pulse. It is achieved by including counting means for counting up and counting down.

[0007]

In the present invention, the excitation voltage of the resolver and the timing for storing the binarized value of the two-phase detection signal of the resolver are synchronized, and the moving direction is determined and stored based on the stored value. In this way, since the count up and count down can be performed by taking the moving direction into consideration even in the number of revolutions which cannot be conventionally distinguished from the count up and the count down, a higher maximum response number of revolutions can be obtained.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a counter circuit of a position pulse generator of the present invention in correspondence with FIG. 5, and the same portions are designated by the same reference numerals and the description thereof will be omitted. 2 is a truth table of the logic circuit 15, FIG. 3 is a truth table of the logic circuit 13, and FIGS. 4 (a) to 4 (x) are timing charts. The direction storage unit 18 includes a logic circuit 13 and a storage circuit 14. As shown in FIG. 4 (p), the logic circuit 13 outputs the signal CC for determining the moving direction.
A logical operation is performed from W, A1, A0, B1, and B0 according to the truth table of FIG. The memory circuit 14 is shown in FIG.
As shown in (q), when the signal F is "H", the stored signal CCW indicating the moving direction is inverted and stored at the falling edge of the clock pulse C.

The counting section 19 includes a logic circuit 9 and a logic circuit 15.
And OR circuits 16 and 17, a memory circuit 12, and an up / down counter 10. The logic circuit 15 is shown in FIG.
As shown in (r) and (s), signals CCW, A1,
A logical operation is performed from A0, B1 and B0 according to the truth table of FIG. 2 to obtain signals G and H. The memory circuit 12 is shown in FIG.
As shown in (w), the OR circuit 16 ORs the signals G and U, the OR circuit 17 ORs the signals H and D, and the signals P1 and P0.
Are latched at the falling edge of the clock pulse, and the count-up signal UP and the count-down signal DOWN of the up-down counter 10 and the signals P1 ′ and P0 ′ are output. With this configuration, P0 '
0 bit, P1 'is 1 bit, and count value CNT is 2 bit
It is possible to obtain the position detection values for the eyes and beyond.

The logic circuit 13 and the memory circuit 14 of the direction memory section
The moving direction is discriminated and stored by the counter, and the logic circuit 15 of the counting unit adds the conditions for counting up and counting down when the rotational speed exceeds the conventional maximum response rotational speed. You get a number. At time t0 to t2 in FIG. 4, since the region was discontinuous, a conventional count error occurred. However, with this configuration, the count error does not occur and the device can operate normally.
The maximum response rotation speed Rmax ′ obtained with this configuration is shown in Equation 2.

## EQU00002 ## Rmax '<1 / (2.multidot.X.multidot.T) In other words, the maximum response rotation speed according to the present invention is twice as fast as the conventional one, as compared with Expressions 1 and 2. Incidentally, such a counter circuit can be used not only in the position pulse generator by the resolver described above but also in an optical position pulse generator in which the power consumption is reduced by blinking the light quantity of the light source by the clock pulse.

[0011]

As described above, according to the counter circuit of the position pulse generator of the present invention, it is possible to obtain a higher maximum response rotational speed while maintaining a high resolution. High-precision processing can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a counter circuit of a position pulse generator of the present invention, corresponding to FIG.

FIG. 2 is a diagram showing an example of a truth table of a logic circuit used in the counter circuit of the position pulse generator of the present invention.

FIG. 3 is a diagram showing an example of a truth table of a logic circuit used in the counter circuit of the position pulse generator of the present invention.

FIG. 4 is a timing chart of the counter circuit of the position pulse generator of the present invention.

FIG. 5 is a block diagram showing an example of a counter circuit of a conventional position pulse generator.

FIG. 6 is a diagram showing an example of a truth table of a logic circuit used in a counter circuit of a conventional position pulse generator.

FIG. 7 is a diagram showing an example of a truth table of a logic circuit used in a counter circuit of a conventional position pulse generator.

FIG. 8 is a diagram showing an example of a combination of signals of a counter circuit of a position pulse generator of a conventional technique and a region name.

FIG. 9 is a timing chart of a counter circuit of a conventional position pulse generator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 clock pulse generator 2 excitation circuit 3 resolver 4 comparison circuit 5 comparison circuit 6 logic circuit 7 storage circuit 8 storage circuit 9 logic circuit 10 up-down counter 12 storage circuit 13 logic circuit 14 storage circuit 15 logic circuit 16 OR circuit 17 OR circuit 18 direction memory unit 19 counting unit 20 position pulse generator

Claims (3)

[Claims] 1. A first storage means for storing a two-phase position pulse from a position pulse generator in response to a clock pulse, in synchronization with the clock pulse, and a first storage means in synchronization with the clock pulse. A second storage means for storing the output, and a direction storage for discriminating the moving direction based on the patterns of the respective stored values stored in the first storage means and the second storage means and storing the same in synchronization with the clock pulse. Position pulse, and a counting means for counting up and down based on a pattern of respective stored values stored in the direction storage means, the first storage means and the second storage means. Generator counter circuit. 2. The direction storage means comprises a logic circuit for discriminating a moving direction and a storage circuit for storing the output of the logic circuit in synchronization with the clock pulse, and the discrimination made by the logic circuit is the above-mentioned. The counter circuit of the position pulse generator according to claim 1, which is performed based on a pattern of each stored value stored in a storage circuit, the first storage means, and the second storage means. 3. The logic circuit for calculating the conditions for counting up and down based on the patterns of the respective stored values stored in the direction storing means, the first storing means and the second storing means. The position pulse generator according to claim 1, comprising: a storage circuit that stores the output of the logic circuit in synchronization with the clock pulse; and an up-down counter that counts up and down with the output of the storage circuit. Counter circuit.