JPH06216122A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06216122A JPH06216122A JP50A JP419293A JPH06216122A JP H06216122 A JPH06216122 A JP H06216122A JP 50 A JP50 A JP 50A JP 419293 A JP419293 A JP 419293A JP H06216122 A JPH06216122 A JP H06216122A
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- Prior art keywords
- film
- teos
- semiconductor device
- sion
- sio
- Prior art date
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- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関するものであり、さらに詳しくは有機シラン系化合物
を原料ガスとして用いる化学気相成長により、半導体基
板と金属配線との間の絶縁膜、金属配線間の層間絶縁膜
及びパッシベーション膜として作用する最終絶縁膜とし
て使用することができる絶縁膜を形成する方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to an insulating film between a semiconductor substrate and a metal wiring by chemical vapor deposition using an organic silane compound as a source gas. The present invention relates to a method of forming an insulating film that can be used as an interlayer insulating film between metal wirings and a final insulating film that acts as a passivation film.
【０００２】[0002]
【従来の技術】近年、VLSIデバイスの高集積化及び高密
度化が急速に進み、半導体加工技術ではサブミクロン加
工が必須のものとなってきている。サブミクロン加工が
進むに従って半導体基板の表面性状に対する要求がます
ます厳しくなり、特にアスペクト比が大きくなると表面
の凹凸がデバイス製造上の制約となってきている。この
ような問題を解決するために、最も強く望まれているの
が層間絶縁膜の平坦化技術である。2. Description of the Related Art In recent years, high integration and high density of VLSI devices have been rapidly advanced, and submicron processing has become essential in semiconductor processing technology. As submicron processing progresses, the demands on the surface properties of semiconductor substrates become more and more stringent, and surface irregularities are becoming a constraint in device manufacturing, especially when the aspect ratio becomes large. In order to solve such a problem, what is most strongly desired is a planarization technique for an interlayer insulating film.
【０００３】サブミクロンデバイス用の層間絶縁膜に要
求される特性としては、サブミクロンオーダーのスペー
スを形成すること、高アスペクト比を持つパターンに対
する優れたステップカバレージを実現すること等があ
る。これらの要求を満たす層間絶縁膜を形成する方法と
しては、有機シラン又は無機シランを原料ガスに用いた
化学気相成長法（CVD 法）が知られている。CVD 法とし
てはプラズマCVD 法、常圧CVD 法、減圧CVD 法、加圧CV
D 法、光励起CVD 法等がある。Characteristics required for an interlayer insulating film for submicron devices include forming a space of submicron order and realizing excellent step coverage for a pattern having a high aspect ratio. As a method of forming an interlayer insulating film that satisfies these requirements, a chemical vapor deposition method (CVD method) using organic silane or inorganic silane as a source gas is known. Plasma CVD method, atmospheric pressure CVD method, low pressure CVD method, pressurized CV
D method, photo-excited CVD method, etc. are available.
【０００４】これらの内、原料ガスとして有機シランを
使用し、これにオゾンを加えて行う常圧CVD 法では、形
成された絶縁膜、即ち常圧O3- 有機シランCVD シリコン
酸化膜は、その平坦性が特に優れているため層間絶縁膜
の平坦化が最も期待されている方法の１つである。この
ようなCVD 法は、特開昭６１−７７６９５号公報、「電
気化学」５６，No. ７（１９８８），５２７〜５３２頁
等に記載されている。なお、使用される有機シランとし
ては、TEOS(tetraethoxysilane) が最も一般的である。Among these, in the atmospheric pressure CVD method in which organic silane is used as a raw material gas and ozone is added thereto, the formed insulating film, that is, the atmospheric pressure O 3 -organosilane CVD silicon oxide film is Since the flatness is particularly excellent, flattening of the interlayer insulating film is one of the most expected methods. Such a CVD method is described in JP-A No. 61-77695, "Electrochemistry" 56, No. 7 (1988), pages 527-532 and the like. TEOS (tetraethoxysilane) is the most common organic silane used.
【０００５】また、VLSIのデバイスの高集積化及び高密
度化に伴い、素子の信頼性を保つために膜質を向上する
ことが要求されている。膜中に多量の水分が含まれてい
る場合又は水分を通しやすい膜質である場合には、トラ
ンジスタの電気特性に悪影響が及ぼされる。Further, with the high integration and high density of VLSI devices, it is required to improve the film quality in order to maintain the reliability of the device. When the film contains a large amount of water or has a film quality that allows water to easily pass through, the electrical characteristics of the transistor are adversely affected.
【０００６】近年、層間絶縁膜構造としては、TEOSとO2
からなりプラズマCVD 法により得られるシリコン酸化膜
（P-TEOS酸化膜）を下層として、またTEOSとO3からなり
常圧CVD 法により得られるシリコン酸化膜（O3-TEOS 酸
化膜）を上層としてそれぞれ堆積することにより形成さ
れた２層構造を用いる場合が一般的となっているが、こ
れは上層のO3−TEOS酸化膜の下地依存性が大きいためで
ある。このことは平成３年に発行された「電気学会論文
Ａ」，１１１巻７号の６５２〜６５８頁に記載されてい
る。In recent years, TEOS and O 2 have been used as an interlayer insulating film structure.
Of silicon oxide (P-TEOS oxide film) obtained by plasma CVD method as the lower layer and silicon oxide film (O 3 -TEOS oxide film) of TEOS and O 3 obtained by atmospheric pressure CVD method as the upper layer. Although the case of using a two-layer structure formed by depositing each has become common, this is due to the large base dependency of the upper O 3 -TEOS oxide film. This is described in "The Institute of Electrical Engineers of Japan", Vol. 111, No. 7, pp. 652-658, published in 1991.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このよ
うな２層構造を用いても、P-TEOS酸化膜形成後にNH3 プ
ラズマ処理等の下地処理を行わないと上層のO3-TEOS 酸
化膜の膜質が悪化し、ボイドが発生することがわかって
きている。さらに最近の報告では、膜中に水分が多いた
めP-TEOS酸化膜の膜質が非常に悪く、トランジスタの電
気特性に悪影響を及ぼすこともわかってきている。However, even if such a two-layer structure is used, the upper layer of O 3 -TEOS oxide film will not be formed unless an underlayer treatment such as NH 3 plasma treatment is performed after forming the P-TEOS oxide film. It is known that the film quality deteriorates and voids are generated. Furthermore, in recent reports, it has become clear that the film quality of the P-TEOS oxide film is extremely poor due to the large amount of water in the film, which adversely affects the electrical characteristics of the transistor.
【０００８】また、特開平２−１０８５１号公報に記載
された半導体装置の製造方法では、TEOSとO2とNH3 を原
料とし、プラズマCVD 法又は光CVD 法によりSiON膜を形
成することを提案しているが、この方法によっても上記
のような膜質の悪化やその上に形成されるO3-TEOS 酸化
膜中でのボイドの発生や、膜厚のパターン依存性が大き
い、という問題は解決されていない。Further, in the method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 2-10851, it is proposed to form a SiON film by plasma CVD method or optical CVD method using TEOS, O 2 and NH 3 as raw materials. However, this method also solves the problems such as the above-mentioned deterioration of film quality, occurrence of voids in the O 3 -TEOS oxide film formed on it, and large pattern dependence of film thickness. It has not been.
【０００９】本発明は以上の問題点を解決するものであ
り、平坦性が良く、膜質が良好で、水分が少なく、下地
依存性や膜厚のパターン依存性を解消して良好な層間絶
縁膜を形成できる半導体装置の製造方法を提供すること
を目的とするものである。The present invention solves the above problems, and has good flatness, good film quality, low water content, and good inter-layer insulation film by eliminating the underlayer dependency and the pattern dependency of the film thickness. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a film.
【００１０】[0010]
【課題を解決するための手段】本発明による半導体装置
の製造方法は、半導体装置の絶縁膜の少なくとも一部
を、有機シランとNH3 を使用したプラズマCVD 法で形成
したSiON膜を以て形成したことを特徴とするものであ
る。本発明による半導体装置の製造方法の好適実施例に
おいては、上記SiON膜を形成した後に、その上にO3とTE
OSとを用いたO3-TEOS CVD 法でシリコン酸化膜を形成す
る。In the method for manufacturing a semiconductor device according to the present invention, at least a part of the insulating film of the semiconductor device is formed by a SiON film formed by a plasma CVD method using organic silane and NH 3. It is characterized by. In a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, after forming the SiON film, O 3 and TE are formed on the SiON film.
A silicon oxide film is formed by O 3 -TEOS CVD method using OS and.
【００１１】[0011]
【作用】本発明においては、プラズマCVD 法でSiON膜を
形成するに当たり、上述した特開平２−１０８５１号公
報に記載された方法のようにO2、NH3 およびTEOSを用い
たのではボイドが発生したり、下地依存性が生ずること
を確かめ、O2を使用せずNH3 とTEOSのような有機シラン
を使用することによって膜中に窒素が含まれるSiON膜を
形成することができるので、膜中の水分が非常に少なく
なり、また下地依存性が解消されることになる。さら
に、本発明の好適実施例では、このSiON膜を下層膜と
し、その上にO3-TEOS SiO2膜を形成するが、この場合に
はO3-TEOS SiO2膜の膜質は良好となり、特に良好な層間
絶縁膜を形成できる。In the present invention, when forming the SiON film by the plasma CVD method, if O 2 , NH 3 and TEOS are used as in the method described in the above-mentioned Japanese Patent Laid-Open No. 2-10851, voids will be generated. It is possible to form a SiON film containing nitrogen in the film by using an organic silane such as NH 3 and TEOS without using O 2 , by confirming that the film is generated or depends on the substrate. The water content in the film becomes very small, and the dependency on the substrate is eliminated. Furthermore, in a preferred embodiment of the present invention, this SiON film is used as a lower layer film, and an O 3 -TEOS SiO 2 film is formed thereon, but in this case, the film quality of the O 3 -TEOS SiO 2 film becomes good, A particularly good interlayer insulating film can be formed.
【００１２】[0012]
【実施例】以下、本発明による半導体装置の製造方法の
実施例を、図面を参照しながら詳細に説明する。まず、
図１は本発明による半導体装置の製造方法によって製造
した半導体装置の断面図を示す。シリコン基板上に膜厚
が6000ÅのBPSG(Borophosphosilicate glass) 膜１を形
成した後、高さ1.0 μm 、配線幅0.5 μm 、配線間スペ
ース0.5μm のAl配線２を形成する。次にこのシリコン
基板を電極間隔が10mmの電極上に載置する。次にこのシ
リコン基板を400 ℃に加熱し、RF電源から13.56 MHz の
高周波を電極間に印加する。このときRFパワーは150W(1
W/cm2)とする。次に、TEOSを流量が100sccm のN2を用い
てバブリングして反応チャンバに供給する。このときTE
OSのバブラー温度は25℃に保持され、全圧力が１Torrに
なるように調整した。さらに、〔表１〕に示すように、
本実施例ではNH3 を30sccmの流量で反応チャンバに供給
した。このようにしてP-TEOS SiON 膜３を3000Åの膜厚
に形成した。さらに、その上にO3-TEOS SiO2膜４を8000
Åの膜厚に形成した。Embodiments of the method of manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. First,
FIG. 1 is a sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention. After forming a BPSG (Borophosphosilicate glass) film 1 having a film thickness of 6000Å on a silicon substrate, an Al wiring 2 having a height of 1.0 μm, a wiring width of 0.5 μm and a space between wirings of 0.5 μm is formed. Next, this silicon substrate is placed on the electrodes with an electrode interval of 10 mm. Next, this silicon substrate is heated to 400 ° C, and a high frequency of 13.56 MHz is applied between the electrodes from an RF power source. At this time, the RF power is 150 W (1
W / cm 2 ). Next, TEOS is bubbled with N 2 having a flow rate of 100 sccm and supplied to the reaction chamber. At this time TE
The bubbler temperature of OS was maintained at 25 ° C and the total pressure was adjusted to 1 Torr. Furthermore, as shown in [Table 1],
In this example, NH 3 was supplied to the reaction chamber at a flow rate of 30 sccm. In this way, the P-TEOS SiON film 3 was formed to a film thickness of 3000Å. Further, 8000 O 3 -TEOS SiO 2 film 4 is formed on top of it.
It was formed to a film thickness of Å.
【００１３】[0013]
【表１】 [Table 1]
【００１４】図２は比較例１の構成を示すものであり、
図１に示したP-TEOS SiON 膜３をP-TEOS SiO2 膜３ａに
置き換えたものであり、このP-TEOS SiO2 膜３ａを形成
する際には、流量が200sccm のO2を反応チャンバに供給
した。図３は比較例２の構成を示すものであり、図１に
示したP-TEOS SION 膜３をP-TEOS SiO2 膜３ａし、置き
換えたものであり、P-TEOS SiON 膜３を形成したもので
あるが、この比較例２では、流量が30sccmのNH3 と流量
が100sccm のO2をそれぞれ反応チャンバに供給した。FIG. 2 shows the structure of Comparative Example 1.
The P-TEOS SiON film 3 shown in FIG. 1 is replaced with a P-TEOS SiO 2 film 3a, when forming the P-TEOS SiO 2 film 3a, the flow reaction of O 2 200sccm chamber Supplied to. FIG. 3 shows the structure of Comparative Example 2, in which the P-TEOS SION film 3 shown in FIG. 1 is replaced with a P-TEOS SiO 2 film 3a, and a P-TEOS SiON film 3 is formed. In Comparative Example 2, NH 3 with a flow rate of 30 sccm and O 2 with a flow rate of 100 sccm were supplied to the reaction chamber.
【００１５】上述した実施例で形成されたP-TEOS SiON
膜の特性を〔表２〕に示す。P-TEOS SiON formed in the above embodiment
The characteristics of the film are shown in [Table 2].
【００１６】[0016]
【表２】 又、比較例１と２で形成したP-TEOS SiO2 膜の膜特性を
〔表３〕に示す。[Table 2] The film characteristics of the P-TEOS SiO 2 films formed in Comparative Examples 1 and 2 are shown in [Table 3].
【００１７】[0017]
【表３】 [Table 3]
【００１８】図１に示した本発明の実施例では、P-TEOS
SiON 膜３の上に形成したO3-TEOSSiO2膜４中にはボイ
ドが発生せず、疎パターン５及び密パターン６での03-T
EOSSiO2酸化膜の膜厚依存性がなく、均一の膜厚で形成
されていることがわかる。また、P-TEOS SiON 膜３を形
成する際にO2を用いていないため膜中に窒素が入ったP-
TEOS SiON 膜を形成できるので、この膜中の水分は非常
に少なくなる。In the embodiment of the present invention shown in FIG. 1, P-TEOS is used.
Voids do not occur in the O 3 -TEOSSiO 2 film 4 formed on the SiON film 3, and 0 3 -T in the sparse pattern 5 and the dense pattern 6
It can be seen that the EOSSiO 2 oxide film is formed with a uniform film thickness without dependence on the film thickness. In addition, since O 2 is not used when forming the P-TEOS SiON film 3, P- containing nitrogen in the film is used.
Since the TEOS SiON film can be formed, the water content in this film is extremely low.
【００１９】図２に示すように、比較例１により形成さ
れたP-TEOS SiO2 膜３ａの上に形成されたO3-TEOS SiO2
膜４中にはボイド７が発生し、また疎パターン５ではO3
-TEOS SiO2膜４の膜厚が小となり、それに対して密パタ
ーン６では膜厚が大となるので膜厚依存性があることが
わかる。また、P-TEOS SiO2 膜３ａ中には窒素が入って
いなので、この膜中には水分が多く含まれたものとなっ
ている。As shown in FIG. 2, O 3 -TEOS SiO 2 formed on the P-TEOS SiO 2 film 3a formed in Comparative Example 1
Voids 7 occur in the film 4, and O 3 in the sparse pattern 5
It can be seen that the film thickness of the TEOS SiO 2 film 4 becomes small, whereas the film thickness of the dense pattern 6 becomes large, so that there is film thickness dependence. Further, since nitrogen is contained in the P-TEOS SiO 2 film 3a, this film contains a large amount of water.
【００２０】図３に示した比較例２でも、P-TEOS SiO2
膜３ａの上に形成されたO3-TEOS SiO2膜４中にはボイド
７が発生し、またP-TEOS SiO2 膜３ａの成膜ガスとして
O2が添加されたためＮが膜中に入らずこれが原因で比較
例１と同じ膜質のP-TEOS SiO 2 膜が形成され、疎パター
ン５ではO3-TEOS SiO2膜４の膜厚が小となるのに対して
密パターン６では膜厚が大となるので膜厚依存性がある
ことがわかる。Also in Comparative Example 2 shown in FIG. 3, P-TEOS SiO2
O formed on the film 3a3-TEOS SiO2Voids in membrane 4
7 occurs, and P-TEOS SiO2As a film forming gas for the film 3a
O2Because N was added, N did not enter the film and this was the cause of comparison.
P-TEOS SiO with the same film quality as in Example 1 2Membrane formed and sparse putter
O in 53-TEOS SiO2Whereas the film thickness of the film 4 becomes small,
Since the dense pattern 6 has a large film thickness, there is film thickness dependence.
I understand.
【００２１】〔表４〕に、P-TEOS SiON 膜の形成時にお
けるO2とNH3 の流量に対するO3-TEOS SiO2膜に発生する
ボイド及びパターン依存性の有無を示す。〔表４〕によ
り本発明のようにO2を用いない場合にはボイドが発生せ
ず、かつ、パターン依存性もないことがわかる。[Table 4] shows the presence / absence of voids and pattern dependence generated in the O 3 -TEOS SiO 2 film with respect to the flow rates of O 2 and NH 3 during the formation of the P-TEOS SiON film. [Table 4] shows that when O 2 is not used as in the present invention, no void is generated and there is no pattern dependence.
【００２２】[0022]
【表４】 [Table 4]
【００２３】[0023]
【発明の効果】本発明による半導体装置の製造方法によ
れば、O2を使用せず、NH3 とTEOSのような有機シランを
使用したプラズマCVD 法でP-TEOS SiON 膜を形成するの
で、膜中に窒素が含まれるようになり、膜中の水分が非
常に少なくなる。また、下地依存性が解消されているた
めこのP-TEOS SiON 膜上に、例えばO3-TEOS SiO2膜を形
成した場合でも、このO3-TEOS SiO2膜中にボイドが発生
することがないとともに膜厚依存性もなくなり、良好な
層間絶縁膜を形成できるという効果を有する。According to the semiconductor device manufacturing method of the present invention, the P-TEOS SiON film is formed by the plasma CVD method using NH 3 and organosilane such as TEOS without using O 2 . Nitrogen is contained in the film, and the amount of water in the film becomes very small. Further, since the underlayer dependency is eliminated, voids may occur in the O 3 -TEOS SiO 2 film even when an O 3 -TEOS SiO 2 film is formed on the P-TEOS SiON film. In addition, there is no film thickness dependency, and there is an effect that a good interlayer insulating film can be formed.
【図１】本発明による半導体装置の製造方法の実施例に
より得られる半導体装置の断面図を示す。FIG. 1 is a sectional view of a semiconductor device obtained by an embodiment of a method for manufacturing a semiconductor device according to the present invention.
【図２】比較例１により得られる半導体装置の断面図を
示す。FIG. 2 shows a cross-sectional view of a semiconductor device obtained in Comparative Example 1.
【図３】比較例２により得られる半導体装置の断面図を
示す。FIG. 3 shows a cross-sectional view of a semiconductor device obtained in Comparative Example 2.
１ BPSG膜 ２ Al配線 ３ P-TEOS SiON 膜 ３ａ P-TEOS SiO2 膜 ４ O3-TEOS SiO2膜 ５ 疎パターン ６ 密パターン ７ ボイド1 BPSG film 2 Al wiring 3 P-TEOS SiON film 3a P-TEOS SiO 2 film 4 O 3 -TEOS SiO 2 film 5 Sparse pattern 6 Dense pattern 7 Void
Claims (3)
を、有機シランとNH3とを使用したプラズマCVD 法で形
成したSiON膜を以て形成したことを特徴とする半導体装
置の製造方法。1. A method of manufacturing a semiconductor device, wherein at least a part of an insulating film of the semiconductor device is formed by a SiON film formed by a plasma CVD method using organic silane and NH 3 .
とする請求項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the organic silane is TEOS.
とTEOSとを用いたCVD 法で酸化膜を形成することを特徴
とする請求項１又は２記載の半導体装置の製造方法。3. After forming the SiON film, O 3 is formed on the SiON film.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is formed by a CVD method using TiO2 and TEOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06216122A (en) | 1993-01-13 | 1993-01-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06216122A (en) | 1993-01-13 | 1993-01-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216122A true JPH06216122A (en) | 1994-08-05 |
Family
ID=11577839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50A Pending JPH06216122A (en) | 1993-01-13 | 1993-01-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216122A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6437424B1 (en) * | 1999-03-09 | 2002-08-20 | Sanyo Electric Co., Ltd. | Non-volatile semiconductor memory device with barrier and insulating films |
| DE102004003337A1 (en) * | 2004-01-22 | 2005-08-18 | Infineon Technologies Ag | Plasma enhanced chemical vapor deposition method, silicon-oxygen-nitrogen containing material and layer assembly |
| US7807563B2 (en) | 2004-10-15 | 2010-10-05 | Infineon Technologies Ag | Method for manufacturing a layer arrangement and layer arrangement |
| WO2012077330A1 (en) * | 2010-12-06 | 2012-06-14 | シャープ株式会社 | Semiconductor device, method for manufacturing same, solid-state imaging device, method for manufacturing same, and electronic information device |
-
1993
- 1993-01-13 JP JP50A patent/JPH06216122A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6437424B1 (en) * | 1999-03-09 | 2002-08-20 | Sanyo Electric Co., Ltd. | Non-volatile semiconductor memory device with barrier and insulating films |
| DE102004003337A1 (en) * | 2004-01-22 | 2005-08-18 | Infineon Technologies Ag | Plasma enhanced chemical vapor deposition method, silicon-oxygen-nitrogen containing material and layer assembly |
| WO2005071739A3 (en) * | 2004-01-22 | 2006-03-02 | Infineon Technologies Ag | Plasma-excited chemical vapor deposition method, silicon/oxygen/nitrogen-containing material and layered assembly |
| US7755160B2 (en) | 2004-01-22 | 2010-07-13 | Infineon Technologies Ag | Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly |
| US7807563B2 (en) | 2004-10-15 | 2010-10-05 | Infineon Technologies Ag | Method for manufacturing a layer arrangement and layer arrangement |
| WO2012077330A1 (en) * | 2010-12-06 | 2012-06-14 | シャープ株式会社 | Semiconductor device, method for manufacturing same, solid-state imaging device, method for manufacturing same, and electronic information device |
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