JPH0620266B2 - Autofocus circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement of an autofocus circuit used in a video camera.

(B) Conventional technology Various proposals have been made for the autofocus control mechanism that samples the luminance signal obtained from the video camera and rotates the focus ring so that the high frequency component is maximized. Has been done. For example, Japanese Patent Application Sho 58
No. 202332 discloses one example thereof.

In the prior art, as shown in FIG. 3, a luminance signal is input to an AD conversion circuit (4) via a high pass filter (1), an absolute value conversion circuit (2), and an envelope detection circuit (3). This AD conversion circuit
(4) executes AD conversion only during the period when the gate control output is generated from the gate control circuit (5) which controls and inputs the vertical and horizontal synchronizing signals separated from the luminance signal. Therefore, the gate control circuit (5) previously sets only the central portion of the screen as the sampling area, so that the AD conversion output in this sampling area can be obtained. This A
The D conversion output is sequentially stored in the memory (6), and after the AD conversion is completed, the arithmetic circuit (7) outputs all A in the sampling area.
The D conversion value is added during one field period, and this operation output is further stored in the first memory (8) and in the second field in the second memory.
The contents are transferred to (9) and the contents of the first and second memories (8) and (9) are compared to control the focus motor.

(C) Problems to be Solved by the Invention In the above-mentioned prior art, the focus motor control is judged by the accumulated result of the AD conversion outputs of the entire sampling area.
When a video camera that is in focus in a dark position is panned to capture an object at the same distance, if the object has a complicated shape or if it is bright, the focus motor responds sensitively to slight movements of the object. There is a fear of re-driving. On the contrary, when the video camera in the focused state is panned and the objects at different distances are imaged, if the level change happens to be small in the entire sampling area, the focus motor cannot be re-driven.

(D) Means for Solving the Problems The present invention is an autofocus circuit, which includes area changing means for periodically changing the sampling area when the focus motor is stopped, and an arithmetic circuit output for each of the changed sampling areas. It is characterized by comprising a storage means for storing and a comparison means for comparing information of the storage means relating to the same sampling area and restarting the focus motor by the output thereof.

(E) Operation Since the present invention is configured as described above, when the focus motor is stopped, the sampling area is changed variously, and the change amount of the luminance signal for re-driving the focus motor is surely detected.

(F) Example An example of the present invention will be described below with reference to the drawings.

The luminance signal (Y) in the picked-up video signal obtained from the video camera is input to the high-pass filter (HPF) (10) to separate high-frequency components of 100 KHz or more, and then this high-pass output is output. It is input to the absolute value conversion circuit (11). This absolute value output is input to the envelope detection circuit (12) and converted into a detection output that follows the level change of the absolute value output.
It is input to the D conversion circuit (detection means) (13). This AD converter circuit (13) is 5KH from the oscillator circuit (OSC) (14).
AD conversion is performed using the z pulse as a timing pulse. This AD conversion output is input to the arithmetic circuit (15).

The arithmetic circuit (15) synchronizes with the output pulse of the oscillator circuit (14)
The D conversion output is accumulated, and the accumulation is reset by the vertical synchronizing signal (Vsync) so that it is performed for each field. The vertical sync signal is obtained from the luminance signal (Y) through the sync separation circuit (16). The accumulation period is controlled by the area control circuits (17) and (18) so as to correspond to the sampling area near the center of the screen.

The area control circuit (17) determines the vertical sampling area of the screen, and uses the vertical sync signal as a reset input, that is, as an initial value, the horizontal sync signal (Hsync) extracted from the sync separation circuit (16). Is counted, and when the preset value set in the area control constant changing circuit (19) is reached, a high (H) level output is generated. On the other hand, the area control circuit (18) determines the horizontal sampling area of the screen, uses the horizontal sync signal as a reset input, counts the pulses of the oscillation circuit (14), and changes the area control constant circuit (19). When the preset value is reached, the H level output is generated. As the set value, that is, the control constant, as shown in FIG. 2, h ₁ <(Hsync count number) <in the vertical direction.
h ₃ , so that the sampling area is located at c ₁ <(count of c) <c ₃ in the horizontal direction (h ₁ , h ₃ ,
c ₁ , c ₃ ) are given. The area control circuit (1
The outputs (7) and (18) are supplied as a control signal to the arithmetic circuit (15) via the AND gate (20), and the arithmetic circuit (15) accumulates only when the control signal is at the H level.

After the AD conversion is completed, the output of the arithmetic circuit (15) thus obtained is
It is transferred to the first memory (21) and then transferred to the second memory (22) in the next field. Therefore, the first and second memories (21) (2
2) The first comparison circuit (29) having two inputs as outputs compares the operation outputs before and after one field.

Sampling area (S stored in the first memory (21)
Assuming that the level of the luminance signal in A) is S1, the level one field before is S2, and the focusing limit value is ε, S1-S2>
At the time of ε, the normal rotation command signal is supplied from the first comparison circuit (29) to the focus motor control circuit (30) which constitutes the control means together with the first comparison circuit (29) and is driven in one direction in the initial state. Focus motor (31), compared to the output of the first memory (21),
As long as the output of the second memory (22) is small, the normal rotation command signal is received to continue driving. When the output of the second memory (22) becomes large (S2-S1)> ε, a reversal command signal is supplied, the focus motor (31) is reversed, and the focus ring is always brought to the in-focus position. You

| S1-S2 | <ε, that is, when the absolute value of the level change amount is smaller than ε, the H level signal is supplied from the first comparison circuit (29) to the input terminal (32a) of the flip-flop (FF) (32). FF (32) output is in the initial state from L level to H
Change to level, this is the focus motor control circuit (30)
To the stop command signal, and the focus position where the drive of the focus motor (31) is stopped is held.

On the other hand, this FF (32) output is the area control constant changing circuit (19).
Will also be supplied. In response to this, the 4-state counter (3
The area control constant changing circuit (19) that constitutes the area changing means together with 3) is a constant fixed state when the focus motor is driven,
That is, the constant is moved to the constant changing state from the state where the constant is fixed as (h ₁ , h ₃ , c ₁ , c ₃ ) so that the sampling area becomes (SA). In this constant changing state, the vertical sync signal is used as a count, and the constants for controlling the area control circuits (17) and (18) are controlled by the output of the 4-state counter (33) which outputs the address signal according to the count number. The constant changing circuit (19) can be switched to a preset constant for setting a plurality of sub-sampling areas.

The subsampling areas (I), (II), (III), and (IV) are set to the second by the constants for setting the subsampling areas.
It is set as shown. That is, the subsampling area (I) creation constants are (h ₁ , h ₂ , c ₁ , c ₂ ), (I
I) Creation constants are (h ₁ , h ₂ , c ₂ , c ₃ ), (III)
The production constants are (h ₂ , h ₃ , c ₁ , c ₂ ), and (IV) the production constants are (h ₂ , h ₃ , c ₂ , c ₃ ).

Further, the 4-state counter (33) has an address signal of 0, 1, 2, 3, 0, 1, 2, which indicates a remainder number of 4, that is, the value of n of the count number = 4m + n (m, n: integer). ... is output sequentially. In this way, the sampling area determined by the area control circuits (17) and (18) is divided into the sub-sampling areas (I) (II) (III) (IV), and the arithmetic circuit (15) outputs the area (I ) (II) (III) (I
For each V), the level evaluation value is sequentially accumulated in the cycle of one field, and the second, third, fourth, ... Eighth memories (22) (23) ... (2
It is transferred together with 8) to the first memory (21) constituting the storage means (39).

The contents of the first memory (21) are stored in the second memory (2
In step 2), one field later, the data is transferred to the eighth memory (28) in sequence such as the third memory (23). Therefore, the first memory (21) and the fifth memory (25), the second memory (22) and the sixth memory (26), the third memory (23) and the seventh memory (27), the fourth memory
(24) and the eighth memory (28) respectively store the latest data and the data four fields before in the same sub-sampling area.

Comparing means with the third, fourth and fifth comparison circuits (35) (36) (37)
The second comparison circuit (34) constituting the (40) compares the contents of the first memory (21) and the fifth memory (25), and the third, fourth and fifth comparison circuits (35) (36) (37) is the second memory (22) and the sixth memory (2
6), 3rd memory (23), 7th memory (27), 4th memory (24)
And the contents of the 8th memory (28) are compared, and area (I) (II)
(III) When the level change amount from the previous four fields exceeds the preset threshold value every (IV), an H level output is output to the discrimination circuit (38). The discriminating circuit (38) makes a majority decision, and the second, third, fourth and fifth comparing circuits (34) (3
5) As a result of the comparison in (36) and (37), when the threshold value is exceeded in two or more areas, an H level discrimination output is issued. This discrimination output is supplied to the input terminal (32b) of the FF (32), and the FF
The value of (32) is inverted from the H level to the L level, the stop command signal to the focus motor control circuit (30) also becomes the L level, the focus motor (31) is released from the stopped state, and becomes the re-driving state.

At the same time, since the change command signal to the area control constant changing circuit (19) also becomes L level, the area control constant changing circuit (19) shifts from the constant changing state to the constant fixed state, and the constant is the area control circuit (17) ( The sampling area returns to the original value determined as SA by 18). Thus focus motor
(31) is in a driving state until it becomes a focused state again.

Although the sub-sampling area is set to four areas in the present embodiment, it is possible to further subdivide and set many areas by replacing the memory, the comparison circuit, and the state counter. Further, it goes without saying that the operation after AD conversion may be realized by software using a microcomputer.

(G) Effect of the Invention As described above, according to the present invention, when the focus motor is stopped, it is possible to determine whether or not the focus position is the focus area by subdividing the sampling area. Realizable and extremely effective.

[Brief description of drawings]

1 and 2 relate to an embodiment of the present invention. FIG. 1 is a circuit block diagram, FIG. 2 is a diagram showing a sampling area region on a photographing screen, and FIG. 3 is a circuit block of a conventional example. It is a figure. (13) ... AD conversion circuit (detection means), (15) ... arithmetic circuit, (17) (18) ... area control circuit, (19) ... area control constant changing circuit (area changing means), ( 29) ... First comparison circuit (control means), (30) ... focus motor control circuit (control means), (31) ... focus motor, (33) ... 4
State counter (area changing means), (39) ... storage means, (40) ... comparison means.

Claims (1)

[Claims] 1. An area selection means for selecting, as a selection area, either a sampling area set in advance on a screen or a sub-sampling area which is each small block when the area is divided into a plurality of areas, and within the selection area. Detection means for outputting a focus evaluation value by cumulatively calculating the high frequency component level of the image pickup luminance signal corresponding to, and fixing the selected area to the sampling area and the output of the detection means is near the peak. Focus control means for performing a focusing operation until reaching a point, and monitoring means for monitoring the change state of the output of the detecting means by changing the selected area to the sub-sampling area after the focus operation is completed. The autofocus circuit restarts the focusing operation according to