JPH06202148A - Thin-film transistor for liquid crystal display device and its production - Google Patents

Abstract

PURPOSE:To provide the thin-film transistor(TFT) for a liquid crystal display device at a good yield without display defects by simple stages by preventing the overhang by ohmic barrier layers, thereby preventing line defects and spot defects and enhancing the reliability of connection to display electrodes and, a process for production of such TFT. CONSTITUTION:The drain electrode and source electrode of this TFT consist of a three-layered structure consisting of a first layer 29a of the source electrode and first layer 29b of the drain electrode which are the ohmic barrier layers with semiconductor layers 27a, 27b, a second layer 30b of the source electrode and second layer 30b of the drain electrode which consist of a low-resistance material and are main signal wiring layers, and a third layer 31a of the source electrode and third layer 31b of the drain electrode which are battery reaction preventive layers. Similarly the low-resistance data line consists of a three- layered structure consisting of a first layer data wiring 29c which is the ohmic barrier layer, a second layer data wiring 30c which consists of a low-resistance material and is the main wiring layer and a third layer data wiring 31c which is the battery reaction preventive layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a thin film transistor thereof and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor (hereinafter referred to as a TFT
(Hereinafter referred to as)) and a display electrode are arranged in a matrix, and an active matrix type liquid crystal display element (hereinafter referred to as TFT-LCD) is used. Generally, a TFT array is arranged on a transparent substrate such that a plurality of address wirings and data wirings intersect each other at right angles in a row direction and a column direction, and a gate is provided at each intersection of these address wirings and data wirings. A plurality of thin film transistors whose electrodes are connected to address lines and drain electrodes to data lines are arrayed, and a plurality of display electrodes connected to the source electrodes of the thin film transistors are arrayed in a matrix.

TFT of such a conventional TFT-LCD
For example, the one described in JP-A-3-9569 is known, and regarding the TFT array thereof,
This will be described with reference to FIGS. 4 and 5. Note that FIG. 4 shows a cross section taken along the line AA of FIG. First, a gate electrode 2 made of Al, Al-based alloy, Ta, Ta alloy, Cr or the like is formed on an insulating transparent substrate 1 such as a glass substrate by sputtering and a predetermined processing method.

Then, if necessary, the surface of the gate electrode is anodized into a predetermined shape, so that the first gate insulating film 3 is formed.
To form. Next, the SiN film 4, which is the second gate insulating film, and n ^- a-Si, in which impurities that will be the semiconductor layer are non-doped
(Amorphous silicon) film 5, n doped with impurities
⁺ a-Si (amorphous silicon) layer 6 is sequentially deposited by plasma CVD.

Then, the n ⁺ a-Si layer 6 and the n ^- a-S are formed.
Elements are separated by processing the i layer 5 into a predetermined shape. Next, a transparent display electrode 7 having a predetermined shape is formed by sputtering and processing a transparent film made of ITO. Further, a metal having a two-layer structure of the Mo film 8 and the Al film 9 is deposited by sputtering and processed into a predetermined shape, so that the first layer 8a of the source electrode, the second layer 9a of the source electrode and the drain electrode The first layer 8b, the second layer 9b of the drain electrode, the first layer 8c of the data wiring, and the second layer 9c of the data wiring are formed. The first layer 8a of the source electrode is connected to the transparent display electrode 7 made of ITO.

At this time, the Al film 9 and the Mo film 8 can be etched with the same phosphoric acid-based etching solution (a mixed solution of phosphoric acid, nitric acid, acetic acid, and water). Also, M
The o film 8 has an effect as an ohmic barrier between the n ⁺ a-Si layer 6 and the Al film 9, and since the Al film 9 has a low resistance, it serves as a main wiring electrode. The channel region of the thin film transistor is formed by removing the unnecessary n ⁺ a-Si layer 6 by dry etching using the source and drain electrodes as a mask.

Finally, the surface protective film 10 made of SiN film
Is formed into a predetermined shape by plasma CVD and processing, whereby a thin film transistor for a liquid crystal display is completed.

[0008]

However, in the above-described conventional thin film transistor for liquid crystal display device, the Mo film 8 and the A film forming the source and drain electrodes of the two-layer structure are formed.
Although the 1 film 9 can be etched with the same etching solution, it has the following problems. (1) Since the etching rate of the lower Mo film 8 that is an ohmic barrier is as high as 4 to 6 times that of the Al film 9, the lower Mo film 8 is etched when the upper Al film 9 is etched. The Al film 9 tends to overhang,
The Al film 9 is easily peeled off or turned over.

Due to these factors, in the later process, the sauce,
The drain electrode is broken, resulting in a line defect or a point defect in the liquid crystal display device. In order to prevent this overhang, an alloy film of a Mo film and a dissimilar metal W is used as a lower layer film to control the etching rate and prevent the overhang.

However, when forming an alloy film of a Mo film and a dissimilar metal W, there is no reproducibility of the sputtered film quality.
Etching rate control becomes unstable and overhang tends to occur. Further, there is a problem such as an increase in cost due to the production of an alloy target for sputtering. (2) Further, since it is necessary to reduce the space, the connection between the transparent display electrode made of the ITO film and the source electrode is made via the first layer made of Mo.
Since it is necessary to reduce the space with respect to the first layer made of, a small contact area can be taken, and sufficient electrical connection is difficult.

Due to the above-mentioned causes, there has been a problem that a display defect of the liquid crystal display occurs, the yield is lowered, and the cost is increased. The present invention solves the above problems and prevents line defects and point defects by preventing overhang due to the ohmic barrier layer, and
Improves the reliability of connection with the display electrode, and in a simple process,
Provided are a thin film transistor for a liquid crystal display device having no display defect and a high yield, and a manufacturing method thereof.

[0012]

In order to achieve the above-mentioned object, the present invention provides a thin film transistor and a source electrode of the thin film transistor at each intersection of a plurality of address wirings and a plurality of data wirings arranged to intersect each other. And a plurality of display electrodes connected to one of the drain electrodes are arranged in a matrix, and the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode. In the device thin film transistor, the drain electrode, the source electrode and the data line are a first layer which is an ohmic barrier layer with the semiconductor layer, a second layer which is a low resistance material and is a main signal wiring layer, and a battery reaction prevention It is characterized by having a three-layer structure including a third layer which is a layer.

In addition, a thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are formed in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged to intersect each other. In a method for manufacturing a thin film transistor for a liquid crystal display device in which a plurality of thin film transistors are arranged, the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode, respectively, on the insulating transparent substrate, the gate is formed. An electrode, an insulating film on the gate electrode, a semiconductor layer in which impurities are non-doped above the insulating film corresponding to the gate electrode, and electrically separated from the non-doped semiconductor layer. A doped semiconductor layer,
A first step of forming a display electrode partially laminated on the semiconductor layer doped with the impurities, a first layer as an ohmic barrier layer thereon, and a main signal wiring layer made of a low resistance material. A second step of sequentially laminating a certain second layer and a third layer which is a battery reaction prevention layer, and a first step of forming the ohmic barrier layer by processing the second layer and the third layer which is a battery reaction preventing layer in a predetermined shape and under predetermined conditions
A third step of forming a source electrode, a drain electrode and a data wiring having a three-layer structure including a layer, a second layer which is a main signal wiring layer, and a third layer which is a battery reaction prevention layer, and the source electrode And a fourth step of forming a surface protective film on the drain electrode and the data wiring.

[0014]

According to the present invention, as described above, the data wiring is the first layer data wiring 29c which is the ohmic barrier layer (Cr) 29, and the main signal wiring layer (Al or Al series) made of a low resistance material. Alloy) 30 second layer data wiring 3
0c and a third layer data wiring 31c which is a battery reaction prevention layer (Mo) 31, and has a three-layer structure. Similarly, drain electrodes and source electrodes of a plurality of thin film transistors are
The first layer 29a of the source electrode and the first layer 29b of the drain electrode which are ohmic barrier layers (Cr) 29 with the semiconductor layer.
And a second layer 30a of a source electrode and a second layer 30b of a drain electrode which are main signal wiring layers (Al or Al-based alloy) 30.
And a third layer 31a of the source electrode and the third layer 31b of the drain electrode, which are the battery reaction prevention layer (Mo) 31, have a three-layer structure.

Therefore, the ohmic barrier layer (Cr)
Since the etching rate of the lower layer is higher than that of the main signal wiring layer (Al or Al-based alloy) which is the upper layer, and the etching selection ratio is large, when the upper main signal wiring layer (Al or Al-based alloy) is etched, The lower ohmic barrier layer (Cr) is not etched, and the overhang of the main signal wiring layer (Al or Al-based alloy) caused by the side etching of the first layer does not occur.

Further, since the ohmic barrier layer (Cr) is not an alloy film, the reproducibility of the sputtered film quality is good,
A stable etching rate control can be performed. Furthermore,
The Mo film and the Al film can be collectively etched with the same etching solution, and the Mo film has an etching rate of 4 than that of the Al film.
Since it is ~ 6 times faster, the upper Mo film is formed in a tapered shape during the etching of the lower Al film, and the Si
The step coverage of the N protective film is improved.

The display electrode made of ITO has a lower layer n ⁺
It is sandwiched between the a-Si layer and the upper ohmic barrier layer (Cr layer), and the display electrode has a good ohmic contact property with the ohmic barrier layer (Cr), and a sufficient contact area can be obtained. Therefore, the ohmic contact property between the display electrode and the source electrode becomes particularly good, and the connection reliability can be improved.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a sectional view of a thin film transistor for a liquid crystal display device showing an embodiment of the present invention, FIG. 2 is a partial plan view of the liquid crystal display device, and FIG. 3 is a sectional view of a manufacturing process of the thin film transistor for a liquid crystal display device. Note that FIG. 1 shows a cross section taken along the line BB of FIG.

In FIG. 1, reference numeral 21 is an insulating transparent substrate such as a glass substrate. A gate electrode 22 is formed on the insulating transparent substrate 21, and the surface of the gate electrode 22 is anodized into a predetermined shape. Further, the first gate insulating film 23 is provided, and the SiN film 24 which is the second gate insulating film is deposited on the first gate insulating film 23. An impurity is a non-doped semiconductor layer n above the SiN film 24 corresponding to the gate electrode 22.
^An a-Si layer 25 is formed, and a blocking layer 26 made of SiN is formed thereon. Furthermore, on the n ^- a-Si layer 25 and the blocking layer 26, which are semiconductor layers, n ⁺ is doped with impurities on the source electrode side.
An a-Si ohmic layer 27a and an n ⁺ a-Si ohmic layer 27b doped with impurities on the drain electrode side are formed.

The display electrode 28 made of ITO is formed on the second gate insulating film so as to be connected to the n ⁺ a-Si ohmic layer 27a on the source electrode side. The source electrode portion, the drain electrode portion, and the data wiring portion have a film thickness of 100 to 5
The first layer 29a of the source electrode portion, the first layer 29b of the drain electrode portion, and the first layer data line 29 made of Cr of 00Å
c is an Al layer having a film thickness of 1000 to 5000Å as a main signal wiring layer (second metal layer) 30 on the upper layer thereof.
Alternatively, the second layer 30a of the source electrode and the second layer 30 of the drain electrode are made of an Al-based alloy containing Al and at least one kind of metal selected from Ti, Mo, W, Ta, and Cu.
b, and the second-layer data wiring 30c are further formed thereon as a battery reaction prevention layer (third metal layer) 31 with a film thickness of 1
The third layer 3 of the source electrode, which is made of Mo of from 00 to 500Å
1a, a third layer 31b of the drain electrode, and a third layer data wiring 31c are formed respectively.

That is, the source electrode (2
9a, 30a, 31a) and drain electrodes (29b, 30)
b, 31b), the first layer data wiring 29c, the second layer data wiring 30c, and the third layer data wiring 31c are formed. And, on these surfaces SiN
A surface protective film 32 made of a film is formed. The plane of the liquid crystal display device thus formed is shown in FIG. Here, the surface protection film is omitted.

A method of manufacturing a thin film transistor for a liquid crystal display device showing an embodiment of the present invention will be described below. First, as shown in FIG. 3 (A), Al, Al-based alloy, Ta, Ta alloy, on an insulating transparent substrate 21 such as a glass substrate,
The gate electrode 22 made of Cr or the like is formed by sputtering and a predetermined processing method.

Next, if necessary, the surface of the gate electrode 22 is anodized into a predetermined shape on the gate electrode 22 to form a first gate insulating film 23. Next, FIG.
As shown in (B), the SiN film 24 that is the second gate insulating film, and the n ^- a-S semiconductor layer that is a non-doped semiconductor layer.
The i layer 25 and the blocking layer 26 made of SiN are continuously deposited by plasma CVD, and the upper SiN film is processed into a predetermined shape as shown in FIG.

Next, as shown in FIG. 3C, an n-type semiconductor layer doped with impurities by plasma CVD is used.
⁺ A-Si ohmic layer 27 is deposited, etched by the ⁿ - a-Si layer 25 and the n ⁺ a-Si ohmic layer 27 is processed and formed into a predetermined shape, n source electrode side ⁺ a-
The Si ohmic layer 27a and the drain side n ⁺ a-Si ohmic layer 27b are separately formed. After that, the display electrode 28 is formed in a predetermined shape by sputtering and processing a transparent film made of ITO that partially overlaps the n ⁺ a-Si ohmic layer 27a on the source electrode side and extends.

Thereafter, as shown in FIG. 3D, an ohmic barrier layer 29 of Cr having a film thickness of 100 to 500 Å and a main signal wiring layer (second metal layer) 30 are formed by sputtering, vapor deposition or the like. As an Al layer having a film thickness of 1000 to 5000Å or an Al-based alloy containing at least one metal selected from Ti, Mo, W, Ta, and Cu, and a battery reaction prevention layer (a metal of the third layer). As the layer 31, Mo having a film thickness of 100 to 500 Å is continuously deposited.

Thus, the first layer 29 of the source electrode is formed.
a and the first layer 29b of the drain electrode, the second layer of the source electrode
The layer 30a and the second layer 30b of the drain electrode, and the third layer 31a of the source electrode and the third layer 31 of the drain electrode
b, first layer data wiring 29c, second layer data wiring 3
0c and the third layer data wiring 31c are obtained at the same time. Next, as shown in FIG. 3E, the metal film stacked in three layers is processed in a predetermined shape and under predetermined conditions to form a source electrode, a drain electrode, and a data wiring having a three-layer structure, respectively. It

At this time, the Mo film 31 which is the uppermost layer and the main signal wiring layer 30 which is the lower layer and which is made of Al or an Al-based alloy have the same phosphoric acid-based etching solution (phosphoric acid, nitric acid,
It can be etched with a mixture of acetic acid and water. The first ohmic barrier layer (Cr) 29, which is the lowermost layer, is processed by wet etching using an etchant solution of cerium-ammonium cerium acetate or dry etching using Cl ₂ gas.

Finally, the surface protection film 32 made of SiN film
Is formed into a predetermined shape by plasma CVD and processing, whereby a thin film transistor for a liquid crystal display device as shown in FIG. 1 is completed. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0029]

As described in detail above, according to the present invention, the following effects can be achieved. (1) Data wiring is ohmic barrier layer (Cr) 29
The first-layer data wiring 29c, which is a low-resistance material, the second-layer data wiring 30c, which is a main signal wiring layer (Al or Al-based alloy) 30, and a battery reaction prevention layer (Mo).
The third layer has a three-layer structure including the third-layer data wiring 31c, and similarly, the drain electrode and the source electrode of the plurality of thin film transistors are the first layer of the source electrode that is the ohmic barrier layer (Cr) 29 with the semiconductor layer. 29a, the first layer 29b of the drain electrode, and the main signal wiring layer (Al or Al
System alloy) 30, the second layer 30a of the source electrode, the second layer 30b of the drain electrode, and the battery reaction prevention layer (Mo) 31
The third layer 31a of the source electrode and the third layer of the drain electrode
By adopting the three-layer structure including the layer 31b, the etching rate of the lower layer which is the ohmic barrier layer (Cr) 29 and the etching rate of the main signal wiring layer (Al or Al-based alloy) 30 which is the upper layer are different, and the etching selection ratio is different. Therefore, when the upper main signal wiring layer (Al or Al-based alloy) 30 is etched, the lower ohmic barrier layer (Cr) 29 is not etched.

Further, since the ohmic barrier layer (Cr) 29 is not an alloy film, the reproducibility of the sputtered film quality is good, and stable etching rate control can be performed. Therefore, the overhang of the main signal wiring layer (Al or Al-based alloy) 30 caused by the side etching of the first layer does not occur. Therefore, problems such as peeling and turning of the main signal wiring layer (Al or Al-based alloy) 30 are caused, and
It is possible to prevent disconnection of the source and drain electrodes in a later process which causes these.

(2) The Mo film 31 and the Al film 30 can be collectively etched with the same etching solution, and the Mo film 31 is A
The etching rate is 4 to 6 times faster than that of the Al film 30.
The film 31 is tapered. This improves the step coverage of the SiN protective film in the subsequent process.

(3) A part of the display electrode 28 made of ITO is sandwiched between the lower n ⁺ a-Si ohmic layer 27 and the first layer 29a of the source electrode, which is the ohmic barrier layer (Cr) 29, and is sufficiently formed. The contact area can be obtained, and
The ohmic contact between Cr and n ⁺ a-Si in the ohmic barrier layer is good. Therefore, the ohmic contact between the display electrode and the data wiring becomes particularly good, and the reliability of connection can be improved. In that case, since the Mo film 31 as the battery reaction preventing layer is formed on the uppermost layer, the permeation of the developing solution during the developing process using the alkaline developing solution is prevented, and the battery reaction is less likely to occur. It is possible to eliminate the pattern defect of the display electrode.

(4) Further, since the source, drain, and data line electrodes can be formed collectively, the process can be simplified and another effect of cost reduction can be obtained.
As described above in detail, as a liquid crystal display device, neither line defects nor point defects occur, so that display quality can be improved and the process can be simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a thin film transistor for a liquid crystal display device showing an embodiment of the present invention.

FIG. 2 is a partial plan view of a liquid crystal display device showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing process of a thin film transistor for a liquid crystal display device showing an example of the present invention.

FIG. 4 is a cross-sectional view of a conventional thin film transistor for a liquid crystal display device.

FIG. 5 is a partial plan view of a conventional liquid crystal display device.

[Explanation of symbols]

21 Insulating Transparent Substrate 22 Gate Electrode 23 First Gate Insulating Film 24 SiN Film 25 n ^- a-Si Layer 26 Blocking Layer 27 n ⁺ a-Si Ohmic Layer 27a Source Electrode Side n ⁺ a-Si Ohmic Layer 27b Drain Electrode Side n ⁺ a-Si ohmic layer 28 display electrode (ITO) 29 ohmic barrier layer (Cr) 29a first layer of source electrode 29b first layer of drain electrode 29c first layer data wiring 30 main signal wiring layer (second Second metal layer: Al or A
1-based alloy) 30a Second layer of source electrode 30b Second layer of drain electrode 30c Second layer data wiring 31 Battery reaction prevention layer (third layer metal layer: Mo) 31a Third layer of source electrode 31b Drain electrode Third layer 31c Third layer data wiring 32 Surface protection film

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ichiro Ohno 2951-5 Ishikawacho, Hachioji City, Tokyo Casio Computer Co., Ltd. Hachioji Research Center

Claims (7)

[Claims] 1. A matrix is provided with a thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other. In a thin film transistor for a liquid crystal display device in which a plurality of gate electrodes of the thin film transistor are arranged, the address wiring is connected to the other of the source electrode and the drain electrode, the drain electrode, the source electrode and the data wiring are It has a three-layer structure of a first layer which is an ohmic barrier layer with a semiconductor layer, a second layer which is made of a low resistance material and which is a main signal wiring layer, and a third layer which is a battery reaction preventing layer. And a thin film transistor for a liquid crystal display device. 2. The thin film transistor for a liquid crystal display device according to claim 1, wherein the semiconductor layer is n ⁺ a-Si. 3. The thin film transistor for a liquid crystal display device according to claim 1, wherein the first layer is Cr. 4. The second layer comprises Al, Ti, M
The thin film transistor for a liquid crystal display device according to claim 1, wherein the thin film transistor is an Al-based alloy made of Al and at least one kind of metal selected from o, W, Cr, Ta, and Cu. 5. The thin film transistor for a liquid crystal display device according to claim 1, wherein the third layer is Mo. 6. A connection portion between the display electrode and the thin film transistor, in order from a lower layer forming a source electrode or a drain electrode of the thin film transistor, a display electrode / a first layer composed of a metal layer / a second layer composed of a metal layer / a metal layer. The thin film transistor for a liquid crystal display device according to claim 1, wherein the thin film transistor is formed of a third layer including: 7. A matrix of a thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other. In a method for manufacturing a thin film transistor for a liquid crystal display device, wherein the plurality of thin film transistors are arranged in a line, the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode, (a) on an insulating transparent substrate A gate electrode, an insulating film on the gate electrode, a non-doped semiconductor layer above the insulating film corresponding to the gate electrode, and an electrically separated layer on the non-doped semiconductor layer. , A semiconductor layer doped with impurities and a display electrode partially stacked on the semiconductor layer doped with impurities are sequentially formed And (b) a first layer that is an ohmic barrier layer, a second layer that is a main signal wiring layer made of a low resistance material, and a third layer that is a battery reaction prevention layer on top of that. A second step of sequentially laminating, and (c) a first layer composed of the ohmic barrier layer, a second layer which is a main signal wiring layer, and a battery reaction prevention layer by being processed in a predetermined shape and under predetermined conditions. A third step of forming a source electrode, a drain electrode, and a data wiring having a three-layer structure including a certain third layer, and (d) a fourth step of forming a surface protective film on the source electrode, the drain electrode, and the data wiring. The method for manufacturing a thin film transistor for a liquid crystal display device, comprising: