JPH06196451A - Dry etching method for amorphous silicon, and manufacture of thin film transistor using thereof - Google Patents

Abstract

PURPOSE:To decrease the defective products due to disconnection of wire of a TFT source and drain electrode and a drain bus line by a method wherein the gas, which is formed by mixing halogen gas, containing F and Cl atoms, and O2, is used for a dry etching process in which an amorphous silicon film is formed in island shape. CONSTITUTION:A Cr film is formed on a glass substrate 1, and a gate electrode 2 is formed. Then, a gate insulating SiN film 3, a semiconductor layer amorphous silicon (a-Si) film 4, and an ohmic contact layer n-type a-Si film 5 are formed successively. The a-Si film 4 is element-isolated by conducting dry etching in plasma of gas produced by mixing a single or plural halogen gases, containing F and Cl atoms. At that time, the a-Si film 4 is gently tapered. As a result, the disconnection of wire on the TFT source and drain electrode and a drain bus line and defective products due to high resistance can be reduced.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T hin- F il to be mounted on the switching element such as a liquid crystal display device
m T ransistor, hereinafter referred to as TFT) semiconductor active layer using amorphous silicon (A morphous Si licon, following a-S
i)).

[0002]

2. Description of the Related Art Since a-Si can be formed at a relatively low temperature, it can be formed on an inexpensive glass substrate and is used as a semiconductor layer of a semiconductor device such as a TFT used in a liquid crystal display device or the like. ing.

Hereinafter, a TFT using a-Si (hereinafter referred to as a
-Si.TFT) will be described below.

FIG. 2 is a sectional view of a general a-Si TFT. 1 denotes an insulating substrate such as a glass substrate, 2 denotes a gate electrode (for example, Cr film), 3 (referred for example, a silicon nitride film, Si licon N itride, less SiN film) is a gate insulating layer,
4 is a semiconductor layer (a-Si film), 5 is a phosphorus-doped n-type a-Si film for obtaining ohmic contact between the semiconductor layer and the upper metal electrode (Al), and 6 is a source electrode (for example, Al film). , 7 are drain electrodes (for example, Al film),
8 display pixel electrodes (e.g., indium and tin oxide film, I n
shown dium T in O xide, the following referred to as ITO film), respectively.

The gate insulating layer SiN film 3, semiconductor layer a-Si film 4, ohmic contact layer n-type a- shown in FIG.
Si film 5, a plasma CVD (C hemical V apor D eposit
ion) method for continuous film formation, and a- on the SiN film 3 is formed by an ordinary photolithography process and dry etching process.
The Si film 4 and the n-type a-Si film 5 are separated into islands. The dry etching process at this time is described in JP-A-1
There is known a method of using a mixed gas of SF ₆ and CCl ₄ as an etching gas as shown in No. 32627.

[0006]

The above-mentioned prior art S
In the dry etching using the mixed gas of F ₆ and CCl ₄ , the semiconductor layer a-Si film 4 (including the n-type a-Si film 5)
Is a processed cross section when a is formed in an island shape.
The taper angle of the -Si film becomes as steep as 75 to 85 degrees, and thereafter, the source / drain electrodes 6 and 7 that overcome the step of the semiconductor layer a-Si film 4 formed in an island shape and the TFT
TF arrayed on a plane and used for a large screen display device
When the T matrix substrate is manufactured, the coverage of the drain bus line (not shown here) connecting the drain electrodes 7 to the step of the a-Si film 4 becomes insufficient,
There has been a problem that the yield of the TFT matrix substrate decreases due to disconnection and increase in resistance.

An object of the present invention is to make the etching cross-sectional shape of the amorphous silicon film to be dry-etched gentle in order to improve the coverage of the wiring material formed by sputtering or the like on the amorphous silicon island. , T
It is an object of the present invention to provide a dry etching method for amorphous silicon which does not cause defects due to disconnection of the source / drain electrodes and drain bus lines of FT and increase in resistance.

[0008]

In order to achieve the above object, the present invention provides a dry etching step of forming an a-Si film 4 (including an n-type a-Si film 5) of a TFT in an island shape. F, is obtained by dry-etched using single or multiple halogen gas and O ₂ mixed gas, in particular to the O ₂ amount in the range of 2 to 20 volume% gas containing Cl atom.

[0009]

In general, when the a-Si film 4 is etched by a dry etching method using plasma, a halogen-based gas containing F and Cl is used as an etching gas. In this case, the F radical is a reactive species (Si + 4F → SiF ₄ ↑) having a property that the etching form is isotropic, and Cl is a cation and a reactive species having a property of easily causing anisotropy.
It works as (Si + 4Cl → SiCl ₄ ↑).

When O ₂ is added to the halogen-based gas, F radicals, which are isotropic reactive species, increase. Further, the resist used as a mask for patterning the a-Si film 4 into a desired shape and size is ashed.

FIG. 3 shows the state of receding of the resist 20 which is ashed by adding O ₂ and the etching of the a-Si film 4. The etching of the a-Si film 4 and the receding of the resist 20 are simultaneously performed, and the taper angle of the a-Si film 4 is set to 30 to 6.
It can be processed into a gentle slope of about 0 degree.

Here, the amount of O ₂ added is important. Figure 4
Shows the relationship between the amount of O ₂ added to a single halogen gas or a plurality of halogen gases and the taper angle of the a-Si film. In FIG. 4, θ ₁ is a−
The taper angle of the portion in contact with Si and the base film SiN, θ ₂ is a
The taper angle of the tangent line of the contact portion between the -Si uppermost layer, a-Si, and the resist is shown. As a result, the amount of O ₂ added is preferably in the range of 2 to 20% by volume with respect to the halogen gas.

If the amount of O ₂ added is less than 2% by volume, the effect of increasing F radicals, which are isotropic reaction species, and the effect of resist receding are small, and the taper angle of the a-Si film 4 becomes larger than 60 degrees. However, it cannot be processed into a gentle slope.

If the amount of O ₂ added exceeds 20% by volume, an undercut as shown in FIG.
-A defect occurs due to disconnection of the source / drain electrodes of the TFT and drain bus line that cross over the Si film 4 and an increase in resistance.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view schematically showing a main part of a parallel plate type reactive ion etching apparatus for etching with a mixed gas of a single or plural halogen gas containing F and Cl atoms and O _{2 according to} the present invention. Is.

In FIG. 1, 10 is an etching chamber and 11 is an etching chamber.
Is an anode electrode, 12 is a cathode electrode serving as a substrate stage, 13 is an etching gas introduction pipe, 14 is a gas exhaust port, and 15 is a high frequency power supply (13.56 MHz). The etching gas is introduced into the etching chamber from a gas supply system installed outside the etching chamber 10 through a flow rate controller. Further, the cathode electrode 12 has a structure that is water-cooled to prevent the temperature of the sample from rising.

The mixed gas used in this embodiment is SF ₆ : 2.
5 sccm, CClF ₃ : 25 sccm, O ₂ : 5 sccm, gas pressure: 30 Pa, power density: 0.5 W / cm ² . The substrate 16 (TFT matrix substrate) was placed on the cathode electrode 12 and the etching was carried out in a high frequency plasma of a mixed gas. In FIG. 6, a- in the case of etching under the above conditions
The processed cross section of a Si film is shown. The taper angle of the a-Si film at this time was 40 degrees.

Using the dry etching method of the present invention,
An a-Si.TFT matrix substrate having a large number of a-Si.TFTs having the structure shown in FIG. 2 arranged on a plane and used for a large-screen display device was manufactured by the following procedure.

(1) A Cr film is formed on a glass substrate 1 by a sputtering method, and a gate electrode 2 is formed by an ordinary photolithography process and etching with an aqueous solution of ceric ammonium nitrate.

(2) The gate insulating layer SiN film 3, the semiconductor layer a-Si film 4, and the ohmic contact layer n-type a-Si film 5 are continuously formed by the plasma CVD method. The a-Si film 4 (including the n-type a-Si film 5) is separated into islands by a dry etching method.

(3) SiN on the gate wiring terminal portion (not shown here) for connecting to an external driver
The film 3 is removed by a normal photolithography process and dry etching using SF ₆ .

(4) An ITO film is formed by a sputtering method, and a display pixel electrode 8 is formed by a normal photolithography process and etching with a mixed solution of hydrochloric acid, nitric acid and water.

(5) An Al film is formed by a sputtering method, and the source electrode 6 is formed by a normal photolithography process and etching with a mixed solution of phosphoric acid / acetic acid / nitric acid / water.
The drain electrode 7 is formed.

[0024] (6) a source electrode 6, an n-type a-Si film on the TFT channel and the drain electrode 7 as a mask is removed by dry etching using CClF _3.

By manufacturing the a-Si / TFT matrix substrate in this manner, in the present embodiment, the a-Si film 4 is processed into a gentle taper shape in the a-Si element isolation step (2). (FIG. 7 shows an a-Si film 40).

Therefore, it is possible to reduce the defects due to the disconnection of the source / drain electrodes and the drain bus line which cross the a-Si film 4 and the increase in the resistance.
It was possible to improve the yield of the matrix substrate.

[0027]

According to the present invention, in dry etching of an a-Si film when manufacturing an a-Si / TFT matrix substrate, the a-Si film can be processed with a taper angle in the range of 30 to 60 degrees. The defects due to the disconnection of the source / drain electrodes and the drain bus line of the TFT and the increase in the resistance, which are generated because the processed cross section of the -Si film is steep, can be reduced. TFT
This has the effect of improving the yield of the matrix substrate.

[Brief description of drawings]

FIG. 1 is a schematic explanatory view of an apparatus used in a dry etching method of the present invention.

FIG. 2 is a sectional view of an a-Si TFT.

FIG. 3 is a diagram showing an effect of resist receding when an a-Si film is etched using a resist as a mask.

FIG. 4 is a diagram showing the relationship between the amount of O ₂ added to a halogen gas and the taper angle of an a-Si film.

FIG. 5 is a processed cross-sectional view of a-Si in which an undercut occurs when the amount of added O ₂ exceeds 20% by volume.

FIG. 6 is a cross-sectional view of a-Si processed by using the dry etching method of the present invention.

FIG. 7 is a cross-sectional view of an a-Si TFT manufactured by using the dry etching method of the present invention.

[Explanation of symbols]

3 ... Gate insulating layer SiN film, 4 ... Semiconductor layer a-Si film,
5 ... Ohmic contact layer n-type a-Si film, 6 ... Source electrode, 7 ... Drain electrode, 10 ... Etching chamber, 11
... Anode electrode, 12 ... Cathode electrode, 16 ... Substrate (a
-Si / TFT matrix substrate), 20 ... Resist, 4
0 ... Semiconductor layer a-Si film processed into a tapered shape.

Claims (3)

[Claims] 1. Drying of an amorphous silicon film, characterized by dry-etching the amorphous silicon film in plasma of a gas in which a single or plural halogen gas containing F, Cl atoms and O ₂ are mixed. Etching method. 2. The amorphous silicon film according to claim 1, wherein O ₂ is added to the single or plural halogen gas containing F and Cl atoms in the range of 2 to 20% by volume of the halogen gas. A dry etching method for amorphous silicon, characterized in that an etched cross section is processed into an inclined shape having a taper angle in the range of 30 to 60 degrees. 3. A thin film transistor having a structure in which a gate electrode, a gate insulating layer, a semiconductor layer, and a source / drain electrode are sequentially laminated on an insulating substrate, wherein a semiconductor layer amorphous silicon film on a gate insulating layer silicon nitride film. 3. The method of manufacturing a thin film transistor, wherein the dry etching method according to claim 1 or 2 is used for the etching of.