JPH0619588A - Power source controller for information processor - Google Patents

Abstract

PURPOSE:To prevent data in a disk device from being destroyed even when a power source switch is unwillingly turned off during the data access of the disk device. CONSTITUTION:A data read/write command to a disk controller 14 is decoded, the AND output of a write signal outputted with the command and the decode signal is latched, and a disable signal is prepared. Then, a power source-off request based on the operation of a power source switch 6 can be prevented from being transmitted to a main power source circuit 3 by the disable signal, so that a power supply state can be maintained. The disable signal is stopped by a disk access end signal, the power source-off request is transmitted to the main power source circuit 3, and the power supply is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a personal computer equipped with a hard disk device or a flexible disk device, and more particularly to a power supply control device in the device.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication (Kokai) No. 3-10309 discloses that when a power switch is turned off, it is determined whether or not a hard disk device is in operation. There is disclosed a technical idea for preventing data destruction in the inside. However, the specific method is not described.

Further, in Japanese Patent Laid-Open No. 3-95609,
An interrupt (NMI) is generated when the power switch is turned off, and an interrupt routine in the BIOS performs a soft process to wait for the power supply to be cut off when the disk is being accessed and destroys the disk data. A system for preventing this is disclosed.

On the other hand, in Japanese Patent Laid-Open No. 3-73465,
If the power switch is turned off while the hard disk is being accessed, a movement end signal is output when the head has finished moving to the non-data area to prevent the head from remaining in contact with the media in the data area. Disclosed is a control device that configures a hard disk device and delays power-off until a movement end signal is output from the hard disk device after operating a power switch.

[0005]

In the conventional software processing using interrupts, there is a possibility that the interrupt routine may be rewritten depending on the program to be used and may not operate. Further, depending on the OS or the like, the interrupt routine may be interrupted. In some cases, the conventional method cannot be adopted.

Further, since a normal hard disk or flexible disk device is not configured to output a head movement end signal as disclosed in Japanese Patent Laid-Open No. 3-73465, the above method using this signal is generally used. It was not applicable.

Therefore, according to the present invention, in a device using a normal hard disk or a flexible disk device, regardless of the installed software, even if the power switch is turned off while the disk is being accessed, the disk data is surely destroyed. The purpose is to be able to prevent.

[0008]

In order to solve the above problems, the present invention controls a data access to a disk device in an information processing device having a disk device according to an input data read / write command. In addition, a disk controller that outputs a disk access end signal after data access, a detection circuit that detects that the data read / write command is sent to the disk controller and outputs a detection signal, a power supply circuit, and a power supply A switch and, after the detection signal is output, prevents the power supply from the power supply circuit from being shut off based on an off operation of the power supply switch, and releases the blocking state in response to the disk access end signal. And a control circuit for shutting off the power based on the turning off of the power switch is provided. Than it is.

Further, according to the present invention, in response to the disk access end signal output immediately after the power switch is turned off, a first prohibition circuit for prohibiting the writing of the data read / write command to the disk controller. Is provided.

Further, according to the present invention, in response to the turning-off operation of the power switch, the writing of the data read / write command to the disk controller is prohibited.
The prohibition circuit is provided.

[0011]

According to the present invention, when a data read / write command is sent to the disk controller, access to the disk is started, and this command is detected by the detection circuit. Thereafter, the power is turned on when the power switch is turned off. Is blocked. Then, when the disk access end signal is output from the disk controller,
The blocking state is released, and the power is shut off based on the operation of turning off the power switch.

Further, the first or second prohibition circuit reliably prohibits writing of a new data read / write command to the disk controller after the power switch is turned off.

[0013]

1 is a block diagram showing the configuration of a personal computer as an embodiment of the present invention, 1 being an AC
Adapter 2 is a battery, 3 is connected to AC adapter 1 and battery 2 via diodes 4 and 5, and converts the input power supply voltage VI to a predetermined power supply voltage VO.
A main power supply circuit configured to include a C / DC converter and supplying a power supply voltage VO to each part of the device described later, 6 is a power switch for manual operation for instructing on and off of power, and 7 is a power switch Switch signal S according to the operation of
It is a power switch monitoring circuit that outputs W.

Reference numeral 8 is a CPU which sends out addresses and data via the buses 9 and 10 and outputs read signals RD and write signals WR via lines 11 and 12, and 13 is a hard disk device or a flexible disk device.
14 is connected to the buses 9 and 10 and the line 11, and
It is a disk controller which receives the chip select signal CS0 and the write signal BWR and controls the data read / write operation with respect to the connected disk device 13.

The disk controller 14 is a general disk controller, and exchanges with the CPU 1 in the conventional manner.

That is, a predetermined I / O address is assigned to the disk controller 14 and the disk 1
When accessing 3, the I / O address is assigned to the CPU 8
Is output to the address bus 9. Also, the disk 13
When reading or writing the data, the CPU 1 first sends a read or write command to the data bus 10 and outputs a write signal WR to the line 11.
A command is written to the disk controller 14, then parameters representing cylinders, heads, sectors, etc. are sent to the data bus 5, and a write signal WR is output to the line 11 to write the parameters to the disk controller 14. I'm trying to do. Then, when the data read or write of the disk 13 is completed, the disk controller 14 outputs the interrupt signal IRQ as a disk access end signal. As commands for the disk controller, various commands such as a data read / write command and a seek command are prepared.

Next, in FIG. 1, numeral 15 decodes the I / O address assigned to the disk controller 14 to generate a chip select signal CS0, and further decodes this I / O address and data read / write command. A chip select signal CS1 and a chip select signal CS1 and a write signal WR.
To read data to the disk controller 14 /
An AND gate that outputs a signal DACW when a write command is written, 17 inputs the output signal DACW of the AND gate 16 to the clock terminal CL, inputs the power supply voltage V0 to the D input terminal, and inputs the power supply voltage V0 to the clear terminal CLR from the disk controller 14. D flip-flop for inputting the disk access end signal IRQ of 1 through the OR gate 18 and outputting the switch disable signal SWDIS,
Reference numeral 9 denotes an inverted signal of the switch disable signal SWDIS at one end and a switch signal SW from the power switch monitor circuit 7 at the other end, and controls passage of the switch signal SW by the signal SWDIS to supply the power as an output. It is an AND gate that sends the off signal PWROFF to the main power supply circuit 3. The backup auxiliary power supply voltage VBACK is supplied to the AND gate 19, the power switch monitoring circuit 7, and the pull-up resistor 20.

Reference numeral 22 denotes a chip select signal CS at one end.
An AND gate 23 which inputs 1 and inputs the signal DIS from the OR gate 21 to the other end and outputs a write disable signal WRDIS for blocking the write signal WR.
Is an AND gate that controls the passage of the write signal WR by the write disable signal WRDIS and inputs the output signal BWR to the write signal input terminal of the disk controller 14, 24 is the switch signal SW is input to the D terminal, and the disk access end signal D flip-flop 25 inputs IRQ to the clock terminal CL and sends the output signal DIS2 to the OR gate 21, 25 inputs the output signal DACW from the AND gate 16 to the D terminal, and inputs the switch signal SW to the clock terminal CL. , A D flip-flop that outputs the output signal DIS1 to the OR gate 21. To the D flip-flops 17, 24, 25, a reset signal RST generated when the power is turned on and the reset key is operated is input to each clear terminal CLR.

The operation of this embodiment will be described below with reference to the timing chart of FIG.

When the power switch 6 is on, the switch signal SW is at L level, so the power off signal PWROFF from the AND gate 19 also maintains L level. Therefore, the main power supply circuit 3 outputs the main power supply voltage V0. It is supplied to each part of the device such as the CPU 8, the disk device 13, the disk controller 14 and the like.

When the power supply voltage V0 is supplied, the CPU
For accessing disk data, the I / O address, the data read command or the data write command, and the write signal W are provided to the buses 9 and 10 and the line 12, respectively.
When R is output, the decoder 15 generates L level chip select signals CS0 and CS1 as shown in FIGS. 2a and 2b, and the output signal DACW of the AND gate 16 is at L level for the same period as the write signal WR (see FIG. 2e). Since the D terminal of the D flip-flop 17 is connected to the H level, its output switch disable signal SWDIS changes to the H level in accordance with the fall of the signal DACW to the L level.

Therefore, even if the switch signal SW changes to the H level as shown in FIG. 2g by turning off the power switch 13, the AND gate 19 prevents the switch signal SW from passing, and the power off signal PWROFF becomes Figure 2l
It keeps the L level as shown.

The disk controller 14 is the CPU
The data of the disk device 13 is accessed in response to the writing of the data read command or the data write command from the D flip-flop 17 when the disk access end signal IRQ indicating the end of this access is output (FIG. 2f). Is cleared and the switch disable signal SWDIS changes from H level to L level as shown in FIG. 2h. As a result, the H level switch signal SW instructing to turn off the power source passes through the AND gate 19, and the power source off signal PWROFF becomes the H level as shown in FIG. Therefore, the main power supply circuit 3 comes to stop the supply of the power supply voltage V0.

That is, even if the power switch 6 is turned off during the data read or write of the disk 13, the supply of the power supply voltage V0 is maintained and the power supply is cut off after the disk access is completed.

Further, in this embodiment, the data read / write command is prevented from being written in the disk controller 14 after the power switch is turned off as follows.

That is, the output signal DAC of the AND gate 16
W becomes L level only when a data read / write command from the CPU 8 is written to the disk controller 14. Therefore, when the power switch 6 is turned off during the other H level period, the output signal DIS1 of the D flip-flop 25 becomes H level (see FIG. 2).
i), the output signal DIS of the OR gate 21 also becomes H level. Therefore, in the AND gate 22, when the decoder 15 outputs the chip select signal CS1 of L level, the write disable signal WRDIS becomes H level, and the write signal WR output simultaneously with CS1 is A
The passage will be blocked by the ND gate 23. Therefore, the data read / write command is not written in the disk controller 14.

However, in the AND gate 22, when the chip select signal CS1 is not output, the write disable signal WRDIS is fixed to the L level, so that the parameters subsequent to the data read / write command and other commands are written. Write signal WR for
Are not blocked by AND gate 23. For example, the timing T1 in FIG. 2 indicates a data read / write command, and T2 indicates the subsequent parameter writing. Incidentally, the timing T0 is an example of writing a seek command without writing parameters, and in this case, the chip select signal CS1 is not output.

By the way, the output signal D of the AND gate 16
Power switch 6 while ACW is at L level
Is turned off, the D flip-flop 25 cannot block the write signal WR because the output signal DIS does not become H level.

However, in this embodiment, when the disk access end signal IRQ is sent from the disk controller 14 after the power switch 6 is turned off, the output signal DIS2 of the D flip-flop 24 is changed as shown in FIG. 2j. Since it becomes H level, the AND gates 22 and 23 prevent the write signal WR output together with CS1 from passing through, as in the case where the signal DIS1 becomes H level. Therefore, as shown at timing t3 in FIG. 2, the data read / write command output from the CPU is not written to the disk controller 14 after the disk access that is being performed when the power switch 6 is turned off is completed. .

The D flip-flop 25 is not necessarily provided if the disk controller 14 does not take in the next data read / write command until the disk access end signal IRQ is output.

[0031]

As described above, according to the present invention, it is possible to ensure that the power switch is inadvertently turned off during the data access of the disk device without using a special disk device and regardless of the installed software. It is possible to prevent data destruction in the disk device.

Since a new data read / write command is prevented from being written to the disk controller after the power switch is turned off, more reliable data destruction prevention can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a diagram showing a timing chart of each signal in the example.

[Explanation of symbols]

 3 Main Power Circuit 6 Power Switch 7 Power Switch Monitoring Circuit 8 CPU 13 Disk Device 14 Disk Controller 15 Decoder 16, 19, 22, 23 AND Gate 17, 24, 25 D Flip-Flop 18, 21 OR Gate

Claims (3)

[Claims] 1. An information processing apparatus comprising a disk device, which controls data access to the disk device according to an input data read / write command and outputs a disk access end signal after the data access. , A detection circuit that detects that the data read / write command is sent to the disk controller and outputs a detection signal, a power supply circuit, a power switch, and, after the detection signal is output, Control for preventing the power from the power supply circuit from being shut off based on the off operation, releasing the blocked state in response to the disk access end signal, and shutting off the power based on the off operation of the power switch A power supply control device for an information processing device, comprising: a circuit. 2. A first prohibition circuit for prohibiting the writing of the data read / write command to the disk controller in response to the disk access end signal output immediately after the power switch is turned off. The power supply control device of the information processing apparatus according to claim 1. 3. The data read / write to the disk controller in response to an off operation of the power switch.
The power supply control device for an information processing apparatus according to claim 1, further comprising a second prohibition circuit that prohibits writing of a write command.