JPH0618230B2 - Memory IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a memory IC test apparatus.

[Conventional technology]

In order to improve the yield in the manufacturing process of the memory IC, it is necessary to investigate the content of the defect and the cause of the defect.
In the wafer process step, it is necessary to examine the defect mode of each defective chip on the wafer, the cause of the defect, the in-wafer distribution of the defective chip, and the like. Conventionally, the above-described failure analysis was performed using a test apparatus as shown in FIG. In FIG. 5, 1 is a function test circuit for performing a function test of a memory device to be measured which will be described later, 2 is a memory device to be measured (here, each chip on the wafer), and 3 is each chip on the wafer, which is automatic one by one. A wafer prober 4 serving as a wafer probing device having a function of moving the optical axis is a CRT indicating the position of a defective bit.

When there is a defective memory cell that does not always perform a function, the screen on the CRT is brightly displayed in the same positional relationship as the actual position where this memory cell is arranged in the chip. What is displayed is called a fail bitmap. As described above, according to the conventional device, it is possible to easily find the position of the defective cell in the chip from the CRT display, and it is possible to easily find the defective mode when there is a characteristic defect. It has been used as a very effective means for failure analysis of memory ICs.

[Problems to be solved by the invention]

However, in the conventional device, it is necessary for a human to read the CRT display one by one, and therefore it takes a lot of time to investigate the defective mode for all the chips in one wafer. Moreover, since the rough pattern of defective bits is manually recorded by hand, there is a defect that the accuracy is lacking.

The present invention has been made in view of the above circumstances, and an object of the present invention is to automatically test all chips in one wafer and to roughly determine one defective bit in all chips or To obtain a memory IC test device capable of displaying on two print sheets.

[Means for solving problems]

In order to achieve such an object, the present invention provides a wafer probing device that outputs relative position information on a wafer of a memory device under test having a plurality of memory cells, and a function test of each memory cell in the memory device under test. A function test circuit to perform, a fail bit memory that stores position information of a defective memory cell in the memory device under test detected by the function test circuit, and a defective memory in the memory device under test stored in the fail bit memory It receives the cell position information and the relative position information from the wafer probing device, and based on the position information of the defective memory cell, the compressed position information of the defective memory cell in the array smaller than the cell array of the memory cell of the memory device under test is obtained. Generate this compressed position information and relative position information Memory tester having an information processing means for outputting the combined viewed as file data, and further comprising a printing device for printing based on the file data from the information processing device in this memory tester on the print paper.

[Action]

In the present invention, the test of each chip is performed automatically.

〔Example〕

A first embodiment of a memory IC test apparatus according to the present invention
Shown in the figure. In FIG. 1, 2 is a memory element to be measured, 5
Is a memory tester, 6 is a wafer prober as a wafer probing device which can automatically move the memory element 2 to be measured on the wafer and recognize the relative position of the element 2.
Is a dot printer as a printing device for displaying defective bits at a predetermined position on a print sheet.

The memory tester 5 combines an external storage device by combining a function test circuit 51 for performing a function test of the memory device under test 2, a storage information of a fail bit memory, which will be described later, and relative position information on the wafer of the memory device under test 2 (see FIG. CPU 52 as information processing means for storing the file data in a file (not shown), outputting the file data on a print sheet, and controlling the function test circuit 51.
And a fail bit memory 53 for storing the defective bit address of the memory device under test 2 detected by the function test circuit 51. The fail bit memory 53 is a memory that can store the defective bit address of the memory device under test 2 in real time during execution of the function test.

FIG. 2 is a flowchart showing a data processing procedure in this apparatus, and FIG. 3 is a data structure diagram showing a data structure in the data processing process.

Next, the operation of this device will be described with reference to FIGS. First, in step 10 in FIG. 2, the chip is moved to a predetermined position, and in step 11, a test is performed. The function test circuit 51 checks whether all the memory cells of the memory device under test 2 are operating normally. The fail bit memory 53 is composed of a storage circuit having a storage capacity equal to or larger than the storage capacity of the memory device under test 2, and if the memory device under test 2 has a defective bit, data "1" is stored at the same address position.
Is to be written.

FIG. 3 shows how the data “1” is written. In FIG. 3, 20 is the memory cell array of the memory device under test 2 in which memory cells are arranged in a matrix, 30 is the contents of the fail bit memory 53, 40 is the structure of the data file stored in the external storage device, and 50a and 50b. Indicates the display of the dot printer 7.

If the memory cell indicated by the "x" mark in the memory cell array 20 is defective, the fail bit memory 53 has the same content as the memory cell array 20 of the memory device under test 2 as shown in the content 30 thereof. Data "1" is written in the memory cell at the position, and the fail information of the memory cell element 2 under test can be stored. Since data is written in the fail bit memory 53 each time a test is performed, after the test is completed, steps 12 and 1 in FIG.
As shown in FIG. 3, this fail information is read, combined with the chip position information, and stored as a file in the external storage device. The information of each chip is stored as a file in the order of the test, and after the test of all chips is completed, the file data is read and printed on a print paper in a predetermined format.

In the file data structure, as shown in the file structure 40, data indicating the chip position (this data is output from the wafer prober 6) is placed at the head address, and file information is placed after that. Since the fail bitmap of one chip is displayed on the print paper as it is, it is impossible to display all the chips of one wafer on one print paper. Therefore, a means called data compression is used here. For example, in the case of a memory element having a memory capacity of 64 kbits, an area of at least 256 × 256 dots is required to display all the bits, and one print sheet can display only a few pixels at most. Although various data compression methods can be considered, the method shown in FIG. 3 was adopted here.

Next, a method of compressing the above data will be described. As shown in the content 30 of the fail bit memory 53, the fail bit memory 53 is divided into several blocks, and a memory reduced to 1 / n ² in which one block is 1 bit is created. Here, n is a unit of division, which is 4 in this example.
When reading the fail bit memory 53, it is checked whether or not there is a defect, that is, data "1" in this block. In order to save the storage capacity of the file data stored in the external storage device, one bit in one word (word) corresponds to one bit in the memory (one block when data reduction is performed) It is stored in the storage device as a file (see step 13 in FIG. 2). After the test of all the chips is completed, the file data of the external storage device is read as shown in step 14 of FIG. 2, and the bitmap of the reduced memory is sequentially displayed at the predetermined chip positions as shown in step 15. To do. In this example,
As shown in the displays 50a and 50b of the dot printer 7,
A defective bitmap having the same pattern as the actual bitmap of the memory cell array 20 can be obtained. In this example, the block of 4 × 4 is divided as one unit, but it can be reduced to any size according to the memory capacity of the memory element under test 2 and the number of chips in one wafer. Further, here, if at least one defect is present in each block, this block is displayed as a defect. However, the number of bits can be two or more, and the number of bits can be changed depending on the block. is there.

FIG. 4 is a defective bit map showing an actual display example in this device. In the case of FIG. 4, some modifications other than those described above are carried out: "O" for non-defective products, "X" for all-bit defective products, and "IF" for input / output disconnection defects.
Is displayed. The defective chip with margin is also modified so that the defective category number is displayed in a circle.

〔The invention's effect〕

As described above, according to the present invention, the relative position of the memory device under test on the wafer is recognized, the function of the memory device under test is controlled by controlling the function test circuit by the information processing means, and the detected device under test is detected. The defective bit address of the memory element is stored in the fail bit memory, the storage information of the fail bit memory and the relative position information on the wafer of the memory element under measurement are combined and stored as a file in the external storage device, and the file data is printed on the print paper. By outputting to, the defective bitmaps of all the chips on the wafer are displayed on the print paper, so that it is possible to obtain accurate data in a short time.

[Brief description of drawings]

1 is a system diagram showing an embodiment of a memory IC test apparatus according to the present invention, FIG. 2 is a flow chart for explaining the operation of the apparatus of FIG. 1, and FIG. 3 is data in the apparatus of FIG. FIG. 4 is a data structure diagram showing the structure, FIG. 4 is a defective bit map in the apparatus of FIG. 1, and FIG. 5 is a conventional memory I.
It is a system diagram which shows a C test device. 2 ... Memory element to be measured, 5 ... Memory tester, 6 ...
Wafer prober, 7 ... Dot printer, 51 ... Function test circuit, 52 ... CPU, fail bit memory.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/10 491 8728-4M

Claims (2)

[Claims] 1. A wafer probing device for outputting relative position information on a wafer of a memory device under test having a plurality of memory cells, a function test circuit for performing a function test of the memory cell in the memory device under test, and this function. A fail bit memory for storing position information of a defective memory cell in the memory device under test detected by a test circuit, and position information of a defective memory cell in the memory device under test stored in the fail bit memory, and Receiving the relative position information from the wafer probing device, and generating the compressed position information of the defective memory cells in an array smaller than the cell array of the memory cells of the memory device under test based on the position information of the defective memory cells, This compressed position information and the relative position information are combined. A memory IC tester comprising: a memory tester having an information processing means for combining and outputting as file data; and a printing device for printing on print paper based on file data from the information processing means in the memory tester. 2. The information processing means stores file data for a plurality of measured memory elements on the same wafer in a storage means, and the printing device stores files for the plurality of measured memory elements stored in the storage means. According to an arrangement of the measured memory elements of the wafer based on the data, the defective memory cells are printed in accordance with the arrangement of the defective memory cells of the corresponding measured memory elements. A memory IC test device according to claim 1.