JPH06180988A - Detection amplifier - Google Patents

Abstract

PURPOSE:To give access to memory transistors at high speed and increase detection accuracy by providing a first transistor(TR) having a small ON- resistance, a second transistor to be controlled by negative feedback and a third transistor forming current mirror construction with the first transistor. CONSTITUTION:A PMOSTR 3 having a small ON-resistance is connected between the first positive power supply of a detection amplifier 1 and a semiconductor memory 600, and a negative-feedback controlled NMOSTR 4 is connected in series to the PMOSTR 3 through an inverter S. Then, a PMOSTR 9 is connected in series to a second positive power supply 8 to form current mirror construction with the PMOSTR 3. Thereby, a detection current proportional to a current which flows through the PMOSTR 3 flows through the PMOSTR 9, and the junction part between the PMOSTR 3 and the PMOSTR 9 makes no direct connection with the output signal of a detection amplifier and also since the ON-resistance of the PMOSTR 3 and the PMOSTR 9 is small, a potential at the input of the detection amplifier become a fixed value in a short time, so as to be able to give access at high speed and at the same time increase detection accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier included in a reading section for reading data from a data storage section provided in an integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 16, in an integrated circuit in which a logic circuit section and a memory circuit section 50 are provided in the same chip, the memory circuit section 50 is arranged from a memory array section 51 as shown in FIG. An input unit supplied with address data designating a memory transistor for reading stored data, a decoder unit for creating X and Y direction data for specifying a memory transistor based on the address data, and stored data read from the memory array unit. Selection unit 52 for selecting based on the output signal of the decoder unit, and the selection unit 52
Sense amplifier 5 for detecting the potential of data sent from
3 and an output section 54 for sending the data sent by the sense amplifier 53 to the outside of the memory circuit. The circuit of the memory array 51 has a well-known configuration as shown in FIG. 19, and the circuit of the selection unit 52 has a well-known configuration as shown in FIG. Further, the memory array section 51 and the selection section 52 are referred to as semiconductor memory means 600.

The sensing amplifier 53 is conventionally constructed as shown in FIG. 18, the same components as those shown in FIG. 17 are designated by the same reference numerals. The input side of the sense amplifier 53 to which the selection section 52 is connected is connected to the source side of N-channel MOS (hereinafter referred to as NMOS) transistors 63 and 64 and the inverter 61.
Is connected to the input side of the inverter 61 and the output side of the inverter 61 is connected to the NMO.
It is connected to the gates of S transistors 63 and 64. N
The drain side of the MOS transistor 63 is connected in series to the drain side of a P-channel MOS (hereinafter referred to as PMOS) transistor 65 whose gate is supplied with a signal φp described later and whose source side is connected to a positive power source. Also, NMOS
On the drain side of the transistor 64, the gate is grounded, and the source side is connected to the positive power supply.
The drain side of 6 is connected in series.

Further, between the output side of the inverter 61 and the input side of the detection amplifier 53, an NMOS transistor 67 is provided for direct negative feedback of the inverter 61 for the purpose of removing positive noise applied to the detection amplifier 53. And 68 are connected in series. The gate of the NMOS transistor 67 is connected to the connection point between the PMOS transistor 66 and the NMOS transistor 64, and the signal of φp is supplied to the gate of the NMOS transistor 68.
The connection point between the PMOS transistor 66 and the NMOS transistor 64 is connected to the input side of the output section 54 via the inverter 69.

[0005]

The operation of the sense amplifier configured as described above will be described below. Selector 5
The data sent from 2 is first supplied to the inverter 61, the signal level is inverted, and the NMOS transistor 64
Is supplied to the gate of the NMOS transistor 6
4 on / off control is performed. That is, the inverter 61 acts so as to maintain the input side potential of the sense amplifier 53 near the inversion potential level of the inverter 61. For example, when the selected memory transistor in the memory array section 51 has a high resistance or is in an off state, the sense amplifier 53
Since the input side potential is higher than the inversion potential, the level of the signal supplied to the gate of the NMOS transistor 64 is changed by the action of the inverter 61, and the NMOS transistor 64 is turned off. Therefore, the sense amplifier 5
Since the input side of the inverter 69 provided in the output section of 3 is connected to the positive power supply via the PMOS transistor 66 which is always on, the input side of the inverter 69 is high.
(H) level, and the output side of the detection amplifier 53 changes to low (L) level by the action of the inverter 69.

On the contrary, when the memory transistor has a low resistance or is in the ON state, the NMOS transistor 64 is kept in the ON state by the action of the inverter 61,
The input side of the inverter 69 is connected to the PMOS transistor 66.
Indicates a relatively low level potential determined by the current flowing through the memory transistor and the on-current of the memory transistor. in this case,
The input side of the sense amplifier 53 has a PMOS transistor 66.
Depending on the on-resistance value of, the above potential may not be maintained and may be lower than the inversion potential of the inverter 61. After such a state, when the next selected memory transistor has a high resistance or is in an off state, the sense amplifier 53 is restored until the input side potential of the sense amplifier 53 is restored.
Does not work properly. That is, the NMOS transistor 6
4 does not go off. The time required for this recovery is P
Although it is determined by the on-resistance value of the MOS transistor 66, this resistance value is usually set to a considerably large value for the purpose of producing a sufficient potential difference with a not-too-large on-current of the memory transistor. Therefore, there is a drawback that the above recovery requires a long time.

In order to solve this drawback, a PMOS transistor 65 whose operation is controlled by using a clock signal φp and inputting the clock signal φp to the gate, and the PM transistor
The inverter 6 connected in series with the OS transistor 65
And an NMOS transistor 63 to which the output potential of 1 is applied to the gate, and a PMOS transistor 65 and an NMO are provided.
By setting the on-resistance value of the S-transistor 63 to be relatively low, the input side potential of the detection amplifier 53 is rapidly recovered. However, even in the sense amplifier 53 configured as described above, during the period when the clock signal φp is at the L level, the current is diverted to the input side of the inverter 69 by the PMOS transistor 65 and the NMOS transistor 63 in addition to the ON current of the memory transistor. Therefore, there is the first problem that the input side potential of the inverter 69 cannot show a normal potential, and the detection amplifier 53 does not operate normally. Therefore, the access time cannot be shortened beyond a certain level regardless of whether or not there is a solution that has a long recovery time.

Further, there is a second problem that a sufficient L potential may not be supplied to the inverter 69 due to variations in the on-resistance value of the PMOS transistor 66 and variations in the on-current of the memory transistor.

Further, NMOS transistors 67 and 68 are provided for direct negative feedback of the inverter 61 for the purpose of removing the positive noise applied to the sense amplifier 53. As described above, since the inverter 61 that applies the negative feedback does not operate normally with respect to the NMOS transistor 64, the clock signal φp is separately supplied to the gate of the NMOS transistor 68 to control the operation of the NMOS transistor 68. ing. Further, since it is considered that the forward noise is normally input only when the selected memory transistor has a high resistance or is in an off state, the fact that the input of the inverter 69 is at the H level in such a state is utilized to make the NMOS transistor 67. The input side of the inverter 69 is connected to the gate of the. In this way, when the memory transistor has a high resistance or is off and the clock signal φp is at the H level, the input and output of the inverter 61 are short-circuited, the resistance of the input of the detection amplifier 53 is temporarily lowered, and noise is absorbed and the inverter 61 is absorbed. Tries to maintain the inversion potential of. In this case, as described above, the sense amplifier 53 has a third problem that it cannot operate normally. Also, since it takes a long time to recover this potential,
Access time cannot be faster than a certain value.

The present invention has been made in order to solve the above-mentioned problems, and maintains the access time to the memory transistor in a short state, and further improves the current-to-voltage amplification factor to improve the detection accuracy. An object of the present invention is to provide a sense amplifier that operates reliably.

[0011]

According to the present invention, there is provided a first transistor having a low ON resistance value, which is serially connected to the first positive power source between the first positive power source and the semiconductor memory means. A second transistor connected in series to the first transistor between the first transistor and the semiconductor memory means, to which a negative feedback circuit having a first inverting element is connected, a second positive power supply and a sense amplifier output section. And a third transistor that is connected in series to the second positive power supply and that forms a current mirror structure with the first transistor.

By connecting the output part of the sense amplifier to the output side of the third transistor and making the first transistor and the third transistor have a current mirror structure, the current value flowing through the third transistor and the current flowing through the first transistor are Proportional to the value. Therefore, since the potential of the contact portion between the first transistor and the second transistor is not directly related to the output signal of the detection amplifier, the use of the current mirror structure for the first transistor and the third transistor means that the ON resistance of the first transistor is increased. The value can be set low, and the resistance value of the negative feedback circuit of the first inverting element can be lowered. Therefore, the above configuration enables the potential of the input portion of the sense amplifier to be set constant in a short time, and acts to speed up the access time to the memory transistor.

The present invention also includes a sense amplifier having a fourth transistor to which the output signal of the first inverting element is supplied to the gate of the second inverting element, the sense amplifier being between the second transistor and the semiconductor memory means. A noise removing unit may be provided to prevent the potential of the input section of the sense amplifier from rising due to noise input to the input section.

The noise removing means acts to suppress the rise of the potential by detecting the rise in the potential of the sense amplifier input section due to noise input to the sense amplifier input section. Therefore, the provision of noise removal means
The current value flowing through the first transistor, that is, the third transistor stabilizes, and acts to stabilize the output signal level of the sense amplifier.

Further, according to the present invention, the third positive power source is connected in series between the third positive power source and the dummy semiconductor memory means,
A fifth transistor having a low on-resistance value;
A sixth transistor connected in series with the fifth transistor between the transistor and the dummy semiconductor memory means, to which a negative feedback circuit having a third inverting element is connected;
A seventh transistor which is connected in series to a positive power source and forms a current mirror structure with the fifth transistor; and an eighth transistor whose output signal from the third inverting element is supplied to the gate via a fourth inverting element, Noise removing means for preventing an increase in the potential of the input portion due to noise input to the input portion between the sixth transistor and the dummy semiconductor memory means, and the third transistor and the seventh transistor, respectively. 9th and 1st connected in series
An output signal stabilizing unit in which the 0-transistor has a current mirror structure may be provided.

Since the dummy semiconductor memory means is composed of a semiconductor memory transistor having a low on-resistance value, the current value flowing through the seventh transistor simulates a value when the semiconductor memory transistor having a low on-resistance value is selected. Connecting the tenth transistor serially connected to the seventh transistor and the ninth transistor having a current mirror structure and connected to the third transistor in series means that the current value flowing through the seventh transistor and the third transistor It acts so as to be proportional to the current value flowing through. Therefore, the above-described structure acts so that the detection operation is corrected and the detection amplifier outputs a signal of a correct level even when the memory transistors have different on-resistance values due to manufacturing conditions.

Further, according to the present invention, an eleventh transistor connected in series with the fifth positive power source between the fifth positive power source and the semiconductor memory means and having a low on-resistance value, the eleventh transistor and the semiconductor memory means. Between the above and 11th
A twelfth transistor connected in series to the transistor, to which a negative feedback circuit having a fifth inverting element is connected, is connected in series to the fifth positive power supply between a fifth positive power supply and ground, and is connected to the eleventh transistor and a current. Mirror structure thirteenth
A transistor; a fourteenth transistor connected between the thirteenth transistor and ground; a fifteenth transistor serially connected to the sixth positive power supply between a sixth positive power supply and the sense amplifier output section; It is characterized in that it is provided between the sense amplifier output section and the ground, and is provided with the fourteenth transistor and a sixteenth transistor having a current mirror structure.

The eleventh to thirteenth transistors have the same operation as the above-mentioned first to third transistors, respectively. Further, the fourteenth transistor is turned on by the current flowing through the thirteenth transistor, and the fourteenth and sixteenth transistors have a current mirror structure, so that the current flowing through the fourteenth transistor is proportional to the current flowing through the sixteenth transistor. . Further, the output potential of the sense amplifier is the same as the current characteristic flowing through the fifteenth transistor and the first potential.
The characteristics of the current flowing through the six transistors. In this way, the fifteenth transistor has a circuit connection that is not related to the precharge operation for recovering the potential on the input side of the detection amplifier, so that the current characteristic of the fifteenth transistor is such that the constant current value of the fifteenth transistor is substantially constant. Can be set to an ideal characteristic value. Further, since the constant current value of the sixteenth transistor is almost constant, the connection point between the fifteenth transistor and the sixteenth transistor is set as the output terminal of the detection amplifier, so that the fifteenth transistor and the sixteenth transistor are connected to the detection amplifier. To improve the current-to-voltage amplification factor, and further improve the current-to-voltage amplification factor to improve the detection accuracy of the output side potential of the semiconductor memory means.

Further, according to the present invention, the seventh positive power source is connected in series between the seventh positive power source and the dummy semiconductor memory means,
A seventeenth transistor having a low on-resistance value, and an eighteenth transistor connected in series to the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means and connected to a negative feedback circuit having a sixth inverting element. Is connected in series to the seventh positive power supply between a seventh positive power supply and ground, and is connected between the nineteenth transistor forming a current mirror structure with the seventeenth transistor, and the nineteenth transistor and ground. 20th transistor and 8th
Connected in series to the eighth positive power supply between a positive power supply and a sense amplifier output section, connected between the fifteenth transistor and a twenty-first transistor forming a current mirror structure, and between the sense amplifier output section and a ground; A twenty-second transistor having a current mirror structure with the twentieth transistor may be provided.

With this configuration, when the ON resistance value in the semiconductor memory means on the normal side differs depending on the manufacturing conditions, the normal side detection amplifier having the structure according to claim 4 cannot detect the normal operation. Even if
The dummy-side sense amplifier including the seventeenth to twenty-second transistors and performing the sensing operation of the dummy semiconductor memory means acts so as to correct the sensing operation according to the difference in the on-resistance value and enable the normal sensing operation. .

Further, according to the present invention, one dummy memory transistor, which has the same structure as the memory transistor constituting the semiconductor memory means and is in an ON state, is connected, and a reference current of a predetermined multiple of a current value which can be passed by the dummy memory transistor. Reference voltage value sending means for detecting a value, and the first
A gate of one transistor and the thirteenth transistor and an output side of the reference voltage value sending means are connected, and a current value flowing through the eleventh transistor is compared by comparing the current value flowing through the eleventh transistor with the reference current value. Is greater than or equal to the reference current value, the precharge detection means for detecting the precharge state in the semiconductor memory means and the output side of the precharge detection means are connected, and the precharge detection means precharges the semiconductor memory means. And a pre-charge-enhancing current supply means for flowing a current in addition to the value of the current flowing through the eleventh transistor between the eleventh transistor and the semiconductor memory means when detecting the charging state. it can.

With this configuration, the precharge detecting means acts so as to detect that the output side of the semiconductor memory means is in the precharged state, and when it is in the precharged state, it is supplied through the thirteenth transistor. In addition to the generated current, the precharge enhancing current supply means acts to supply the precharge current to the output side of the semiconductor memory means. Therefore, the precharge detection means and the like act to shorten the time required for the precharge operation of the semiconductor memory means and shorten the access time to the memory transistor.

Further, according to the present invention, the seventh positive power source is connected in series between the seventh positive power source and the dummy semiconductor memory means,
A seventeenth transistor having a low on-resistance value, and an eighteenth transistor connected in series to the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means, to which a negative feedback circuit having a seventh inverting element is connected. Is connected in series to the seventh positive power supply between a seventh positive power supply and ground, and is connected between the nineteenth transistor forming a current mirror structure with the seventeenth transistor, and the nineteenth transistor and ground. 20th transistor and 8th
A twenty-first transistor connected in series to a positive power source and forming a current mirror structure with the fifteenth transistor;
A second transistor connected between the first transistor and ground and forming a current mirror structure with the twentieth transistor, gates of the seventeenth transistor and the nineteenth transistor, and an output side of the reference voltage value sending means, By comparing the current value flowing through the seventeenth transistor and the nineteenth transistor with the reference current value, the current value flowing through the seventeenth transistor and the nineteenth transistor becomes the reference current value or more.
A second precharge detecting means for detecting a precharge state in the dummy semiconductor memory means is connected to an output side of the second precharge detecting means, and the dummy semiconductor memory means is precharged by the second precharge detecting means. A second precharge-enhancing current supply means for supplying a current in addition to the value of the current flowing through the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means when the state is detected. You may do it.

With this configuration, the dummy-side detection amplifier including the seventeenth to twenty-second transistors, the second precharge detection means, and the second precharge enhancement current supply means detects the normal side detection amplifier. Even if the operation has different memory transistor characteristics depending on the manufacturing conditions and the normal operation cannot be performed, the detection operation is corrected to operate normally.

Further, according to the present invention, there is provided a detecting and amplifying means having a current mirror structure, wherein an input side is connected to an output side of the semiconductor memory means, and a detecting operation of a current value sent by a detection target memory transistor in the semiconductor memory means is carried out. A dummy detection amplifier having a current mirror structure, an input side of which is connected to an output side of a dummy semiconductor memory means simulating the semiconductor memory means, and which detects a current value sent by a dummy memory transistor in the dummy semiconductor memory means. Means, a load terminal connected to the input side of the detection output means connected to the output side of the detection amplification means, and a control current input terminal connected to the output end of the dummy detection amplification means, The current value sent from the detection output means is determined in relation to the current value on the output side of the detection amplification means. And a load means for flowing a reference current of the dummy semiconductor memory means, wherein the dummy semiconductor memory means has a maximum current value and a minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. It is characterized in that it is a comparison current generating means for generating a current having a current value between that and the current value of.

With this configuration, the comparison current generating means has a current value between the maximum current value and the minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. Since a current is generated, the reference current flowing through the load means is set to a current value corresponding to the maximum current value and the minimum current value, which improves detection accuracy.

The comparison current generating means has a dummy semiconductor memory array having a low on-resistance value, a low resistance dummy semiconductor memory means connected to the input side of the dummy detecting and amplifying means, and a high on-resistance value. A dummy semiconductor memory array having a high resistance dummy semiconductor memory means connected in parallel to an output side of the low resistance dummy semiconductor memory means and an input side of the dummy detection amplification means, and an equivalent of the dummy detection amplification means. The high resistance and low resistance dummy semiconductor memory means may have an equivalent resistance value and a shunt means having an input side connected to an output side connected in parallel.

With this configuration, the low resistance dummy semiconductor memory means, the high resistance dummy semiconductor memory means, and the shunt means use the reference current flowing through the load means as a current corresponding to the maximum current value and the minimum current value. Set to a value to improve detection accuracy.

Further, according to the present invention, the detecting and amplifying means having a current mirror structure, the input side of which is connected to the output side of the semiconductor memory means, and the operation of detecting the current value sent by the detection target memory transistor in the semiconductor memory means is carried out. And the input side is connected to the output side of the dummy semiconductor memory means simulating the semiconductor memory means to detect the current value sent out by the dummy memory transistor in the dummy semiconductor memory means. Amplification means, a load terminal connected to the input side of the detection output means connected to the output side of the detection amplification means, and a control current input terminal to which the output end of the dummy detection amplification means is connected, To determine the current value sent from the detection output means in relation to the current value at the output side of the detection amplification means A load means for supplying a reference current, the dummy semiconductor memory means has a dummy semiconductor memory array having a low on-resistance value, and a low resistance dummy semiconductor memory means connected to the input side of the dummy detection amplification means; A dummy semiconductor memory array having an ON resistance value, and a high resistance dummy semiconductor memory means connected in parallel to an output side of the low resistance dummy semiconductor memory means and an input side of the dummy detection amplification means, A sense amplifier which is a comparison current generating means for generating a current having a current value between a maximum current value and a minimum current value among current values flowing through the memory transistor to be detected selected from the semiconductor memory means. The current amplification factor of the current mirror structure of the detection amplification means is higher than the current amplification factor of the current mirror structure of the dummy detection amplification means. Characterized in that it is a major.

With such a configuration, the ratio of the current amplification factors in the detection amplification means and the dummy detection amplification means is such that the reference current value flowing through the load means is the current flowing through the detection target memory transistor selected from the semiconductor memory means. Of the values, the current value is set to be between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value, and the detection accuracy is improved.

Further, the comparison current generating means according to claims 8 and 10 has the same number of serial connection stages as or more than the number of series connection stages of the memory transistors in the current path to the ground of the semiconductor memory array included in the semiconductor memory means. The same number of semiconductor memory transistors having a low on-resistance value forming a current path to the ground and the number of memory transistors connected in series in the current path to the ground of the semiconductor memory array included in the semiconductor memory means, or It may include a semiconductor memory transistor having a high on-resistance value, which is connected to the semiconductor memory array in parallel and which forms a current path to the ground having a higher number of stages.

With such a configuration, the comparison current generating means can calculate the
The current value is set to be between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value, and the detection accuracy is improved.

[0033]

【Example】

First Embodiment: A first embodiment of the sense amplifier of the present invention will be described with reference to FIG. The input side of the sense amplifier 1 to which the output side of the selection section 52 is connected has an NMO connected to the input side.
The source side of the S transistor 4 is connected, and the drain side of the NMOS transistor 4 is connected to the positive power source 2 at the source side.
3 is connected in series. In addition, PM
The on-resistance value of the OS diode 3 is set lower than the on-resistance value of the conventional PMOS diode when used in the circuit configuration as described above. For example, in the circuit configuration as described above, the voltage drop value due to the ON resistance in the conventional PMOS diode is approximately equal to the power supply voltage value of 5 V, but the voltage drop value in the PMOS diode 3 in this embodiment is about 0.5.
It is about V, which is about 10 times different from the conventional one. Explaining the voltage drop value further, the lower limit value of the voltage drop value is a value which is not less than the voltage value in a so-called bit line connected from the memory array section 51 to the detection amplifier via the selection section 52. The upper limit value is a value sufficient for the PMOS diode 3 to operate as a current mirror structure described later.

Further, on the input side of the sense amplifier 1, the inverter 5 in the inverters 5 and 6 connected in series is provided.
Is connected to the input side thereof, and the source side is grounded, and the drain side of the NMOS transistor 7 to which the output side of the inverter 6 is connected to the gate is connected. The inverted potential of the inverter 6 is set to an intermediate potential between the inverted potential of the inverter 5 and the potential obtained by adding the threshold voltage of the NMOS transistor 4 to the inverted potential. The connection point between the PMOS diode 3 and the NMOS transistor 4 is connected to the gate of the PMOS diode 3 and the gate of the PMOS transistor 9 whose source is connected to the positive power supply 8. still,
The on-resistance value of the PMOS transistor 9 may be different from the on-resistance value of the PMOS diode 3 described above, but it is preferable to design the same or higher value during normal design. This is because it is desirable to set the current amplification factor by the current mirror circuit described later to 1 or more.

An NMOS transistor 10 whose source side is grounded is connected in series to the drain side of the PMOS transistor 9, and the PMOS transistor 9 and the NMOS transistor 10 are connected in series.
The connection point with the transistor 10 is connected to the output section via the inverter 11. For the sake of explanation, the above-mentioned constituent part 2
The part composed of 9 to 9 is referred to as a detection amplification part.

With this structure, the PMOS diode 3 and the PMOS transistor 9 form a current mirror structure. Therefore, the current value that the PMOS transistor 9 tries to flow is proportional to the current value that flows in the PMOS diode 3. Therefore, PM like a conventional sense amplifier
The potential of the connection point between the OS transistor and the NMOS transistor does not become the output signal level of the sense amplifier. Therefore, even if the selected memory transistor has a low resistance, the PMOS diode 3 and N
By adjusting the on-resistance value of the MOS transistor 4, it is possible to prevent the input potential of the sense amplifier from being unnecessarily lower than the inversion potential of the inverter 5.

In the manufacture of an integrated circuit, when a large number of memory transistors forming the semiconductor memory array are formed of low on-resistance values,
On the other hand, on the contrary, it may change from wafer to wafer, such as in the case where a large number of on-resistance values are provided. Therefore, in the present sense amplifier 1, when many of the memory transistors that form the semiconductor memory array have low on-resistance values, or conversely, when many of them have high on-resistance values. Even
H, L in which the output signal level of the inverter 11 is stable
A dummy detection amplification unit 12 having substantially the same circuit configuration as the detection amplification unit described above is provided so that the resistance value of the load of the PMOS transistor 9 can be automatically adjusted to reach the level.

On the input side of the dummy sense amplifier 12, there is a known semiconductor memory array, that is, the dummy memory array section 13 having the same structure as the above-mentioned memory array section 51 and composed only of memory transistors having a low ON resistance value. The output side of the dummy selection section 14 to which the output side is connected and which has the same configuration as the selection section 52 is connected. A decoder section is connected to the dummy memory array section 13 and the dummy selection section 14 as shown in FIG. Further, the circuit portion including the dummy memory array section 13 and the dummy selection section 14 is referred to as dummy semiconductor memory means 601.

The dummy detection amplifier 12 is configured as follows, like the detection amplification section. That is, on the input side of the dummy detection amplification section 12, the source side of the NMOS transistor 17 is connected to the input side, and the drain side of the NMOS transistor 17 is connected to the positive power source 15 on the source side. 16 is connected in series. In addition, PMOS
The on resistance value of the diode 16 is equal to the PMO described above.
Like the S diode 3, it is set low.

Further, the input side of the dummy detection amplifier 12 is connected to the input side of the inverter 18 in the inverters 18 and 19 connected in series, and the source side is grounded and the output side of the inverter 19 is connected to the gate of the NMOS. The drain sides of the transistors 20 are connected to each other. The connection point between the PMOS diode 16 and the NMOS transistor 17 is a PMO whose source side is connected to the gate of the PMOS diode 16 and the positive power source 21.
It is connected to the gate of the S transistor 22. In addition, PMO
The on-resistance value of the S transistor 22 may be different from the on-resistance value of the PMOS diode 16,
It is preferably the same value or more.

An NMOS transistor 23 whose source side is grounded is connected in series to the drain side of the PMOS transistor 22, and the drain side of the NMOS transistor 23 is connected to the NMOS transistor 23 and the above-mentioned NMOS.
It is connected to each gate of the transistor 10.

The operation of the sense amplifier 1 configured as described above will be described below. The inverter 5 and the NMOS transistor 4 operate so as to make the input side potential of the detection amplification unit constant, similar to the operation of the conventional detection amplifier. That is,
Among the memory transistors forming the memory array section 51, the high resistance or the low resistance of the selected memory transistor causes the NMOS transistor to be turned off or on as described above. Further, as described above, the PMOS diode 3 and the PMOS transistor 9 have a current mirror structure.

Therefore, when the selected memory transistor has a high resistance, the NMOS transistor 4 is turned off, so that the PMOS diode 3 and the PMOS transistor 9 are in a state in which almost no current flows or no current flows. . Therefore, the input side potential of the inverter 11 becomes L level, and the H level signal is sent to the output section.

On the other hand, when the memory transistor has a low resistance or is in the ON state, the NMOS transistor 4 is kept in the ON state by the action of the inverter 5. Therefore, the input side of the detection amplification unit is connected to the PMOS diode 3 and the NM.
Although the potential is determined by the ON resistance of the OS transistor 4, the resistance value via the NMOS transistor 4 is changed to the PMOS value by adopting the current mirror structure.
It can be lowered by lowering the ON resistance value of the diode 3. Therefore, the current can be supplied at high speed from the positive power supply 2 through the PMOS diode 3.

Therefore, even if the memory transistor having a low resistance is selected and then the memory transistor selected next has a high resistance or is in an off state, the potential on the input side of the sense amplifier, which is a drawback of the conventional sense amplifier, is reduced. The problem that the sense amplifier does not operate normally until it recovers is solved. Therefore, the potential of the input section of the sense amplifier can be kept constant for an extremely short period of time without requiring a separate clock signal as in the conventional sense amplifier, and high-speed access is possible.

When the selected memory transistor has a low resistance, the current flows through the PMOS diode 3, so that the current also flows through the PMOS transistor 9 due to the current mirror structure. Therefore, the input side potential of the inverter 11 becomes H level, and the L level signal is sent to the output section.

Since the present detection amplifier operates as described above, the output side potential of the inverter 5 is normally the inversion potential of the inverter 5 plus the threshold voltage of the NMOS transistor 4 during the above-mentioned operation period. It never drops below the potential. However, when positive-direction noise is input to the input side of the sense amplifier, the above potential may decrease.

In such a case, as described above, the inversion potential of the inverter 6 is set to an intermediate potential between the inversion potential of the inverter 5 and the potential obtained by adding the threshold voltage of the NMOS transistor 4 to the inversion potential. When the above noise is input, the output side of the inverter 6 becomes H level, and N
The MOS transistor 7 is turned on. Therefore, the potential at the input section of the detection amplification section is lowered, and the noise is removed. When the output side potential of the inverter 5 rises, the output side potential of the inverter 6 changes to the L level and NM
The OS transistor 7 changes to the off state.

By providing the inverter 6 in this way, when noise in the positive direction input to the sense amplifier is input,
By controlling the gate voltage of the NMOS transistor 7, it is possible to reduce the input resistance of the detection amplification unit and quickly remove the noise. Therefore, the NMOS transistor 4
Since the operation of is stable, the signal level sent from the inverter 11 to the output section can be stabilized without delay.

Further, by providing the dummy detection amplification section 12, it is possible to simulate the output current value of the detection amplification section when the ON resistance value of the selected memory transistor is low. That is, in the dummy detection amplification unit 12, the selected memory transistor has a low on-resistance value, and as described above, the PMOS transistor 22.
Current flows. Therefore, the NMOS transistor 23 is turned on, and the NMOS transistor 10 forming a current mirror structure with the NMOS transistor 23 also has an NMO.
A current proportional to the current flowing through the S transistor 23 flows. Therefore, the magnitude of the current flowing through the PMOS transistor 9 can be made proportional to the magnitude of the current flowing through the PMOS transistor 22 in the dummy detection amplification section.

As described above, when the ON resistance value of the memory array section 51 is biased to the lower side due to the manufacturing conditions, the amount of current flowing through the PMOS transistor 9 is automatically adjusted accordingly, and conversely the above. When the ON resistance value is biased toward the higher side, the amount of current flowing through the PMOS transistor 9 can be automatically adjusted to increase. Therefore, a stable H or L level potential is supplied to the input side of the inverter 11, and an erroneous output level is not sent from the sense amplifier 1. Therefore, the sense amplifier 1
Since the operation is guaranteed, the reliability of the memory circuit operation can be improved.

Further, by providing the dummy detection / amplification unit 12, the detection limit due to the variation of the ON current of the memory transistors in the memory array unit 51 due to the manufacturing conditions depends on the absolute error to the relative error by the automatic correction function. Therefore, the product yield of the sense amplifier is improved. Therefore, the reliability of the operation as the sense amplifier is improved.

Second Embodiment: By adopting the circuit configuration described in the first embodiment, as shown in FIG.
Although the ON resistance of the MOS diode 3 can be reduced, there is a limit to the reduction of the ON resistance due to the limitation of the current mirror operation with the PMOS transistor 9. That is,
For example, in the case of low voltage operation in which the power supply voltage is 2 to 3.6 V, the on-current of the memory transistor in the memory array section 51 is small, but even in that case, the voltage in the PMOS diode 3 necessary for the current mirror operation. The descent must be kept constant. Therefore, since the on resistance value of the PMOS diode 3 needs to be set to a certain value or more, in the circuit configuration of the first embodiment, the output side of the memory array section 51 and the column selection section 52, in other words, the input of the detection amplifier concerned. P on the side bit line
There is a drawback in that the precharge operation for supplying a current via the MOS diode 3 cannot be accelerated beyond a certain level.

Since the PMOS diode 3 and the PMOS transistor 9 have a current mirror structure,
The impedance of the PMOS transistor 9, which appears at the drain of the PMOS transistor 9, changes relative to the on-current of the memory transistor. The response speed at this time is almost P
It depends on the gate capacitances of the MOS diode 3 and the PMOS transistor 9, and if the gate capacitance is large, the response speed becomes slow. Therefore, the gate channel length of these transistors should be selected to be the minimum length allowed by the process.

However, although the ON resistance value is reduced by shortening the gate channel length of the PMOS transistor, for example, as shown in FIG. 6A, the constant current characteristic in the saturation region of the PMOS transistor 9 is By turning on and off, the slope of the graph showing the current characteristics in the saturation region becomes large as shown by the dotted line. On the other hand, the characteristics of the NMOS transistor 10 do not change as in the PMOS transistor 9 because the channel length is not changed, and the characteristics show a substantially constant current in the saturation region.

In the first embodiment, as described above, the PMO
Since the connection node potential between the S transistor 9 and the NMOS transistor 10 is used as the output of the detection amplifier, the inverter 1
6 to provide sufficient logic levels on the input side of FIG.
As shown by "A" in (a), it is necessary to swing the drain-source voltage of the PMOS transistor 9 from approximately the ground potential to the positive power supply potential. Therefore, when the drain-source voltage as shown in “A” above is set, the PMO
P when the gate channel length of the S transistor is shortened
The constant current characteristic of the MOS transistor is shown by the dotted line graph B.
It becomes like 1, B2. In FIG. 6A, for example, the gate voltage of the PMOS transistor when the drain voltage value is “D” will be obtained from FIG. 6B. Incidentally, FIG. 6B shows the relationship between the gate voltage and the drain current of the PMOS transistor.

At the drain voltage value "D", graph B
The drain current values of the PMOS transistor when showing the characteristics of 1 and B2 are "D1" and "D2". As shown in FIG. 6B, the change amount of the gate voltage of the PMOS transistor at this time is "D1" and "D2". It becomes E ". On the other hand, the characteristics of the PMOS transistor when the gate channel length is set to be long without being shortened are shown in FIG.
The current characteristics are indicated by 1 and C2. In such a current characteristic, as in the case described above, the drain current values of the PMOS transistor when the drain voltage value is “D” are “D3” and “D4”, respectively, as shown in FIG. The change in the gate voltage of the PMOS transistor at this time is "F".

Further, as is clear from FIG. 6A, when the drain voltage value is "D", the change amount of the drain current value in the PMOS transistor of each characteristic is smaller than that in the PMOS transistor having a shorter gate channel length than that of the PMOS transistor. There are fewer PMOS transistors with longer channel lengths. As described above, when the change in the output of the sense amplifier is fixed to "A", the drain in the PMOS transistor having a longer gate channel length than the change in the drain current (D1-D2) in the PMOS transistor having a short gate channel length. Since the amount of change in current (D3-D4) is smaller, there is a drawback that the amplification factor of current-to-voltage in the PMOS transistor becomes worse when the gate channel length is shortened. That is, the improvement of the operating speed of the PMOS transistor and the improvement of the current-to-voltage amplification factor are contradictory.

The sense amplifier according to the second embodiment further eliminates these drawbacks, and by precharging the bit line at a higher speed, the memory transistor can be accessed at a higher speed, and further the current-to-voltage amplification is performed. It is configured for the purpose of improving the rate and the detection accuracy.

The second embodiment will be described below with reference to FIGS. 2 and 3. It should be noted that FIGS. 2 and 3 are originally shown in one figure, but are divided for convenience of space, and are shown at corresponding portions * 1 to * 4 in FIGS. 2 and 3, respectively. It is united in one figure by connecting with. or,
2 and 3, the same components as those shown in FIG. 1 referred to in the first embodiment are designated by the same reference numerals. Therefore, the operation and the like of these constituent parts are the same as the contents described in the first embodiment described above, and the description thereof will be omitted unless there is a special note.

As in FIG. 1, the source of the PMOS diode 3 is connected to the positive power supply 100, and the PMOS diode 3 is connected.
Is connected to the drain of the NMOS transistor 4, and the source side of the NMOS transistor 4 is connected to the output side of the column selection section 52 connected to the memory array section 51. The output side of the column selection unit 52 is connected to the gate of the NMOS transistor 4 via the inverter 5,
The drain side of the S diode 3 is the PMOS diode 3
Connected to the gate.

Furthermore, the source is connected to the positive power source 100, the gate of the PMOS diode 3 is connected to the gate of the PMOS transistor 9, and the drain side of the PMOS transistor 9 forming a current mirror structure with the PMOS diode 3 is an NMOS diode. Connected to the drain of 101. The drain side of the NMOS diode 101 is connected to the gate of the NMOS diode 101,
The source side of the MOS diode 101 is grounded. still,
As described below, the output point of the sense amplifier is
Since the configuration is taken from the connection portion between the transistor 102 and the PMOS transistor 104, the PMOS transistor 9 has a structure in which the gate channel length of the PMOS transistor 9 is as short as possible for the purpose of improving the operation speed.

Thus, the gate channel length of the PMOS transistor 9 is made short and the NMOS shown in FIG.
The NMOS diode 10 shown in FIG.
By setting it to 1, the PMOS transistor 9 and the NMOS
The current characteristic of the diode 101 is as shown in FIG. The current characteristic of the PMOS transistor 9 shown in FIG. 7 is equal to the current characteristic of the PMOS transistor shown by the dotted line in FIG. Therefore, the drain current value flowing through the contact portion between the PMOS transistor 9 and the NMOS diode 101 is obtained from the intersection of the current characteristic graph of the PMOS transistor 9 and the current characteristic graph of the NMOS diode 101, and the change amount is clear from FIG. Thus, the size is indicated by "G". Thus, the drain side of the NMOS diode 101 is connected to the NMOS diode 1
Since the current characteristic of the NMOS diode 101 shows a steep rise by connecting it to the gate of 01, the change "G" of the drain current value becomes larger than that of a simple resistive load.

PMO whose source is connected to the positive power source 103
The drain side of the S-transistor 104 is connected to the output terminal of the sense amplifier of the present embodiment and also has an NMOS.
It is connected to the drain of the transistor 102. In addition, PM
Since the OS transistor 104 has nothing to do with the precharge operation of the bit line, it is not necessary to keep the on-resistance value low, and therefore it is not necessary to shorten the channel length. Therefore, the drain current characteristic with respect to the drain voltage in the PMOS transistor 104 can be made substantially flat in the saturation region as shown in FIG. Therefore, since the current characteristic of the NMOS transistor 102 is essentially flat, the change in the gate voltage of the PMOS transistor 104 can be reduced as shown by “F” in FIG. By setting the connection point between 104 and the NMOS transistor 102 as the output terminal of the detection amplifier, the current-to-voltage amplification factor of the detection amplifier can be improved.
Further, since the current-to-voltage amplification factor is improved, the detection capability for the variation in the on-current of the memory transistor is improved, and the product yield is improved. Therefore, the operational reliability of the product can be improved.

The gate of the NMOS transistor 102 is connected to the gate of the NMOS diode 101, and N
MOS diode 101 and NMOS transistor 102
Forms a current mirror structure. The source side of the NMOS transistor 102 is grounded.

Furthermore, the source is connected to the positive power source 201, and the drain side of the PMOS transistor 202, whose on resistance is formed lower than that of the PMOS diode 3, is NM.
NMO connected to the drain side of the OS transistor 203
The source side of the S transistor 203 is connected between the source of the NMOS transistor 4 and the input side connection point of the inverter 5 in the bit line. Also, NMOS
The output side of the inverter 5 is connected to the gate of the transistor 203.

Further, the positive power supply 201, the PMOS transistor 202, and the NMOS transistor 203 constitute the precharge strengthening current supply circuit 200. The pre-charge enhancing current supply circuit 200 is used to flow a current having a current value larger than the current value into the bit line in addition to the current flowing into the bit line via the PMOS diode 3 when pre-charging the bit line. The circuit is a circuit for increasing the speed of the precharge operation.

The reference voltage value sending circuit 250 and the precharge detecting circuit 300 shown in FIG. 3 are circuits related to the precharge operation of the bit line together with the above-mentioned precharge enhancing current supply circuit 200. That is, as described above, the PMOS diode 3, the PMOS transistor 9 and the PMOS transistor 302 described later have a current mirror structure. As will be described later, many current mirror structures are provided in the present embodiment, and current flows from the positive power supply to the parts forming the current mirror structure during precharge, resulting in increased power consumption. The reference voltage value sending circuit 250 and the like are circuits for suppressing the power consumption during precharge.

The start of the precharge operation is detected by the PMOS diode 3 in the states other than the precharge.
Since the current value flowing through the memory transistor does not exceed the on-current value of the memory transistor, the on-current value of the memory transistor sent from the reference voltage value sending circuit 250 and the current value flowing through the bit line are That is, PMO
This can be done by comparing with the value of the current flowing through the S diode 3.

The reference voltage value sending circuit 250 is a circuit for generating a current value corresponding to the above-mentioned on-current value of the memory transistor, and the on-current value of the memory transistor sent from the output terminal of the sense amplifier shown in FIG. The voltage used for the purpose of detecting the reference current having the same value as or a value corresponding to several times the ON current is transmitted. Therefore, the circuit configuration of the reference voltage value sending circuit 250 is such that the input side of the inverter 5 shown in FIG. 2 is connected to the memory transistor 251 in the ON state, and the precharge enhancing current supply circuit 20.
The circuit configuration is the same as that shown in FIG. The characteristics of each element such as the on-resistance value are determined by the reference voltage value sending circuit 2
When the reference current value indicated by the output voltage value of 50 and the output current value of the detection amplifier are the same, the conditions are exactly the same,
When the output voltage value of the reference voltage value sending circuit 250 is set to a value corresponding to a multiple of the output current value of the detection amplifier, for example, the PMOS diode 253 and the PMOS transistor 256, or the NMOS diode 257 and the NMOS.
The ratio of the channel width with the transistor 258 may be changed.

Therefore, although the circuit configuration of the reference voltage value sending circuit 250 will be briefly described, the positive power supply 100 shown in FIG.
3 corresponds to the positive power supply 252 shown in FIG.
Is a PMOS diode 253,
The one corresponding to the MOS transistor 4 is the NMOS transistor 254, the one corresponding to the inverter 5 is the inverter 255, the one corresponding to the PMOS transistor 9 is the PMOS transistor 256, and the NMO.
An NMOS diode 257 corresponds to the S diode 101, an NMOS transistor 258 corresponds to the NMOS transistor 102, and a PMOS.
The PMOS transistor 259 corresponds to the transistor 104. Further, the drain side of the PMOS transistor 259 is provided in the gate of the PMOS transistor 259 and the precharge detection circuit, which will be described later.
It is connected to the gate of the transistor 305. In addition, PMO
The voltage value sent from the drain side of the S transistor 259 is the voltage value indicating the reference current value provided from the reference voltage value sending circuit 250.

The precharge detection circuit 300 is a PMOS
It is a circuit that compares the current value flowing through the diode 3 with the reference current value provided by the reference voltage value sending circuit 250 described above, and sends a signal level corresponding to the comparison result to the precharge enhancing current supply circuit 200. .

The precharge detection circuit 300 has the following circuit configuration. PM whose source side is connected to the positive power source 301
The gate of the OS transistor 302 has the PM shown in FIG.
The OS diode 3 and the gate of the PMOS transistor 9 are connected. Therefore, the PMOS transistor 302
Together with the PMOS diode 3 and the PMOS transistor 9 form a current mirror structure. The drain side of the PMOS diode 302 is connected to the drain side of the NMOS diode 303, the source side of the NMOS diode 303 is grounded, and the drain side of the NMOS diode 303 is connected to the gate of the NMOS diode 303.

Like the circuit configuration described above, the positive power source 301
As described above, the reference voltage value sending circuit 250 is connected to the gate of the PMOS transistor 305 whose source side is connected to
The output end of is connected. Therefore, the PMOS transistor 305 is the PMOS included in the reference voltage value sending circuit 250.
It forms a current mirror structure with the transistor 259. PM
The drain side of the OS transistor 305 is connected to the drain side of the NMOS transistor 304, the source side of the NMOS transistor 304 is grounded, and the gate of the NMOS transistor 304 is the NMOS transistor 3 described above.
It is connected with the gate of 03. Therefore, the NMOS diode 303 and the NMOS transistor 304 form a current mirror structure. Further, the drain side of the PMOS transistor 305 is connected to the gate of the PMOS transistor 202 included in the above-mentioned precharge enhancing current supply circuit 200.

In the precharge detection circuit 300 having such a configuration, since the PMOS transistor 302 has a current mirror relationship with the PMOS transistor 3 and the like, PM
A current having a value several times the value of the current flowing through the OS transistor 3 flows through the PMOS transistor 302.

Furthermore, since the NMOS diode 303 and the NMOS transistor 304 in the precharge detection circuit 300 have a current mirror relationship, a current having a value several times the value of the current flowing through the NMOS transistor 303 flows through the NMOS transistor 304. That is, NMO
The value of the current flowing through the S transistor 304 corresponds to the value of the current flowing through the PMOS transistor 3.

Further, since the PMOS transistor 305 has a current mirror relationship with the PMOS transistor 259 provided in the reference voltage value sending circuit 250, the value of the saturation current characteristic flowing through the PMOS transistor 305 is several times the reference current value. Become.

Therefore, the PMOS transistor 305
The potential on the drain side, that is, the potential applied to the gate of the PMOS transistor 202 included in the precharge enhancing current supply circuit 200 is the value of the saturation current characteristic flowing through the PMOS transistor 3, in other words, the saturation current characteristic flowing through the NMOS transistor 304. Based on the saturation current characteristic value flowing through the PMOS transistor 305
OS transistor 305 and NMOS transistor 304
The drain voltage is determined from the drain current characteristics of and.

The output voltage from the precharge detection circuit 300 causes the P of the precharge enhancement current supply circuit 200 to rise.
The MOS transistor 202 turns on and off. That is, when the current value flowing through the PMOS transistor 3 is larger than the reference current value, that is, at the time of precharge, the output voltage of the precharge detection circuit 300 becomes L level and the PMOS transistor 202 is turned on.
Further, the NMOS transistor 203 is in the ON state by the output voltage of the inverter 5. Therefore, a current flows from the positive power source 201 to the bit line via the PMOS transistor 202 and the NMOS transistor 203.

The bit line is, of course, a PMOS.
A current is supplied from the positive power supply 100 via the diode 3, but as described above, since the ON resistance value of the PMOS transistor 202 is smaller than the ON resistance value of the PMOS transistor 3, the transistor is formed, A large amount of current flows into the bit line from the positive power supply 201 side. Therefore, as in the first embodiment, the PMOS
Since the precharge operation is not performed only through the transistor 3, the time required for precharge can be further shortened. Further, the shortening of the time required for precharging and the bypassing of the current result in the reduction of the current flowing through the PMOS transistor 9 in the current mirror relationship with the PMOS transistor 3.

Further, when the current value flowing through the PMOS diode 3 is smaller than or equal to the reference current value, that is, when other than the precharge, the output voltage of the precharge detection circuit 300 becomes the H level and the PMOS transistor 202 becomes It is turned off. Therefore, the positive power source 20
No current flows from 1 to the bit line.

The operation of the thus-configured sense amplifier will be described below. The operations of the NMOS transistor 4 and the inverter 5 are similar to those described in the first embodiment, and the NMOS transistor 4 and the inverter 5 operate so as to maintain the input side potential of the sense amplifier constant, and P
The operations of the MOS transistor 3 and the PMOS transistor 9 are the same as the operations described in the first embodiment, and the description thereof will be omitted.

In this embodiment, the NMOS diode 101 is used.
With regard to the above, the gate and drain of the NMOS diode 101 are connected to form a MOS diode and this is used as a load. Due to the current mirror relationship with the PMOS transistor 3, a current flows through the PMOS transistor 9, so that a current also flows through the NMOS diode 101.
When the current flows through the NMOS diode 101, the NM
NM in current mirror relationship with OS diode 101
A current also flows through the OS transistor 102.

As will be described later, the gate of the PMOS transistor 104 is connected to the gate of the PMOS transistor 359 provided in the dummy sense amplifier, and the PMOS transistor 104 and the PMOS transistor 359 form a current mirror relationship. And PMOS
A current several times as large as the current flowing through the PMOS transistor 359 flows through the transistor 104. When the dummy sense amplifier is not provided, the gate of the PMOS transistor 104 is grounded.

Therefore, the PMOS transistors 104 and N
The potential at the connection point with the MOS transistor 102 is
The potential corresponds to the current value determined by the mutual relationship between the current characteristic flowing through the PMOS transistor 104 and the current characteristic flowing through the NMOS transistor 102.

The current flowing through the PMOS transistor 104 is the PMOS transistor 3 in the dummy side sense amplifier.
Although it depends on the current flowing through the memory cell 59, the dummy memory array is composed of memory transistors having a low on-resistance value as will be described later. , The current sent from the memory transistor selected from the memory array 51 on the normal side can be accurately detected from the output terminal of the detection amplifier of this embodiment.

Further, since the PMOS transistor 104 has a circuit configuration that is completely unrelated to the PMOS diode 3 and the PMOS transistor 9 related to the bit line precharge operation, it is necessary to keep the ON resistance value low. Therefore, it is not necessary to shorten the channel length. Therefore, the drain current characteristic of the PMOS transistor 104 with respect to the drain voltage can be made substantially flat in the saturation region.

On the other hand, the drain current characteristic with respect to the drain voltage of the NMOS transistor 102 is flatter than that of the PMOS transistor 9 in the saturation region. Therefore, as shown in FIG. 5, the output potential of the sense amplifier of the present embodiment is determined by the two transistors whose drain current characteristics are substantially flat in the saturation region, so that the current-to-voltage amplification factor is the first. Improved compared to the example. Therefore, the current detection accuracy of the sense amplifier is determined by the ratio of the width of the current change required for the output potential of the sense amplifier to make a full swing with respect to the average value of the on-current value of the memory transistor. Can be improved.

Current supply circuit 200 for strengthening precharge,
The operations of the reference voltage value sending circuit 250 and the precharge detection circuit 300 will be briefly described above. At some time, a current is supplied to the bit line by the pre-charge enhancing current supply circuit 200.

Next, a case where a dummy memory array is further provided will be described. As described in the first embodiment, in order to further improve the detection operation accuracy, the dummy memory array and the other circuits associated with the dummy memory array also have the above-described circuit configuration in the second embodiment. Configure exactly the same. The reference current value sending circuit 250 is not separately provided because the reference current value can be shared. The detection amplifier that performs the detection operation of the dummy memory array is called a dummy-side detection amplifier, while the detection amplifier that performs the above-described normal memory array detection operation is called a normal-side detection amplifier.

The circuit on the dummy side will be described with reference to FIG. The connection of each element and the like are exactly the same as the connection relationship described above, and since the sameness can be easily determined from the drawings, detailed description will be omitted below, and only the correspondence relationship of each element will be described. First, refer to FIG. 2 and FIG. The dummy memory array section 35 corresponds to the memory array section 51.
It is 0. All the memory transistors forming the dummy memory array section 350 are formed of memory transistors having a low on-resistance value. The dummy column selection unit 351 corresponds to the column selection unit 52, the positive power supply 355 corresponds to the positive power supply 100, the PMOS diode 352 corresponds to the PMOS diode 3, and the NMO.
The NMOS transistor 353 corresponds to the S transistor 4, the PMOS transistor 356 corresponds to the PMOS transistor 9, the NMOS diode 357 corresponds to the NMOS diode 101, and the NMOS transistor 102 corresponds to the NMOS transistor 102. NMO
The S transistor 358 is the positive power supply 360, which corresponds to the positive power supply 103, and the PMOS transistor 104.
Corresponds to the PMOS transistor 359.

The gate of the PMOS transistor 104 and the gate of the PMOS transistor 359 are connected,
The PMOS transistors 104 and 359 form a current mirror relationship. Further, the gate of the PMOS transistor 359 and the drain of the PMOS transistor 359 are connected.

Further, the dummy side precharge enhancing current supply circuit 400 corresponds to the precharge enhancing current supply circuit 200. Regarding each element in the current supply circuit for strengthening precharge, the positive power supply 201 corresponds to the positive power supply 401, the PMOS transistor 202 corresponds to the PMOS transistor 402, and the NMOS.
The NMOS transistor 403 corresponds to the transistor 203.

Next, please refer to FIG. 2 and FIG. The dummy side precharge detection circuit 450 corresponds to the precharge detection circuit 300. For each element in the precharge detection circuit, the positive power source 45 corresponds to the positive power source 45.
1, the PMOS transistor 302 corresponds to the PMOS transistor 452, the NMOS diode 303 corresponds to the NMOS diode 453, and the NMOS transistor 304 corresponds to the NMO.
The S transistor 454 and the PMOS transistor 3
A PMOS transistor 455 corresponds to 05.

The gate of the PMOS transistor 452 is connected to the gates of the PMOS diode 352 and the PMOS transistor 356.
2, 352 and 356 form a current mirror relationship. The drain side of the PMOS transistor 455 is P
It is connected to the gate of the MOS transistor 402, and the PMO
The gate of the S transistor 455 is connected to the output terminal of the reference voltage value sending circuit 250 shown in FIG.

The operation when the circuit of the dummy memory array section 350 or the like is configured in this way will be described. The dummy memory transistor corresponding to the memory transistor selected on the memory array section 51 side is the dummy memory array section 35.
The sense operation of the selected dummy memory transistor selected from 0 is performed by the same operation as described above.
In this case, the PMOS transistor 35 provided on the dummy side
9 and the normal side PMOS transistor 104 have a current mirror relationship, a current several times as large as the current flowing through the PMOS transistor 359 is applied to the PMOS transistor 10.
Flowing through 4. Therefore, as described in the above-described first embodiment, the PMOS transistor 359 is a normal-side sense amplifier even when the normal-side memory array section 51 selects a memory transistor having a low ON resistance value. To reliably send an accurate detection output value.
The characteristic of the current flowing through the PMOS transistor 104 is preferably set to about 0.5 times the characteristic of the current flowing through the PMOS transistor 359.

The precharge detection circuit 450 detects the precharge time of the bit lines of the dummy memory array section 350, and the dummy side precharge enhancement current supply circuit 4
The operation of supplying a current from 00 to the dummy side bit line is the same as the operation in the normal side sense amplifier described above.

In the second embodiment, the positive power source 10
0, 103, etc. may be provided separately as described above, or the circuits may be connected so as to be shared.

Third Embodiment: In the first and second embodiments described above, the current appearing at the output of the sense amplifier is as shown in FIG.
In the case of, the intersection of the drain current characteristics of the PMOS transistor 9 and the NMOS transistor 10, and in the case of FIG. 2, the PMOS transistor 104 and the NMOS transistor 1
It is determined at the intersection of the drain current characteristics with 02, and the reference for judging "0" or "1" as data at the output part of the sense amplifier is not biased to "0" or "1". The drain current characteristic of the NMOS transistors 10 and 102, which serves as a reference for determining “0” or “1” as data at the output portion of the sense amplifier, is almost half the maximum current characteristic of the drain current characteristics of the PMOS transistors 9 and 104. As described above, in the detection amplification unit connected to the semiconductor memory 600 and the dummy detection amplification unit connected to the dummy semiconductor memory 601, the transistors forming each current mirror, for example, in the detection amplifier shown in FIG. PMOS transistor 3 and PMOS transistor 9, PMOS transistor 16 and PMOS transistor 22, NMOS The ratio of the size of the transistor 10 and NMOS transistor 23 has been adjusted.

Further, the dummy memory array sections 13 and 350 shown in FIGS. 1 and 4 are composed of only transistors having a low on-resistance value as described above. This is shown in FIG.
It is based on the premise that no leak current flows from the transistors having a high on-resistance value that form the memory array section 51 of the semiconductor memory 600 shown in FIG. 1. In the first and second embodiments, the transistor having a low on-resistance value is read. In this case, the size ratio of the transistors forming the current mirror is halved as described above so that the current characteristic of 1/2 of the current characteristic of the PMOS transistor 9 or the like due to the ON current becomes the current characteristic of the NMOS 10, for example. Had set.

However, in reality, the memory array section 51 is
In some cases, a voltage equal to or higher than the threshold voltage of the transistor having a high on-resistance value is applied to the gate of the transistor having a high on-resistance value. In such a case, a leak current flows from the transistor having a high on-resistance value. When such a leak current flows, as shown in FIG. 14, for example, the drain current characteristic 700 of the NMOS transistor 10
Is set to 1/2 of the drain current characteristic 701 of the PMOS transistor 9 when a memory transistor having a low on-resistance value is selected, for example, the PMOS when a memory transistor having a high on-resistance value is selected.
The drain current characteristic 702 of the transistor 9 approaches the current characteristic 700 as shown by the dotted line, and it may be difficult to determine “0” or “1” at the detector output section, resulting in an erroneous determination. Therefore, in order to further improve the detection accuracy, it is necessary to take the leak current into consideration, and the detection amplifier shown in the third embodiment improves the detection accuracy in consideration of the leak current. The configuration and operation of the third embodiment will be described below.

Incidentally, "low threshold value" and "high threshold value" described in the drawings and the like are synonymous with each other. The leak current means a current flowing through a memory transistor having a high ON resistance value, and the ON current means a current flowing through a memory transistor having a low ON resistance value. Further, in the following description, the case where the circuit of the third embodiment is applied to the first embodiment is taken as an example, but it is of course possible to apply it to the second embodiment.

FIG. 8 shows the outline of the configuration of the third embodiment. The same components as those shown in FIG. 1 are designated by the same reference numerals, and their explanations are omitted. To do. In this embodiment, the dummy semiconductor memory 60 shown in FIG.
Instead of 1, the reference current considering the leak current is NM
A comparison current generator 650 for supplying a current having a value to be applied to the gate of the OS 10 or 102 to the input section is connected. The specific circuit configuration of the comparison current generator 650 will be described below.

As an example of the comparison current generator 650, the circuit configuration shown in FIG. 9 can be considered. This circuit configuration is composed of dummy semiconductor memories 653 and 656 and a shunt circuit 661. The dummy semiconductor memory 653 has a dummy memory transistor array 651 having memory transistors having a low on-resistance value as shown in FIG. 1, and a dummy selection unit 652 of the dummy memory transistor array 651, and the output of the dummy selection unit 652. The side is connected to the "input section" of the dummy detection amplification section 662 shown in FIG.

The dummy semiconductor memory 656 has a dummy memory transistor array 654 having a memory transistor having a high on-resistance value, and a dummy selecting section 655 of the dummy memory transistor array 654, and the output side of the dummy selecting section 655 is the dummy. It is connected to the output side of the selection unit 652.

A concrete circuit configuration of the dummy memory transistor array 651 having memory transistors having a low on-resistance value in the dummy semiconductor memory 653 is shown in FIG. 10, and the memory transistors having a high on-resistance value in the dummy semiconductor memory 656 are shown. FIG. 11 shows a specific circuit configuration of the dummy memory transistor array 654 having the above. Figure 1
0 and the circuit configuration itself shown in FIG. 11 are not different from the circuit configuration in a general semiconductor memory, and therefore description thereof will be omitted, but in the figure, the transistor indicated by “M” indicates a transistor with a low threshold value. Transistors indicated by "C" indicate high threshold transistors.

Also, in FIG. 10 and FIG. 11, “A” is H
When (High), this memory block is selected,
When "C" is H, the memory data transistor region is selected, "B" is H, "D" is L (low), the memory transistor on the left side of the memory data transistor region in the figure is selected, and "B" is When L and "D" are H, the memory transistor on the right side of the drawing in the memory data transistor region is selected.

The shunt circuit 661 has the positive power supply 21, the PMOS transistor 16, and the NMOS which are obtained by removing the positive power supply 21 and the PMOS transistor 22 from the circuit configuration of the dummy detection amplification section 662 to which the dummy semiconductor memory 653 is connected.
A positive power supply 657, a PMOS transistor 658, an NMOS transistor 659, and an inverter 660, which have the same circuit configuration as the circuit including the transistor 17 and the inverter 18. Further, the shunt circuit 661 is used for the positive power supply 15 and the PMO in the dummy detection amplification section 662.
The dummy semiconductor memory 656 has an equivalent resistance value to the circuit including the S transistor 16, the NMOS transistor 17, and the inverter 18, and the output side of the dummy selection unit 655 of the dummy semiconductor memory 656 is NM.
It is connected to the source side of the OS transistor 659.

Thus, the comparison current generator 650 is
Dummy semiconductor memories 653 and 656 and shunt circuit 66
The operation in the case of being composed of 1 will be described below. The on-state current value of the low threshold memory transistor including the leakage current is i
₂ , the on-current value of the high-frequency memory transistor is i ₁ , the output current value of the comparison current generator 650 is i, and NM shown in FIG.
The saturation current appearing at the gate of the OS transistor 10 is Ir
If ef, then i = (ai ₁ + bi ₂ ) / (a + b). Note that a and b are arbitrary positive numbers.

The input-to-output ratio in the detection amplification section 662 shown in FIG. 8, that is, the current amplification rate is α, and the input-output ratio in the detection amplification section 663 shown in FIG. 8, that is, the current amplification rate is β, in FIG. It is assumed that the input-to-output ratio of the current mirror used as the load circuit 664, that is, the current amplification factor is γ, for example, α = β · γ, and that it is connected to the output part of the dummy detection amplification part 663. The current value appearing at the output of the load circuit is I ₁ with respect to the above current value i ₁ , and the above current value i ₂
Assuming that I ₂ is Iref = α · (ai ₁ + bi ₂ ) / (a + b) I ₁ = αi ₁ and I ₂ = αi ₂ , Iref = (aI ₁ + bI ₂ ) / (a + b) Become. The ratio α is, for example, in FIG.
The ratio β indicates how many times the current of the OS transistor 9 passes the current of the PMOS transistor 3, and the ratio β is a ratio indicating how many times the current of the PMOS transistor 22 passes the current of the PMOS transistor 16 in FIG. 8, for example. The ratio γ is, for example, in FIG. 8, a ratio that indicates how many times the current that the NMOS transistor 23 flows in the NMOS transistor 10.

In the above-mentioned case where the comparison current generator 650 is composed of the dummy semiconductor memories 653 and 656 and the shunt circuit 661, for example, the above a and b are set to approximately 1, and the above i ₂ is the output from the dummy semiconductor memory 653. I ₁ is an output current from the dummy semiconductor memory 656. Then, the sum of these output currents i ₁ + i ₂ is attenuated by the shunt circuit 661. In the present embodiment, as described above, the shunt circuit 661 is configured to have an equivalent resistance value to the dummy detection amplification unit 663 shown in FIG. 8, so the value of i ₁ + i ₂ is halved, and the value of Iref is halved. The value is a value corresponding to about 1/2 of the on-current value i ₂ of the low threshold memory transistor and the on-current value i ₁ of the high threshold memory transistor. As described above, in the present embodiment, the Iref value is determined in consideration of the leak current as well, so that more accurate detection can be performed.

In the above description, for example, the reference current value flowing through the NMOS ₁₀ is about ½ of the ON current value i ₂ of the low frequency memory transistor and the ON current value i ₁ of the high frequency memory transistor. Although the values are set to correspond to each other, the present invention is not limited to this. According to the configuration of the present embodiment, for example, the ratio of each current mirror, that is, the above-mentioned ratio α,
By changing β and γ, the reference current value is set to correspond to an arbitrary value between the ON current value i ₂ of the low frequency memory transistor and the ON current value i ₁ of the high frequency memory transistor. Can be set.

Further, in the present embodiment, the shunt circuit 661 is provided as described above to attenuate the values of i ₁ + i ₂ described above. Is adjusted to change the ratio of α: (β · γ) in the above α, β, γ. For example, the reference current value flowing through the NMOS transistor 10 is I ₂ corresponding to the ON current value of the low range memory transistor, and The value may be set to an intermediate value with I ₁ corresponding to the ON current value of the high frequency memory transistor.

Since the comparison current generator 650 having the above-mentioned structure makes the circuit scale a little larger,
As a configuration example of the comparison current generator 650, a configuration as shown in FIG. 12 or 13 can be adopted. These are the ones in which the structure of the dummy semiconductor memory is changed to control the leak current or the on-current itself sent from the dummy semiconductor memory array. That is, the dummy semiconductor memory normally has the structure shown in FIG. 10 or FIG.
In the case of the dummy semiconductor memory array shown in FIG. 0, the on-state current value is a memory transistor having a low threshold value, for example, memory transistors 665, 666, 6 connected in series in the block selector and memory data transistor area.
It is decided at 67. Therefore, as shown in FIG. 12, the low threshold memory transistors 668 to 671 are connected in parallel to the transistors forming the high threshold memory data transistor region.

It should be noted that the reason for connecting five memory transistors with low threshold values as shown in FIG. 12 is that the memory transistors with low threshold values connected in series in FIG.
5, 666, 667, the on-current value is sent from the dummy semiconductor memory array shown in FIG. 10 by setting the number of memory transistors with low threshold value connected in series to double the value. This is because it is about 1/2 of the on-current value.

With such a configuration, in this case, for example, in the above α, β, γ, α = β, γ = 1 should be set, but when the leak current is half or less of the memory-on current. As shown in FIG. 15, when there is no leak current, for example, the current characteristic 700 of the NMOS transistor 10 is located almost in the middle of the current characteristic 701. However, since the leak current actually exists, the above current characteristic is present. 700 is close to the current characteristic 702. However, by adding the leak current component as described above, the current characteristic 700 is changed to the current characteristic 703 indicated by the dotted line, so that it is possible to increase the margin for the proximity to the current characteristic 702. In other words, the Iref can be corrected so that the leak current value is added to the current characteristic 700.

Therefore, for example, the NMOS transistor 1
The reference current flowing through 0 should be a value in the direction of higher detection accuracy than the intermediate between I ₂ corresponding to the ON current value of the low threshold memory transistor and I ₁ corresponding to the ON current value of the high threshold memory transistor. Can be set to.

In the dummy semiconductor memory array shown in FIG. 12, the leak current is applied as it is. It may be configured to do so. With such a configuration, the same effect as in the case of the configuration shown in FIG. 12 can be obtained. In this case, the leak current does not have to be half or less of the on-current of the memory transistor.

The circuit configuration shown in FIG. 12 can be adopted only when the leak current value is less than half of the on-current value, but the on-current value in a normal memory transistor is about 250 microamperes. Since the leak current value is about 10 to 20 microamperes, the above condition is sufficiently satisfied. Therefore, providing the dummy semiconductor memory array shown in FIG. 12 and the like is very effective as a sense amplifier having a small circuit scale and high detection accuracy.

In the first to third embodiments described above, the conductivity type of each transistor, including the memory transistor, is not limited to that described above, and the P type and the N type are inverted in each transistor. It may be one that has been made.

[0121]

As described above in detail, according to the present invention, since the first transistor and the third transistor have the current mirror structure, the on-resistance value of the first transistor can be set low. It is possible to control the potential of the memory cell in a short time, and the access time to the memory transistor can be shortened. Further, according to the present invention, by providing the noise removing means, it is possible to prevent the output signal of the detection amplifier from being affected even if noise is input to the detection amplifier input section.

Furthermore, by providing the dummy detection amplification section and the current mirror structure of the ninth transistor and the tenth transistor, even if a memory transistor having a low ON resistance value is selected, the output of the detection amplifier is increased. It is possible to send a signal of a normal signal level from a part depending on the characteristics of the memory transistor depending on the manufacturing conditions.

Furthermore, according to the present invention, connection between the sixteenth transistor having the current mirror structure and the fifteenth transistor with respect to the fourteenth transistor acting as the load element of the thirteenth transistor having the current mirror structure with the eleventh transistor. Since the fifteenth transistor has a circuit connection which is not related to the precharge operation of the semiconductor memory means by adopting a circuit configuration in which the point is the output end of the sense amplifier, the channel lengths of the fourteenth, fifteenth transistor and sixteenth transistor are The constant current characteristics of these transistors can be set to be substantially constant. Therefore, it is possible to improve the current-to-voltage amplification factor in the detection amplifier that is determined by the current characteristics of the fifteenth transistor and the sixteenth transistor, and improve the detection accuracy of the output end potential of the semiconductor memory means.

Furthermore, the same dummy side detection amplifier as the structure described in claim 4 for detecting the output terminal potential of the dummy semiconductor memory means is connected to the normal side detection amplifier having the structure described in claim 4. Thus, even when the detection operation of the normal-side detection amplifier becomes unstable, the dummy-side detection amplifier can perform correction for the normal-side detection amplifier to operate normally.

Further, according to the present invention, when it is detected that the output side of the semiconductor memory means is in the precharged state, the precharge current is supplied from the precharge enhancing current supply means to the output side, whereby the semiconductor memory means is provided. It is possible to shorten the time required for precharging on the output side of, and to suppress the current value flowing through the thirteenth transistor and the like to be low, thereby reducing power consumption.

Furthermore, a dummy semiconductor memory means is provided,
Furthermore, by connecting the dummy-side detection amplifier loaded with the dummy-side precharge detection means and the precharge-enhancing current supply means to the normal-side detection amplifier having the configuration according to claim 6, the detection operation of the normal-side detection amplifier Even when the characteristics of the memory transistor differ depending on the manufacturing conditions, the dummy side detection amplifier can be corrected so that the normal side detection amplifier can operate normally.

Further, according to the present invention, the dummy semiconductor memory means generates a current having a current value between the maximum current value and the minimum current value of the detection target memory transistor selected by the semiconductor memory means. By using the comparison current generating means, the reference current flowing through the load means is the current corresponding to the maximum current value and the current corresponding to the minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. The value can be set to a current value between the values and the sense amplifier can normally perform the sensing operation even when a leak current flows from the memory transistor having a high on-resistance value.

Further, since the low resistance dummy semiconductor memory means, the high resistance dummy semiconductor memory means and the shunting means are provided as the comparison current generating means, the reference current flowing through the load means is the detection target memory transistor selected by the semiconductor memory means. It is possible to make the current value between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value out of the current values flowing by, and the leakage current from the memory transistor with a high ON resistance value. The sense amplifier can operate normally even when it flows.

According to the present invention, the load amplification means is configured so that the current amplification factor due to the current mirror structure in the detection amplification means is higher than the current amplification factor due to the current mirror structure of the dummy detection amplification means. Of the current value of the detection target memory transistor selected by the semiconductor memory means between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value. Therefore, the sense amplifier can operate normally even when a leak current flows from the memory transistor having a high on-resistance value.

Further, due to the existence of the leak current, the saturation current characteristic appearing at the gate of the ninth transistor, for example, approaches the current characteristic of the dummy semiconductor memory having a high threshold value. By providing a dummy semiconductor memory transistor having a low or high ON resistance value with an increased number of stages, the reference current is increased by the amount corresponding to the leakage current, and the current of the semiconductor memory having a low threshold value and the semiconductor memory having a high threshold value are provided. It can be set at a position approximately in the middle of the current characteristics of. In other words, it is possible to correct the saturation current characteristic so that the leakage current value is added to the saturation current characteristic.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a sense amplifier according to the present invention.

FIG. 2 is a circuit diagram showing a part of the configuration of the second embodiment of the sense amplifier of the present invention.

FIG. 3 is a circuit diagram showing a part of the configuration of the second embodiment of the sense amplifier of the present invention.

FIG. 4 is a circuit diagram showing a part of the configuration of the second embodiment of the sense amplifier of the present invention.

5 is an NMOS transistor 102 and P shown in FIG.
9 is a graph showing characteristics of the MOS transistor 104.

FIG. 6 is a graph showing current characteristics of a PMOS transistor and an NMOS transistor in a sense amplifier output section.

FIG. 7 shows a PMOS transistor 9 and an NMO shown in FIG.
5 is a graph showing current characteristics in the S diode 101.

FIG. 8 is a circuit diagram showing a configuration of a first embodiment of the sense amplifier of the present invention.

9 is a block diagram showing an example of comparison current generating means shown in FIG. 8. FIG.

10 is a circuit diagram showing an example of a dummy memory array of memory transistors having a low threshold value shown in FIG.

FIG. 11 is a circuit diagram showing an example of a dummy memory array of memory transistors having a low threshold value shown in FIG. 9.

12 is a circuit diagram showing an example of a dummy memory array showing another example of the comparison current generating means shown in FIG.

13 is a circuit diagram showing another example of a dummy memory array showing another example of the comparison current generating means shown in FIG.

FIG. 14 is a graph showing current characteristics when low-value and high-value memory transistors are selected and characteristics of a reference current flowing through the NMOS 10.

FIG. 15 is a graph showing current characteristics when low-value and high-value memory transistors are selected and characteristics of a reference current flowing through the NMOS 10.

FIG. 16 is a diagram showing a concept of an integrated circuit including a memory circuit unit.

FIG. 17 is a block diagram showing components for reading data from a memory circuit unit.

FIG. 18 is a circuit diagram showing a configuration of a conventional sense amplifier.

FIG. 19 is a circuit diagram showing a configuration example of a selection unit shown in FIG. 17 and the like.

FIG. 20 is a circuit diagram showing a configuration example of the memory array section shown in FIG. 17 and the like.

[Explanation of symbols]

2 ... Positive power supply, 3 ... PMOS diode, 4 ... NMOS transistor, 5 and 6 ... Inverter, 7 ... NMOS transistor, 8 ... Positive power supply, 9 ... PMOS transistor, 1
0 ... NMOS transistor, 11 ... Inverter, 12 ...
Dummy detection / amplification unit, 13 ... Dummy memory array unit, 14
... Dummy selection section, 23 ... NMOS transistor, 51 ...
Memory array section, 52 ... Selection section, 101 ... NMOS diode, 102 ... NMOS transistor, 104 ... PM
OS transistor, 200 ... Precharge enhancement current supply circuit, 250 ... Reference voltage value sending circuit, 300 ... Precharge detection circuit, 350 ... Dummy memory array, 400
… Dummy side pre-charge enhancement current supply circuit, 450…
Dummy-side precharge detection circuit, 650 ... Comparison current generator, 653 ... Dummy semiconductor memory for flowing maximum current, 6
56 ... Dummy semiconductor memory for passing minimum current, 661 ... Shunt circuit, 665 to 671 ... Memory transistors with low threshold.

Claims (11)

[Claims] 1. A first positive power supply (2) and a semiconductor memory means (6)
00) in series with the first positive power source (2) and having a low on-resistance, the first transistor (3), the first transistor (3) and the semiconductor memory means (6).
00) and a second transistor (4) connected in series to the first transistor (3) and connected to a negative feedback circuit having a first inverting element (5); and a second positive power supply (8). It is connected in series to the second positive power source (8) between the sense amplifier output section (11) and the first transistor.
Third transistor (9) with current mirror structure together with (3)
And a sense amplifier. 2. The output signal of the first inverting element (5) is the second output signal.
It has a fourth transistor (7) supplied to the gate via an inverting element (6) and is input to a sense amplifier input between the second transistor (4) and the semiconductor memory means (600). And a noise removing means (6, 7) for preventing a rise in the potential of the above-mentioned sense amplifier input section due to noise.
The sense amplifier according to claim 1. 3. A fifth transistor (16) having a low on-resistance value, which is connected in series to the third positive power source (15) between the third positive power source (15) and the dummy semiconductor memory means (601).
And a negative feedback circuit having a third inverting element (18) connected in series to the fifth transistor (16) between the fifth transistor (16) and the dummy semiconductor memory means (601). A seventh transistor connected in series with the sixth transistor (17) and the fourth positive power source (21) and forming a current mirror structure with the fifth transistor (16).
(22) and the output signal of the third inverting element (18) is the fourth inverting element (1
9) The eighth transistor (2
0) for preventing the potential rise of the input section due to the noise inputted to the input section between the sixth transistor (17) and the dummy semiconductor memory means (601) ( 19, 20), the third transistor (9) and the seventh transistor
The sense amplifier according to claim 1 or 2, further comprising: an output signal stabilizing section in which a ninth and tenth transistor (10, 23) connected in series to (22) has a current mirror structure. 4. A fifth positive power supply (100) and semiconductor memory means
(600) is connected in series to the fifth positive power source and has an 11th transistor (3) having a low ON resistance value; the 11th transistor and the semiconductor memory means (60).
0) and is connected in series to the eleventh transistor,
First to which a negative feedback circuit having a fifth inverting element (5) is connected
Two transistors (4), a thirteenth transistor (9) connected in series to the fifth positive power supply between the fifth positive power supply and ground, and forming a current mirror structure with the eleventh transistor, and the thirteenth transistor. First connected to ground
A fourth transistor (101), a sixth positive power source (103), and a fifteenth transistor (10) connected in series to the sixth positive power source between the sense amplifier output section.
4) and a sixteenth transistor (102) connected between the sense amplifier output section and the ground and forming a current mirror structure with the fourteenth transistor, the sense amplifier. 5. A seventeenth transistor (35) having a low on-resistance value, which is connected in series to the seventh positive power source between the seventh positive power source (355) and the dummy semiconductor memory means (601).
2), the seventeenth transistor and the dummy semiconductor memory means
Between the seventeenth transistor and the seventeenth transistor connected in series to the seventeenth transistor and connected to the negative feedback circuit having the sixth inverting element (354), and between the seventh positive power source and the ground. A nineteenth transistor (356) connected in series to the seventh positive power source and forming a current mirror structure with the seventeenth transistor, and a second transistor connected between the nineteenth transistor and ground.
0 transistor (357), the eighth positive power supply (360) and the sense amplifier output section are connected in series to the eighth positive power supply, and the twenty-first transistor (35) forming a current mirror structure with the fifteenth transistor.
9. The sense amplifier according to claim 4, further comprising 9), and a 22nd transistor (358) connected between the output of the sense amplifier and ground and forming a current mirror structure with the 20th transistor. 6. A dummy current transistor, which has the same structure as the memory transistor constituting the semiconductor memory means and is in an ON state, is connected, and a reference current value that is a predetermined multiple of the current value that can flow through the dummy memory transistor is detected. For connecting the reference voltage value transmitting means (250), the gates of the eleventh transistor and the thirteenth transistor, and the output side of the reference voltage value transmitting means are connected, and the current value flowing through the eleventh transistor and the reference current value. Of the precharge detection means (300) for detecting the precharge state in the semiconductor memory means in which the value of the current flowing through the eleventh transistor is equal to or greater than the reference current value, and the precharge detection means. The output side is connected, and the semiconductor memory means is connected by the precharge detection means. A precharge-enhancing current supply unit (200) for supplying a current in addition to the current flowing through the eleventh transistor between the eleventh transistor and the semiconductor memory unit when it is detected that the recharge state is present. The sense amplifier according to claim 4 or 5. 7. A seventeenth transistor (35) having a low on-resistance value, which is connected in series to the seventh positive power source between the seventh positive power source (355) and the dummy semiconductor memory means (601).
2) is connected in series to the 17th transistor between the 17th transistor and the dummy semiconductor memory means,
First connected to a negative feedback circuit having an inverting element (354)
An eight-transistor (353), a nineteenth transistor (356) connected in series to the seventh positive power supply between the seventh positive power supply and ground, and forming a current mirror structure with the seventeenth transistor, and the nineteenth transistor. Second connected to ground
A 0th transistor (357), an eighth positive power supply (360) connected in series, and a 21st transistor (359) forming a current mirror structure with the 15th transistor; and a 21st transistor connected between the 21st transistor and ground. A twenty-second transistor forming a current mirror structure with the twentieth transistor
The transistor (358) is connected to the gates of the seventeenth transistor and the nineteenth transistor and the output side of the reference voltage value sending means, and the current value flowing through the seventeenth transistor and the nineteenth transistor and the reference current value are connected to each other. By comparing, the second precharge detecting means (450) for detecting the precharge state in the dummy semiconductor memory means, in which the value of the current flowing through the seventeenth transistor and the nineteenth transistor is equal to or more than the reference current value, When the output side of the second precharge detecting means is connected and the second precharge detecting means detects that the dummy semiconductor memory means is in the precharge state,
7. The detection circuit according to claim 6, further comprising: second precharge enhancing current supplying means (400) for flowing a current in addition to the current flowing through the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means. amplifier. 8. A detecting and amplifying means having a current mirror structure, the input side of which is connected to the output side of the semiconductor memory means (600) to detect the current value sent by the detection target memory transistor in the semiconductor memory means ( 66
2) and the input side is connected to the output side of the dummy semiconductor memory means simulating the semiconductor memory means, and has a current mirror structure for detecting the current value sent by the dummy memory transistor in the dummy semiconductor memory means. A control to which the dummy detection amplification means (663), the load terminal connected to the input side of the detection output means (11) connected to the output side of the detection amplification means, and the output end of the dummy detection amplification means are connected. A load means (664) having a current input terminal and flowing a reference current for determining the current value sent from the detection output means in relation to the current value on the output side of the detection amplification means.
And a dummy semiconductor memory means, wherein the dummy semiconductor memory means has a current value between a maximum current value and a minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. A sense amplifier, which is a comparison current generating means (650) for generating a current having a current value. 9. The comparison current generating means includes a dummy semiconductor memory array having a low on-resistance value, and a low resistance dummy semiconductor memory means (653) connected to an input side of the dummy detecting and amplifying means, and a high resistance dummy semiconductor memory means (653). A dummy semiconductor memory array having an ON resistance value, and a high resistance dummy semiconductor memory means (656) connected in parallel with an output side of the low resistance dummy semiconductor memory means to an input side of the dummy detection amplification means; A shunting means (661) having an equivalent resistance value that is the same as that of the dummy detection amplification means, and an input side of which is connected to an output side of the high resistance and low resistance dummy semiconductor memory means connected in parallel. The sense amplifier according to claim 8. 10. A detection amplification means having a current mirror structure, the input side of which is connected to the output side of the semiconductor memory means (600) and which detects the current value sent by the detection target memory transistor in the semiconductor memory means ( 66
2) and the input side is connected to the output side of the dummy semiconductor memory means simulating the semiconductor memory means, and has a current mirror structure for detecting the current value sent by the dummy memory transistor in the dummy semiconductor memory means. A control to which the dummy detection amplification means (663), the load terminal connected to the input side of the detection output means (11) connected to the output side of the detection amplification means, and the output end of the dummy detection amplification means are connected. A load means (664) having a current input terminal and flowing a reference current for determining the current value sent from the detection output means in relation to the current value on the output side of the detection amplification means.
And the dummy semiconductor memory means has a dummy semiconductor memory array having a low ON resistance value, a low resistance dummy semiconductor memory means (653) connected to the input side of the dummy detection amplification means, and a high ON resistance value. And a high resistance dummy semiconductor memory means (656) connected in parallel to the output side of the low resistance dummy semiconductor memory means and to the input side of the dummy detecting and amplifying means, Comparing current generating means (650) for generating a current having a current value between the maximum current value and the minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. In the amplifier, the current amplification factor due to the current mirror structure of the detection amplification means (662) corresponds to the current mirror structure of the dummy detection amplification means. The sense amplifier is characterized in that it is larger than the current amplification factor. 11. The comparison current generating means reaches a ground having a number of series connection stages which is equal to or more than the number of series connection stages of memory transistors in a current path leading to ground of a semiconductor memory array included in the semiconductor memory means. A semiconductor memory transistor that forms a current path and has a low on-resistance value, and a ground that is equal to or more than the number of series-connected memory transistors in the current path to the ground of the semiconductor memory array included in the semiconductor memory means. 11. The sense amplifier according to claim 8, further comprising a semiconductor memory transistor having a high on-resistance value, which forms a current path to the semiconductor memory array and is connected in parallel to the semiconductor memory array.