JPH06162775A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To ideally and automatically set the timing of the equalizing operation by providing an equalization timing control circuit and controlling the timing of a bit line equalizing signal in accordance with the change of a word line driving signal. CONSTITUTION:In the period of a chip enable signal CE at a low level, an equalizing pulse generating circuit 37 is controlled by an internal chip enable signal DO due to a dummy row decoder 42 and a dummy wiring 55 of the timing control circuit, and a word line driving signal WORD is outputted by a word line driver circuit 18. Therefore, the operation timing of the bit line equalizing signal is controlled corresponding to the rise timing of the change of the signal WORD. Consequently, the bit line equalizing signal is ideally and automatically controlled corresponding to the signal WORD when the operation timing of the bit line equalizing signal is made a certain fixed time ealier than the rise of the signal WORD, and the access time is shortened dependently of the memory capacity even in the case of a capacity variable memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device of a method of precharging and equalizing a bit line and then sense-amplifying a bit line potential when reading data.

[0002]

2. Description of the Related Art FIG. 5 is a CMOS type SRAM (static random access memory) which is an example of a synchronous semiconductor memory device for precharging and equalizing bit lines of a memory cell array using a synchronous clock signal.
3 is a circuit diagram showing a part of FIG. In FIG. 5, SR
AM cells (only one of which is shown as a representative) 12 are arranged in a matrix to form a memory cell array.

Reference numerals 11 and / 11 denote bit lines commonly connected to the other ends of the pair of data transfer transistors 16 and 17 of the SRAM cells 12 in the same column in the memory cell array, and are complementary to each other. Only one pair is shown as a representative.

Reference numeral 13 is a word line commonly connected to the gates of the data transfer transistors 16 and 17 of the SRAM cells 12 in the same row in the memory cell array, and only one word line is shown as a representative.

19 is connected to the bit line pair 11 and / 11,
It is an equalizer circuit which receives an equalize signal EQ which will be described later and precharges the bit line pair 11 and / 11 to a predetermined potential for a predetermined period to equalize each potential. A sense amplifier 25 senses and amplifies the potential difference between the pair of bit lines. Reference numeral 26 is a data output buffer which buffer-amplifies the output of the sense amplifier 25. 27 is a CE input buffer composed of an inverter that inverts the chip enable signal CE input for controlling the active / inactive state of the SRAM chip.

Reference numeral 28 denotes / CE from the CE input buffer 27.
Row address signal input in synchronization with the signal, for example, A0, A
1 is decoded and word line selection signals R0, R1, R2,
A row decoder that generates R3.

The row decoder 28 receives the address signal inputs A0 and A1 correspondingly, and inverts the respective address signal inputs A0 and / A1 to generate internal address signals / A0 and / A1. A0 and / A1 are input correspondingly, inverter circuits 35 and 36 for re-inverting each to generate an internal address signal, and two internal address signals and a / CE signal which are different in combination are input 3 It has input NAND circuits 29, 30, 31, 32.

Reference numerals 51 to 54 are NAND circuits of the row decoder 28.
29, 30, 31, 32 output signal lines (word line selection signal lines),
C0, C1, C2, and C3 are word line selection signal lines 51 to
54 wiring capacitance.

Reference numeral 18 corresponds to the word line selection signals from the word line selection signal lines 51 to 54 of the row decoder 28,
A word line driver circuit, for example, an inverter, which outputs the word line drive signal WORD and supplies it to the corresponding word line, and only one is shown as a representative.

37 is the / CE from the CE input buffer 27
A signal is input, and the equalize signal EQ is synchronized with this.
Is an equalizing pulse generating circuit for generating and supplying the same to the equalizing circuit 19. Here, an outline of the operation of the SRAM of FIG. 5 will be described.

Before the data is read, the bit line pair 11, / 11 are precharged / equalized for a predetermined time in synchronization with the CE signal input. In addition, the address signals A0 and A1 are decoded in synchronization with the CE signal input, and the specific word line 13
Selected and the SRAM connected to this word line 13
Cell 12 is selected. When the precharge / equalization is completed, the selected SRAM cell is
A potential difference occurs between the bit line pair 11 and / 11 according to the data of 12.

By the way, ASIC (application-specific IC)
In such fields, a variable memory capacity type that can arbitrarily change the memory capacity is often required. Said SRAM
Is a variable memory capacity type in which the memory capacity can be changed, the number of bits and the number of word lines of the memory cell array change. That is, the length of the bit line pair 11, / 11 of the memory cell array changes according to the number of memory cells used.

Along with this, the load capacitance of the row decoder 28 (wiring capacitance of the word line selection signal lines 51 to 54) changes, so that the word line drive signal WO after the CE signal is input.
The time it takes for RD to turn on changes.

On the other hand, the equalize signal EQ is set to the ON state at a constant timing synchronized with the input of the chip enable signal CE regardless of the change of the memory capacity, and the word line drive signal is set even in the maximum memory capacity configuration. It is necessary to set the off state at a certain timing that is later than the timing when WORD rises. FIG. 6 shows the SRAM of FIG.
FIG. 6 is a timing waveform chart showing an example of a data read operation when the memory capacity of is an intermediate value within a variable range. FIG. 7 is a timing waveform chart showing an example of the data read operation when the memory capacity of the SRAM of FIG. 5 is the maximum value within the variable range. FIG. 8 shows the SRA of FIG.
FIG. 11 is a timing waveform chart showing an example of a data read operation when the memory capacity of M is the minimum value within the variable range. Next, referring to FIGS. 6 to 8, the SR of FIG.
An example of AM operation will be described in detail.

First, as the row address signals A0 and A1, for example, a low level "L" is input. When the CE signal input becomes "L" level (ground potential VSS), the equalize signal EQ becomes high level "H" (power supply potential VCC) in synchronization with the / CE signal from the CE input buffer 27 and a little later than this. . As a result, the equalizer circuit 19 is turned on, the bit line pair 11 and / 11 are precharged to a predetermined potential, and equalized to the same level.

Further, / C from the CE input buffer 27
The row address signals A0 and A1 are decoded by the row decoder 28 in synchronization with the E signal, for example, the word line selection signal R0 output from the NAND circuit 29 becomes "L" level, and the word of the word line driver circuit 18 at the subsequent stage The line drive signal WORD becomes "H" level, and the word line 13 is selected. After that, when the equalize signal EQ returns to "L" level,
The equalizing circuit 19 is turned off, and the bit line pair 11, /
11. Equalize operation is canceled.

Then, the complementary data in the SRAM cell 12 connected to the selected word line 13 is transferred to the bit line pair.
11 and / 11, a potential difference is generated between the bit line potentials BT and / BT, the potential difference is sense-amplified by the sense amplifier 25, and the output of the sense amplifier 25 is output buffer circuit.
It is output as read data OUT via 26. After that, the CE signal input returns to the “H” level, and the next operation is awaited.

As can be seen from the operation example shown in FIG. 8, when the memory capacity of the SRAM of FIG. 5 is small, the word line drive signal WORD is input after the chip enable signal CE is input.
Rises earlier than the corresponding timing in the maximum configuration of the memory capacity shown in FIG. On the other hand, the timing at which the equalize signal EQ shown in FIG. 8 is turned off is a constant timing like the corresponding timing in the maximum configuration of the memory capacity shown in FIG.

Therefore, in the SRAM of FIG. 5, even when the memory capacity is small, the access time is the same as in the maximum memory capacity configuration, and the access time becomes slower than the original performance.

[0020]

As described above, when the conventional synchronous semiconductor memory device is applied to a memory of variable memory capacity, the timing at which the word line drive signal rises during the data read operation is the memory capacity. However, the timing of turning off the equalizing operation of the bit line is set to a constant timing that is later than the rising timing of the word line driving signal even in the maximum memory capacity configuration. There is a problem that the access time becomes slower than the original performance when the memory capacity is small.

The present invention has been made to solve the above problems, and ideally automatically sets the timing of the equalizing operation of the bit line in the data reading operation in accordance with the rising timing of the word line drive signal. An object of the present invention is to provide a semiconductor memory device capable of shortening the access time depending on the memory capacity even when applied to a memory of variable memory capacity type.

[0022]

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells are arranged in a matrix, and a word line commonly connected to memory cells in the same row in the memory cell array. Commonly connected to the memory cells in the same column in the memory cell array,
To form a pair with a first bit line from which a signal having a potential corresponding to data stored in a memory cell is read, and to compare the read potential when reading data stored in the memory cell A second bit line to which a signal serving as a reference potential of the bit line pair is provided, an equalize signal generation circuit that generates an equalize signal of a constant time width based on a clock signal, and the bit line pair before receiving data by receiving the equalize signal. Is precharged / equalized to a predetermined potential, a row decoder that decodes a row address signal in synchronization with the clock signal to generate a word line selection signal, and a word line selection signal of this row decoder A word line drive circuit that inputs via a signal line and outputs a word line drive signal for driving the word line, and a data line drive circuit. A sense amplifier that senses and amplifies the potential difference between the bit line pair at the time of data read, and an equalize timing control circuit that controls the timing of the equalize signal at the time of data read corresponding to the timing of change of the word line drive signal. It is characterized by doing.

[0023]

Since the equalizing timing control circuit is provided, the timing of the bit line equalizing signal at the time of data reading is automatically controlled in accordance with the timing of the change of the word line driving signal.

Thus, the start of the equalizing operation of the bit line can be set at a timing which is earlier than the rise of the word line driving signal by a predetermined time, and ideally the ending of the equalizing operation can be completed after a required equalizing operation period.

Therefore, even when it is applied to a memory of variable memory capacity, the timing of the equalizing operation of the bit lines ideally changes depending on the memory capacity, and the access time can be shortened depending on the memory capacity. Will be possible.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a part of a synchronous CMOS SRAM as an embodiment of the semiconductor memory device of the present invention.

This SRAM has a memory cell array in which memory cells are arranged in a matrix, a word line commonly connected to memory cells in the same row in the memory cell array, and memory cells in the same column in the memory cell array. A first bit line that is commonly connected and from which a signal of a potential corresponding to the storage data of the memory cell is read, and a pair of the first bit line and the first bit line, which is read when reading the storage data of the memory cell A second bit line to which a signal serving as a reference potential for comparison with the potential is applied (read from the memory cell); and an equalizing circuit for precharging and equalizing the bit line pair to a predetermined potential before reading data. A row decoder that decodes a row address signal in synchronization with a clock signal and selectively controls the word line, and a row decoder A sense amplifier that senses and amplifies the potential difference between the bit line pair at the time of data read, and an equalize timing control circuit that controls the timing of the equalize signal at the time of data read corresponding to the timing of change of the word line drive signal. To have.

That is, in FIG. 1, SRAM cells (only one of which is representatively shown) 12 are arranged in a matrix to form a memory cell array. The SRAM cell 12 includes a flip-flop circuit in which two inverters 14 and 15 are cross-connected, and a pair of data transfer transistors each having one end connected to a pair of data storage nodes of the flip-flop circuit. It consists of 16 and 17.

Complementary bit lines 11 and / 11 (only one pair is shown as a representative) are provided as a pair of data transfer transistors 16 of SRAM cells 12 in the same column in the memory cell array.
The other ends of 17 are commonly connected.

Word line 13 (typically only one is shown)
SRAM cells 12 in the same row in the memory cell array
Are commonly connected to the gates of the data transfer transistors 16 and 17.

The equalizing circuit 19 includes the bit line pair 11,
It is connected to / 11 and receives an internal equalize signal EQ described later to precharge the bit line pair 11 and / 11 to a predetermined potential for a predetermined period to equalize the respective potentials. The sense amplifier 25 sense-amplifies the potential difference between the potentials BT and / BT of the bit line pair 11 and / 11. The data output buffer 26 buffer-amplifies the output of the sense amplifier 25. The CE input buffer 27 has S
The input of the chip enable signal CE for controlling the active / inactive state of the RAM chip is inverted and is composed of an inverter.

The row decoder 28 is the CE input buffer.
Row address signal input in synchronization with / CE signal from 27,
For example, the word line selection signal R0 is decoded by decoding A0 and A1.
~ R3 is generated.

The row decoder 28 receives the address signal inputs A0 and A1 correspondingly and inverts the respective address signal inputs A0 and / A1 to generate internal address signals / A0 and / A1. A0 and / A1 are input correspondingly, and inverter circuits 35 and 36 which re-invert each to generate an internal address signal and two internal address signals and the / CE signal which are different in combination are input 3 It has input NAND circuits (unit decoders) 29-32. 51 to 54 are output signal lines (word line selection signal lines) of the NAND circuits 29 to 32 of the row decoder 28, and C0 to C3 are wiring capacitances of the word line selection signal lines 51 to 54.

The word line driver circuit 18 (only one is shown as a representative) receives corresponding word line selection signals R0 to R3 from the word line selection signal lines 51 to 54, and outputs the word line drive signal WORD. It is output and supplied to the corresponding word line, and is composed of, for example, an inverter.

Further, the timing of the equalize signal EQ at the time of reading data is set to the word line drive signal.
A dummy row decoder 42 and a dummy wiring 55 are provided in order to control the timing of WORD change and to control the equalizing operation period of the equalizing circuit 19.

The dummy row decoder 42 is a 3-input NAND circuit having the same structure as the NAND circuit (unit decoder) group of the row decoder 28 and the same driving capability.
The / C from the CE input buffer 27 is connected to one of its input terminals.
When the E signal is input and the other two input terminals are supplied with the VCC potential, the / CE signal is inverted and the internal CE signal is inverted.
Generate signal D0.

The dummy wiring 55 is connected to the output side of the dummy row decoder 42 and the wiring capacitances C0 to C3 of the word line selection signal lines 51 to 54 on the row decoder output side.
It has a wiring capacitance C4 equivalent to that of the above and transmits an internal CE signal to the equalizing pulse generating circuit 37.

The equalizing pulse generating circuit 37 receives the internal CE signal that has passed through the dummy wiring 55 of the NAND circuit, and in synchronism with this, generates the equalizing signal EQ for a certain period of time and supplies it to the equalizing circuit 19. , And odd-numbered inverter circuits 38, 39, 40 and a 2-input AND circuit 41. A column selection transistor for selecting a column line of the memory cell array and a column decoder for controlling the column selection transistor are not shown. Next, the data read operation of the SRAM will be described with reference to FIGS. FIG. 2 shows the SRA of FIG.
FIG. 11 is a timing waveform chart showing an example of a data read operation when the memory capacity of M is an intermediate value within a variable range. FIG. 3 is a timing waveform chart showing an example of the data read operation when the memory capacity of the SRAM of FIG. 1 is the maximum value within the variable range. FIG. 4 shows the SR of FIG.
FIG. 9 is a timing waveform chart showing an example of a data read operation when the AM memory capacity is the minimum value within a variable range.

The data read operation of the SRAM is basically the same as the operation of the conventional SRAM (FIG. 5) described above with reference to FIGS. 6 to 8, but a circuit for controlling the equalizing timing is added. As a result, the following operation is performed.

That is, the output signal of the dummy row decoder 42 (internal CE signal D0) is the wiring capacitance C4 of the dummy wiring 55.
However, the output signal of the row decoder 28 (word line selection signal) is also delayed by the wiring capacitances C0 to C3 of the word line selection signal lines 51 to 54 on the row decoder output side.

As a result, the rise timing of the equalize signal EQ generated by the equalizer circuit 19 in response to the internal CE signal D0 is determined by the word line drive signal WORD generated by the word line drive circuit 18 in response to the word line selection signal. It will automatically change according to the rising timing of.

Therefore, it is possible to ideally set the start of the equalizing operation of the bit line at a timing which is earlier than the rise of the word line drive signal WORD by a predetermined time and end the equalizing operation after a required equalizing operation period.

As a result, even when it is applied to a memory of variable memory capacity, the timing of the equalizing operation of the bit line pair 11, / 11 changes ideally depending on the memory capacity, and the access time depends on the memory capacity. It becomes possible to shorten it.

Although the SRAM is shown in the above embodiment, the present invention is not limited to this, and the first bit line from which the signal of the potential corresponding to the data stored in the memory cell is read out, and the first bit line. And a semiconductor memory (for example, a read-only memory; ROM) having a second bit line from which a signal serving as a reference potential for reading the stored data of the memory cell is read from the dummy cell. ) And so on.

[0045]

As described above, according to the semiconductor memory device of the present invention, it is possible to ideally automatically set the timing of the equalizing operation of the bit line in the data reading operation in accordance with the rising timing of the word line drive signal. Therefore, even when applied to a memory of variable memory capacity, the access time can be shortened depending on the memory capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of an SRAM according to an embodiment of the present invention.

2 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 1 is an intermediate value within a variable range.

3 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 1 is the maximum value within a variable range.

4 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 1 is a minimum value within a variable range.

FIG. 5 is a circuit diagram showing a part of a conventional mask ROM.

6 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 5 is an intermediate value within a variable range.

FIG. 7 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 5 is the maximum value within the variable range.

8 is a timing waveform chart showing an example of a data read operation when the memory capacity of the SARM of FIG. 5 is the minimum value within a variable range.

[Explanation of symbols]

11, / 11 ... Bit line pair, 12 ... SRAM cell, 13 ... Word line, 16, 17 ... Data transfer transistor, 18 ... Word line driver circuit, 19 ... Equalize circuit, 25 ... Sense amplifier, 26 ... Data output buffer , 27 ... CE input buffer,
28 ... Row decoder, 29, 30, 31, 32 ... 3-input NAND circuit, 33-36 ... Inverter circuit, 37 ... Equalize pulse generation circuit, 42 ... Dummy row decoder, 51-54 ... Word line selection signal line, 55 ... Dummy wiring, R0, R1, R2, R3 ...
Row decoder output signal (word line selection signal), C0,
C1, C2, C3 ... Wiring capacitance of word line selection signal line, C
4 ... Wiring capacitance of dummy wiring, D0 ... Output signal of dummy row decoder (internal CE signal).

Claims (2)

[Claims] 1. A memory cell array in which memory cells are arranged in a matrix, a word line commonly connected to memory cells in the same row in the memory cell array, and a memory cell in the same column in the memory cell array. A bit line connected to a bit line from which a signal having a potential corresponding to the stored data of the memory cell is read, and a pair of the bit line and the first bit line, for comparing with the read potential when reading the stored data of the memory cell A second bit line to which a signal serving as a reference potential is applied, an equalizing signal generating circuit that generates an equalizing signal having a constant time width based on a clock signal, and the bit line pair before receiving data by receiving the equalizing signal. And a row address synchronized with the clock signal. A row decoder that decodes a signal and generates a word line selection signal, and a word line selection signal of this row decoder is input through a word line selection signal line, and a word line drive signal for driving the word line is output. A word line drive circuit, a sense amplifier that senses and amplifies the potential difference between the bit line pairs during data read, and an equalize that controls the timing of the equalize signal during data read in accordance with the timing of change in the word line drive signal. A semiconductor memory device comprising a timing control circuit. 2. The semiconductor memory device according to claim 1, wherein the equalize timing control circuit has the same configuration and drive capability as a unit decoder in the row decoder, and a dummy row decoder to which the clock signal input is input, A dummy wiring which is connected to the output side of the dummy row decoder, has the same wiring capacity as the word line selection signal line on the row decoder output side, and transmits the dummy row decoder output signal to the equalizing pulse generation circuit. A semiconductor memory device comprising: