JPH06153096A - Ccd solid state imaging device - Google Patents

Abstract

PURPOSE:To suppress an output potential fluctuation owing to the non-matching of a back-gate effect in a drive side transistor and a load side transistor without causing terminal number increase, the increase of part item by connection with an external circuit, the deterioration of a frequency characteristic, etc. CONSTITUTION:The power source of a low output impedance which is constituted of an emitter follower circuit 41 by an NPN transistor Q5 and an emitter resistor R3 is inserted between a substrate bias terminal phiVsub and a GND terminal. A bias circuit 42 by bias resistors R1 and R2 is inserted between a power source terminal phiVDD and the GND terminal. Moreover, the gates and sources of the load side MOS transistors Q3 and Q4 in respective source follower circuits SF1 and SF2 are connected to a contact (a) between the emitter and the emitter resistor R3 of the NPN transistor Q5 in the emitter follower circuit 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state image pickup device, and more particularly to an external signal processing system for amplifying an image pickup signal from a CCD solid-state image pickup device body formed inside a CCD solid-state image pickup device (chip). The structure of the output buffer to output to

[0002]

2. Description of the Related Art Generally, as shown in FIG. 6, a CCD solid-state image pickup device comprises a CCD solid-state image pickup device main body 101 and an output buffer 102 formed in one chip CH. The output buffer is usually composed of 2-3 stages of source follower circuits. The example shown is
Two-stage configuration, that is, first and second source follower circuits SF
An example in which the output buffer 102 is composed of 1 and SF2 is shown.

The specific connection relationship of each circuit will be described with reference to the drawing. In the first source follower circuit SF1, the drive side MOS transistor Q1 and the load side (constant current side) MOS transistor Q3 are connected in series. The second source follower circuit SF2 is connected to the drive side MOS transistor Q2 and the load side (constant current side) M.
The OS transistor Q4 is configured to be connected in series.

Then, the first source follower circuit SF1
The image pickup signal Si from the CCD solid-state image pickup device main body 101 is supplied to the gate of the second source follower circuit SF2, and the contact potential of the first source follower circuit SF1 (potential of the connection point of the transistors Q1 and Q3) is supplied to the gate of the second source follower circuit SF2. Wiring is provided so as to be supplied. Further, the contact of the second source follower circuit SF2 (connection point of the transistors Q2 and Q4) is connected to the output terminal φout, and the contact potential can be taken out as the output signal Sv.

The gates and sources of the source follower circuits SF1 and SF2 are connected to the GND terminal so as to be fixed to the ground potential, and the drains of the source follower circuits SF1 and SF2 are connected to the power supply terminal. φV
It is connected to DD so that the power supply voltage VDD is supplied to the drain. The substrate potential Vsub and the electronic shutter pulse Ps are supplied via the substrate bias terminal φVsub.

[0006]

However, in the conventional CCD solid-state image pickup device, the drive side transistors Q1 and Q2 and the load side transistors Q3 and Q are used.
Since the back gate effect is different between 4 and 4, there is a problem that the output potential (the level of the output signal Sv) changes when the electronic shutter pulse Ps is applied.

That is, based on past research, many C's manufactured in recent years for reducing the dark current and realizing the electronic shutter operation.
The CD solid-state image pickup device employs a P-type well region and an N-type embedded channel on an N-type silicon substrate, and therefore, each M of the output buffer 102 of the CCD solid-state image pickup device.
The OS transistors Q1 to Q4 also employ a P-type well region and a surface N-type channel (depletion type) on an N-type silicon substrate. The electronic shutter operation is performed by applying the shutter pulse Ps to the silicon substrate. Since the electronic shutter operation itself is not directly related to this example, its description is omitted.

Generally, a depletion type MOS
It is well known that when the shutter pulse Ps is applied to the substrate of the transistor, the back gate effect modulates the potential of the channel of the MOS transistor.

Here, the drive side MOS transistor Q1 of each of the source follower circuits SF1 and SF2 shown in FIG.
And Q2, and load side MOS transistors Q3 and Q4
How the back gate effect is received will be described based on the potential distribution chart of FIG. In the potential distribution diagram of FIG. 8, the drive-side MOS transistor Q is shown in FIG.
1 and Q2 show the potential distribution just below the gate, and FIG. 9B shows the potential distribution just below the gate of the load side MOS transistors Q3 and Q4.

First, as shown in FIG. 8A, since the MOS transistors Q1 and Q2 on the drive side have high source and drain potentials, the P-type well region immediately below the surface N-type channel is depleted. Therefore, the drive-side MOS transistors Q1 and Q2 have a form in which the surface N-type channel and the N-type substrate are directly coupled by the parasitic capacitance Cg. Therefore, the substrate potential (substrate potential Psu
Due to the change of b), the channel potential PCH and the potential PPW of the P-type well region are modulated. That is, the drive-side MOS transistors Q1 and Q2 have a structure that easily receives the back gate effect from the substrate.

On the other hand, since the sources of the load-side MOS transistors Q3 and Q4 are connected to the GND terminal and are grounded, the P-type well region under the surface N-type channel is not completely depleted, and the P-type well region is not depleted. In the well region, the neutral region NPW fixed at the ground potential remains. Therefore, the potential change of the substrate is absorbed in the P-type well region. That is, the load-side MOS transistors Q3 and Q4 have a structure that is less susceptible to the back gate effect from the substrate.

Therefore, in the circuit configuration shown in FIG. 6, as shown in FIG. 9A, the shutter pulse P for the electronic shutter is applied to the substrate.
When s is applied, drive side MOS transistor Q
In 1 and Q2, since the modulation of the channel potential PCH due to the back gate effect from the substrate is large, the output potential (potential of the output terminal φout) is changed by the shutter pulse Ps as shown in FIG. 9B.

When the potential fluctuation is larger than the signal change amount of the image pickup signal component, the input dynamic range of the external signal processing system which receives the output signal Sv of the CCD solid state image pickup device is set to the original output of the CCD solid state image pickup device. There is a disadvantage that the signal Sv must be set wider than the required range.

Therefore, a circuit configuration as shown in FIG. 7 has been considered. That is, the source terminal φs and the DC input terminal φDC are newly set as the external terminals of the chip CH. The sources of the load side MOS transistors Q3 and Q4 are connected to the source terminal φs, and the load side M
The gates of the OS transistors Q3 and Q4 are connected to the DC input terminal φDC, and a resistor R is provided between the source terminal φs and GND outside the CCD solid-state image sensor CH.
circuit 10 in which s and capacitor Cs are connected in parallel to each other
3 is to be inserted.

The inserted capacitor Cs grounds the sources of the load-side MOS transistors Q3 and Q4 in an AC manner, and the voltage drop of the inserted resistor Rs causes the source potentials of the load-side MOS transistors Q3 and Q4. Can be raised, and the P-type well region immediately below the gate can be depleted.

Therefore, in this circuit configuration, the load side M
Since the OS transistors Q3 and Q4 are also susceptible to the back gate effect similarly to the drive side MOS transistors Q1 and Q2, it is caused by the mismatch of the back gate effect between the drive side MOS transistors Q1 and Q2 and the load side MOS transistors Q3 and Q4. It is possible to suppress the fluctuation of the output potential to be small.

However, in this case, there are the following problems. That is, in order to ground the sources of the load-side MOS transistors Q3 and Q4 in AC, a large-capacity capacitor is required as the capacitor Cs of the external circuit 103 to be inserted. Therefore, the large-capacity capacitor Cs cannot be formed inside the CCD solid-state image pickup element CH, and FIG.
As shown in, it is necessary to connect the circuit 103 to the outside of the CCD solid-state imaging device (chip) CH. Therefore,
As a terminal of the CCD solid-state image sensor, at least a terminal φs for taking out the source is newly required, and the resistance R
s and the external electronic parts of the capacitor Cs increase, which is a disadvantage.

As another solution, in the circuit configuration of FIG. 6, as shown in FIG. 10, a neutral region N is formed in the P-type well regions of the drive side MOS transistors Q1 and Q2.
PW is provided, and load side MOS transistors Q3 and Q4
Drive side MOS transistors Q1 and Q2
However, a method of suppressing the output potential fluctuation due to the back gate effect from the substrate can be considered by making it difficult to receive the back gate effect.

However, in this case, there are the following drawbacks. That is, comparing FIGS. 8A and 10 shows that the length of the depletion layer from the channel to the substrate side is significantly different. In FIG. 8A, the depletion layer reaches the deep portion of the substrate and the length of the depletion layer is long. Therefore, the parasitic capacitance Cga attached to the channel by this depletion layer is small.

On the other hand, in FIG. 10, the depletion layer is P
Since it is terminated in the well region, the length of the depletion layer is shortened, and the depletion layer increases the parasitic capacitance Cgc attached to the channel. As a result,
The method of FIG. 10 has a new drawback that the frequency characteristic is deteriorated due to the parasitic capacitance Cgc attached to the drive-side MOS transistors Q1 and Q2.

The present invention has been made in view of the above problems, and its object is to achieve the above-mentioned drawback, that is, C.
After overcoming the increase in the number of terminals provided in the CD solid-state image sensor, the increase in the number of parts due to the connection of external circuits, and the deterioration of the frequency characteristics, the back gate effect mismatch between the drive-side MOS transistor and the load-side MOS transistor It is an object of the present invention to provide a CCD solid-state image sensor capable of suppressing output potential fluctuations due to the characteristics.

[0022]

The present invention is directed to a photoelectric conversion section S.
And a CCD having a charge transfer unit VR (HR). The CCD solid-state image sensor has an output buffer 2 for amplifying an image pickup signal Si from the main body 1, and the output buffer 2 is composed of multi-stage source follower circuits SF1 and SF2. In the solid-state imaging device, a low-impedance power supply 41 is provided inside the CCD solid-state imaging device (chip CH), and the sources of the transistors Q3 and Q4 constituting the constant current sources of the source follower circuits SF1 and SF2 are connected to the power supply 41. Constitute.

In this case, the low impedance power source 4 is used.
1, a bipolar transistor Q5 can be used.

[0024]

In the CCD solid-state image sensor according to the present invention,
Since the sources of the transistors Q3 and Q4 on the load side, which are the constant current sources of the source follower circuits SF1 and SF2, are connected to the low-impedance power supply 41, the sources of the transistors Q3 and Q4 are AC-wise. Can be considered to be grounded. Therefore, a large-capacity capacitor for grounding the sources of the transistors Q3 and Q4 in an alternating current is not necessary, and a terminal for extracting the sources of the transistors Q3 and Q4 to the outside is also unnecessary.

Further, since the power source 41 raises the potentials of the sources of the load side transistors Q3 and Q4, it is possible to deplete the transistors Q3 and Q4 directly under the gates thereof, and the source follower circuits SF1 and SF2 are depleted. Like the transistors Q1 and Q2 on the drive side, the structure is likely to be affected by the back gate effect. Therefore, drive side transistors Q1 and Q
2 can reduce the output potential fluctuation due to the mismatch of the back gate effect between the load side transistors Q3 and Q4.

Further, since the depletion layer formed immediately below the gates of the load side transistors Q3 and Q4 reaches the deep portion of the substrate and the depletion layer length becomes long, the parasitic capacitance attached to the channel can be suppressed to a small value, and the frequency characteristic can be suppressed. It does not cause deterioration.

[0027]

Embodiments of the CCD solid-state image pickup device according to the present invention will be described below with reference to FIGS.

The CCD solid-state image sensor according to this embodiment is
As shown in FIG. 1, a CCD solid-state image sensor body 1 and an output buffer 2 are formed in one chip CH.

As shown in FIG. 3, in the CCD solid-state image pickup device main body 1, a large number of photoelectric conversion parts (generally called light receiving parts) S composed of pn junctions are arranged in rows (vertical direction) and columns. The image pickup area 3 is formed by arranging in the matrix direction in the direction (horizontal direction), and the vertical transfer registers VR by CCD common to the light receiving sections S arranged in the row direction are arranged in the column direction.

Further, in the lower part of the drawing of the image pickup area 3, a horizontal transfer register HR by a CCD is formed. A charge-voltage conversion unit (output unit) 4 having, for example, a floating diffusion is formed at one end of the horizontal transfer register HR.

First, the charge accumulation period (exposure period)
, The signal charges corresponding to the amount of light incident from the subject are accumulated in the light receiving section S, and during the read period, the light receiving section S
The signal charges stored in the vertical transfer register VR are transferred to the vertical transfer register VR, and in the horizontal blanking period, the signal charges are sequentially transferred to the horizontal transfer register HR side row by row.

The signal charges transferred to the horizontal transfer register HR are sequentially transferred to the output section 4 side in the horizontal scanning period after the horizontal blanking period. Then, after the signal charges transferred to the output unit 4 are sequentially converted into voltage signals, the image pickup signal Sv according to the incident amount of light from the subject can be taken out from the output terminal φout via the output buffer 2.

The sectional structure in the depth direction of the light receiving portion S in this CCD solid state image pickup device is as shown in FIG.
For example, the P-type well region 12 is formed on the surface of the N-type substrate 11, and the N-type light receiving portion S is formed on the surface of the well region 12. A P-type hole accumulation region 13 is usually formed on the surface of the light receiving portion S. Further, in the lateral direction of the light receiving portion S, an N-type vertical transfer register VR and a P-type channel stopper region 15 are formed via a P-type region 14 forming a read gate.

Below the vertical transfer register VR, a P-type impurity diffusion region 16 for preventing the smear component from entering is formed. Then, on the vertical transfer register VR,
A transfer electrode 18 made of, for example, a polycide layer is selectively formed via the gate insulating film 17, and an Al light-shielding film 20 is formed on the transfer electrode 18 via an interlayer film 19.

The Al light-shielding film 20 is selectively etched and removed on the light receiving portion S, and the light L is
The light is incident on the light receiving portion S through the opening 21 formed by this etching removal.

The output buffer 2 is usually 2 to
It is composed of a three-stage source follower circuit. Figure 1
The structure of a typical output buffer 2 is shown in FIG. The illustrated example shows a two-stage configuration, that is, an example in which the output buffer 2 is configured by the first and second source follower circuits SF1 and SF2. In the figure, the portion indicated by the broken line is CC
This is a portion of the D solid-state image pickup element (chip) CH.

The specific connection relationship between the circuits SF1 and SF2 will be described with reference to the figure. The first source follower circuit SF1 is composed of a drive side MOS transistor Q1 and a load side (constant current side) MOS transistor Q3. Are connected in series to form a second source follower circuit SF2.
Is composed of a drive side MOS transistor Q2 and a load side (constant current side) MOS transistor Q4 connected in series. The drains of the drive-side MOS transistors Q1 and Q2 are connected to the power supply terminal φVDD.

Each of the MOS transistors Q1 to Q4 is shown in FIG.
As shown in the cross-sectional view of FIG. 3, a source region 31S and a drain region 31D which are formed on the surface of the P-type well region 12 and are made of a high concentration N-type impurity diffusion region,
1S and a drain region 31D, and a gate electrode 32 made of, for example, a polycide layer formed on the channel region 31C via a gate insulating film 17 made of SiO ₂ , for example, and a low concentration N-type impurity diffusion is made in the channel region 31C. A region is formed to form a so-called surface N-type channel (depletion type) MOS transistor.

Then, the source region 3 of the gate insulating film 17 is formed.
The opening 31 is provided at a position corresponding to the 1S and the drain region 31D.
a is formed, and the source electrode 33S and the drain electrode 33D made of an Al layer are formed through the opening 31a. The P-type well region 12 is connected to GND through a high-concentration P-type impurity diffusion region (takeout region) 34 and fixed at the ground potential.

Then, the first source follower circuit SF1
The image pickup signal S from the CCD solid-state image pickup device body 1 is applied to the gate of
i is supplied, and wiring is provided so that the contact potential of the first source follower circuit SF1 (potential at the connection point of the transistors Q1 and Q3) is supplied to the gate of the second source follower circuit SF2. Further, the contact of the second source follower circuit SF2 (connection point of the transistors Q2 and Q4) is connected to the output terminal φout, and the contact potential can be taken out as the output signal Sv.

In this CCD solid-state image pickup device CH, a low output impedance power supply composed of an emitter follower circuit 41 composed of an NPN transistor Q5 and an emitter resistor R3 is inserted between the substrate bias terminal φVsub and the GND terminal. , Power supply terminal φVDD and GND
Bias circuit 4 for the NPN transistor, which is constructed by connecting bias resistors R1 and R2 in series between terminals.
2 is further inserted, and at the contact point a between the emitter of the NPN transistor Q5 and the emitter resistor R3 in the emitter follower circuit 41, the load side MOS transistors Q3 and Q in the source follower circuits SF1 and SF2 are inserted.
4 is configured by connecting the gate and the source.

Next, the operation of the output buffer 2 will be described. First, since the sources of the load-side MOS transistors Q3 and Q4 are connected to the low-impedance power supply (emitter follower circuit) 41, the sources can be regarded as being grounded in terms of AC. Therefore, a large-capacity capacitor for grounding the sources of the transistors Q3 and Q4 in an alternating current is not necessary, and moreover,
Terminals for taking out the sources of the transistors Q3 and Q4 to the outside are also unnecessary.

Further, as the midpoint potential of the bias resistors R1 and R2 rises, the source potentials of the load side MOS transistors Q3 and Q4 rise, which causes the P-type well region 12 immediately below the gates of the transistors Q3 and Q4.
Will be depleted. Therefore, the load-side MOS transistors Q3 and Q4 are also susceptible to the back gate effect similarly to the drive-side MOS transistors Q1 and Q2, so that the back-gates of the drive-side MOS transistors Q1 and Q2 and the load-side MOS transistors Q3 and Q4 are reduced. It is possible to reduce the fluctuation of the output potential (the fluctuation of the level of the output signal Sv) due to the mismatch of the effects.

Further, in this state, the P-type well region 12 immediately below the gates of the drive-side MOS transistors Q1 and Q2 and the load-side transistors Q3 and Q4 are both depleted, so that the depletion layer immediately below the gate reaches the deep portion of the substrate. ,
Since the parasitic capacitance attached to the channel can be suppressed to a small level, the frequency characteristics will not be deteriorated.

As described above, according to the CCD solid-state image pickup device CH of this embodiment, a low-impedance power supply (emitter follower circuit) 41 is provided inside the CCD solid-state image pickup device (chip) CH, particularly in the preceding stage of the output buffer 2. And the load side MOS transistor Q3 is connected to the power supply 41.
, And the sources of Q4 are connected, without connecting an external circuit to the sources of the load-side MOS transistors Q3 and Q4, and without newly providing a source extraction terminal in the CCD solid-state image sensor CH. Board 1
The output potential fluctuation due to the back gate effect from 1 can be suppressed.

Moreover, in the CCD solid-state image pickup device CH, as described below, the low-impedance power supply (emitter follower circuit) 41 is provided without adding a new process step to the manufacturing process of the CCD solid-state image pickup device CH. And the bias circuit 42 can be added.

That is, the two bias resistors R1 and R2 that constitute the bias circuit 42 are the same as the protective resistors actually formed inside the CCD solid-state image sensor CH in FIG.
For example, the transfer electrode 18 and the gate electrode 3 shown in FIG.
In addition to 2, it can be formed of a polycide layer.

As shown in FIG. 5, the NPN transistor Q5 is a P-type transistor which forms a collector region 51C formed of the N-type substrate 11 and a base region 51B formed on the surface of the collector region 51C. The well region 12,
The emitter region 51E is formed of an N-type impurity diffusion region formed in the base region 51B. In the collector region 51C, the base region 51B, and the emitter region 51E, the high-concentration regions 52 for extraction are respectively provided.
C, 52B and 52E are formed. Then, the insulating film 17 made of SiO 2 is formed on the N-type substrate 11, and further,
The high-concentration region 52 for each extraction in the insulating film 17
Apertures 53 are formed at locations corresponding to C, 52B, and 52E, respectively, and collector electrodes 54C, base electrodes 54B, and emitter electrodes 54E made of an Al layer are formed through these apertures 53.

The base region 51B can be formed simultaneously with the formation of the P-type well region 12 shown in FIGS. 2 and 4, and the emitter region 51E is formed in the vertical transfer register VR (and FIG. 3) shown in FIG. Horizontal transfer register H
It can be formed simultaneously with R). Further, the high-concentration region 52C for taking out the collector and the high-concentration region 52E for taking out the emitter are respectively the source region 3 shown in FIG.
1S and the drain region 31D can be formed at the same time, and the high-concentration region 52B for taking out the base can be formed at the same time as the contact region 34 of the P-type well region 12 shown in FIG. The collector electrode 54C, the base electrode 54B, and the emitter electrode 54E made of an Al layer are the Al light-shielding film 20 shown in FIG. 4 and the source electrode 3 shown in FIG. 2, respectively.
It can be formed simultaneously with 3S and the drain electrode 33D.

In the present embodiment, the source follower circuits SF1 and SF2 having a two-stage structure have been taken as an example of the output buffer 2. However, the number of stages may be one or three or more.

[0051]

As described above, according to the CCD solid-state image pickup device of the present invention, a low-impedance power source is provided inside the CCD solid-state image pickup device, and the power source of the transistor constituting the constant current source of the source follower circuit is provided. Since the source is connected, the back side of the drive side MOS transistor and the load side MOS transistor does not increase without increasing the number of terminals for the CCD solid-state image sensor, the number of parts due to the connection of the external circuit, and the deterioration of frequency characteristics. It is possible to suppress the output potential fluctuation due to the mismatch of the gate effect.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a configuration of a main part of an embodiment of a CCD solid-state image pickup device according to the present invention, in particular, an output buffer.

FIG. 2 is a cross-sectional view showing a configuration of a MOS transistor that constitutes an output buffer of the CCD solid-state imaging device according to the present embodiment.

FIG. 3 is a plan view showing a schematic configuration of a CCD solid-state image sensor according to the present embodiment.

FIG. 4 is a cross-sectional view showing a configuration around a light receiving portion of the CCD solid-state imaging device according to the present embodiment.

FIG. 5 is a cross-sectional view showing a configuration of an NPN transistor that constitutes a low impedance power source in the CCD solid-state imaging device according to the present embodiment.

FIG. 6 is an equivalent circuit diagram showing a configuration of a main part of a CCD solid-state imaging device according to a conventional example, particularly an output buffer.

FIG. 7 is a main part of a CCD solid-state imaging device according to another conventional example,
In particular, it is an equivalent circuit diagram showing a configuration of an output buffer.

FIG. 8 is a potential distribution diagram showing a potential just under a gate of a MOS transistor forming an output buffer according to a conventional example, FIG. 8A shows a potential distribution of a drive-side MOS transistor, and FIG. 8B shows a load-side MO transistor.
The potential distribution of an S transistor is shown.

FIG. 9 is a pulse waveform diagram showing a change in output potential due to application of a shutter pulse.

FIG. 10 is a potential distribution diagram showing the potential in the case where a neutral region is formed in the P-type well region just below the gate in the drive side MOS transistor.

[Explanation of symbols]

 CH chip 1 CCD solid-state image sensor main body 2 output buffer 3 imaging area 4 output section SF1 first source follower circuit SF2 second source follower circuit Q1, Q2 drive side MOS transistor Q3, Q4 load side MOS transistor Q5 NPN transistor R1, R2 Bias resistance R3 Emitter resistance 41 Emitter follower circuit (low impedance power supply) 42 Bias circuit

Claims (2)

[Claims] 1. A CCD having a photoelectric conversion section and a charge transfer section.
A CCD solid-state image pickup device having an output buffer for amplifying an image pickup signal from the solid-state image pickup device main body, and the output buffer having a multistage source follower circuit, wherein a low-impedance power source is provided inside the CCD solid-state image pickup device. A CCD solid-state image pickup device characterized in that the source of a transistor constituting a constant current source of the source follower circuit is connected to the power source. 2. A CCD solid-state image pickup device, wherein the low-impedance power supply is configured by using a bipolar transistor.