JPH06140890A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To set delay quantity at a proper value by means of a lift by permitting the delay quantity of a delay circuit with variable delay quantity by constituting in a manner of being changeable by means of a control register. CONSTITUTION:At first, control bits are written in the control register 37 in accordance with a program within a semiconductor integrated circuit 1 or a program from an outside. The control bits are respectively provided corresponding to the delay circuits 33, 34, 35 and 36 and the written control bits control the delay quantity of the delay circuits 33, 34, 35 and 36 separately through respective control lines 38, 39, 40 and 41. Thus, proper delay quantity is obtained so that the semiconductor integrated circuit dispensing with logic revision for corresponding to noise pulse width and port output permission capacity which are different at every system in a wide range is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 1 is a schematic configuration diagram showing an example of the configuration of a conventional semiconductor integrated circuit having a delay circuit. The semiconductor integrated circuit 1 has an input terminal 2 and an output terminal 6,
Input circuit 3 having a delay circuit 7, a signal processing circuit 4 having second and third delay circuits 8 and 9, and an output circuit 5 having a fourth delay circuit 10. And
The signal input to the input terminal 2 is input to the input circuit 3,
It is input to the signal processing circuit 4 via the input circuit 3. The signal processed by the signal processing circuit 4 is output to the output terminal 6 via the output circuit 5.

FIG. 2 is a block diagram showing an example of the delay circuits 7, 8, 9, and 10. The input terminal 11 is connected to the output terminal 14 via a series circuit of a first inverter 12 and a second inverter 13. FIG. 3 is a block diagram showing an example of the input circuit 3 including the delay circuit 7, which is generally known as a noise canceller. The input terminal 15 is connected to the input side of the first inverter 16 and one input terminal of the NAND circuit 18, and the output side of the inverter 16 is the second inverter.
It is connected to the other input terminal of the NAND circuit 18 via 17. NAND
The output terminal of the circuit 18 is connected to the output terminal 20 via the third inverter 19. Here, the inverters 16 and 17 are the delay circuits described above.

FIG. 4 shows an output circuit 5 using a delay circuit 10.
FIG. 4 is a block diagram showing an example of the above, which is used for reducing power supply noise when the port outputs of a microcomputer (not shown) are at H level at the same time. The first input terminal 21 to which the first signal generated inside the microcomputer is input is connected to one input terminal of the first NAND circuit 22, and the other input terminal is the output timing signal input terminal 30 of the port output. And the input terminal of the first inverter 31. The output terminal of the NAND circuit 22 is connected to the gate of a P-type MOS transistor 24 provided between the power supply 23 and the first port output terminal 25. Second input terminal 26 to which the second signal generated inside the microcomputer is input
Is connected to one input terminal of the second NAND circuit 27.

The output terminal of the inverter 31 is connected to the other input terminal of the NAND circuit 27 via the second inverter 32. NA
The output terminal of the ND circuit 27 is the power supply 23 and the second port output terminal.
It is connected to the gate of a P-type MOS transistor 28 which is interposed between the gate and the gate 29. Note that a plurality of similar circuits are formed according to the number of ports. Here, the first and second inverters 31 and 32 are the delay circuits described above.

Next, the operation will be described. Although the signal input to the input terminal 2 in FIG. 1 is received by the input circuit 3, noise is removed by the delay circuit 7 of the input circuit 3 shown in FIG. Here, the operation of the input circuit 3 will be described. When the input terminal 15 is at the L level, both the one input terminal and the other input terminal of the NAND circuit 18 are at the L level, so that the output terminal 20 is at the L level. Next, input terminal 15 is L
When transitioning from the level to the H level, one input terminal of the NAND circuit 18 connected to the input terminal 15 becomes the H level almost at the same time, but the other input terminal of the NAND circuit 18 becomes the H level because the inverter 16, It is delayed by the delay time caused by 17.

If the input terminal 15 changes from the H level to the L level before the other input terminal of the NAND circuit 18 becomes the H level, the output of the NAND circuit 18 remains at the H level and does not change. In other words, in this delay circuit, inverters 16,1
Do not accept H level signals that are less than the delay time due to 7.
Normally, this delay time is set larger than the pulse width of noise generated in the system used, and the delay amount is adjusted by changing the number of inverter stages.

Next, the signal received by the input circuit 3 is sent to the signal processing circuit 4 and subjected to signal processing according to the purpose. The signal processing circuit 4 is usually divided into a plurality of processing blocks and often processed in synchronization with a clock. In this case, as the scale of the signal processing circuit 4 increases, it becomes necessary to adjust the clock skew (clock shift). A delay circuit is used as one of the means for this adjustment.

The signal processed by the signal processing circuit 4 is output to the output terminal 6 at a predetermined timing by the output circuit 5.
Is output from. However, since the drive current of the output driver in the output circuit 5 is large and noise is likely to occur, a delay circuit may be used to reduce the noise. An example of the port output of the microcomputer will be described with reference to FIG.
First, when an output command to the port is executed by the microcomputer, an L level or H level signal is input from the first input terminal 21 to one input terminal of the NAND circuit 22 and from the second input terminal 26 to the NAND circuit. Input to 27 input terminals respectively.

Next, the port output timing signal from the control unit in the microcomputer is input to the port output timing signal input terminal 30. Since the port output timing signal input terminal 30 is directly connected to the other input terminal of the NAND circuit 22, a signal is output from the first port output terminal 2 at substantially the same timing as the port output timing signal. On the other hand, since the signal of the timing signal input terminal 30 is input to the other input terminal of the second NAND circuit 27 via the inverters 31 and 32, the inverter 31 outputs from the second port output terminal 29 based on the port output timing signal. The signal is output after a delay amount of 32.

Usually, when the port output transits from the off state to the on state or from the on state to the off state, pulse-like noise is generated in the power supply line due to the parasitic inductance of the power supply line. Depending on the magnitude of this noise, a delay circuit is provided. Malfunctions. The magnitude of this noise increases in proportion to the output current value of the ports and the number of ports that change at the same time. Therefore, by shifting the time points at which signals are output from the port output terminals 25 and 29 by the delay circuit in this way, the number of ports that output signals at the same time is reduced and power supply noise is reduced.

FIG. 5 is an equivalent circuit diagram of the inverter 12 (13) in the delay circuit shown in FIG. The input terminal 11 is connected to the output terminal 14 via the switch 70. The switch 70 selectively selects the resistor 76 connected to the power source 71 and the resistor 78 connected to the ground potential 72. Output terminal 14 and ground potential
A capacity 79 is interposed between the two and 72. Here, the resistor 76 is an equivalent resistance in the ON state of the P-type MOS transistor forming the inverter, and the resistor 78 is an equivalent resistance in the ON state of the N-type MOS transistor forming the inverter. The switch 70 selects the resistor 78 when the voltage of the input terminal 11 is higher than the input threshold voltage of the inverter, and selects the resistor 76 when the voltage is low. The capacitance 79 is the sum of the output capacitance of the inverter, the output wiring capacitance, and the input capacitance of the next-stage circuit connected to the output terminal 14.

Next, in this equivalent circuit, the resistance value of the resistor 76 is R786, the resistance value of the resistor 78 is R78, and the capacitance value of the capacitor 79 is C7.
The operation of the delay circuit will be described below. First, from the state where the input terminal 11 is at L level and the output terminal 14 is at H level,
Switch to the H level, the switch 70 selects the resistor 78, so that the output terminal 14 transits from the H level to the L level after a time of the time constant R78 × C79. On the other hand, when the input terminal 11 is at H level and the output terminal 14 is at L level,
When 11 transits to the L level, the switch 70 selects the resistor 76, and the output terminal 14 becomes the L after the time according to the time constant R76 × C79.
Transition from level to H level. Usually, the delay amount of the inverter is determined by finding the optimum value of the resistors 76 and 78 by circuit simulation or the like. In this way, the delay circuit can be designed with the circuit shown in FIG.

[0014]

However, increasing the above-mentioned noise cancellation amount and port output delay amount causes an increase in input signal setup time and output delay time, which lowers the performance of the semiconductor integrated circuit. The amount of delay cannot be unnecessarily increased in order to deal with all the systems used. However, in the conventional semiconductor integrated circuit using the delay circuit, the logic is fixed as described above, and the delay amount cannot be changed once manufactured, so the noise cancellation amount and the port output noise reduction for each system. Revision of the logic is necessary to get the quantity. Further, there is a problem that the logic needs to be revised to adjust the clock skew as the circuit scale of the semiconductor integrated circuit increases. In view of such a problem, it is an object of the present invention to provide a semiconductor integrated circuit capable of logically setting a delay amount to an appropriate value by software.

[0015]

A semiconductor integrated circuit according to a first aspect of the present invention has a structure in which a delay amount of a delay circuit having a variable delay amount can be changed by a control register. The semiconductor integrated circuit according to the second aspect of the invention has a configuration in which a plurality of delay circuits having different delay amounts can be selectively selected by the selection circuit to change the delay amount.

[0016]

In the first aspect of the present invention, the delay amount is changed when the delay circuit whose delay amount is variable is controlled by the control register. This eliminates the need to revise the logic for optimizing the delay amount. In the second invention, the delay amount is changed by selectively selecting a plurality of delay circuits having different delay amounts by the selection circuit. This eliminates the need for revision of the logic that optimizes the delay amount.

[0017]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 6 is a block diagram showing a main configuration of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 includes an input circuit 3 including a first delay circuit 33 having a variable delay amount, a signal processing circuit 4 including a second delay circuit 34 and a third delay circuit 35 having a variable delay amount, and a delay circuit. Fourth delay circuit 36 with variable amount
And the control register 37 for changing the delay amounts of the delay circuits 33, 34, 35 and 36. The input terminal 2 is connected to the input side of the signal processing circuit 4 via the input circuit 3. The output side of the signal processing circuit 4 is connected to the output terminal 6 via the output circuit 5. The control register 37 includes control lines 38, 39, 40, 41 for controlling the delay circuits 33, 34, 35, 36 individually.
It is connected to the delay circuits 33, 34, 35, 36 via.

FIG. 7 is a block diagram showing the configuration of an example of a delay circuit whose delay amount can be changed. The input terminal 42 is the first
It is connected to one input terminal of the NAND circuit 43 and one input terminal of the second NAND circuit 44. The control terminal 49 is connected to the other input terminal of the NAND circuit 43 via the first inverter 50, and also directly.
It is connected to the other input terminal of the NAND circuit 44. The output terminal of the NAND circuit 43 is connected to one input terminal of the NOR circuit 47. The output terminal of the NAND circuit 44 is connected to the other input terminal of the NOR circuit 47 through the series circuit of the first and second inverters 45 and 46,
The output terminal of the circuit 47 is connected to the output terminal 48.

FIG. 8 is a block diagram showing a configuration in which the delay circuit shown in FIG. 2 is applied to a noise canceller. The input terminal 51 includes a first NAND circuit 52, a second NAND circuit 53, and a third NAND circuit 53.
It is connected to each one input terminal of the NAND circuit 57. The control terminal 60 is connected via the inverter 61 to the other input terminal of the NAND circuit 52 and directly to the other input terminal of the NAND circuit 53. NAND circuit
The output terminal of 52 is connected to one input terminal of the NOR circuit 56.
The output terminal of the NAND circuit 53 is connected to the other input terminal of the NOR circuit 56 via the series circuit of the inverter 54 and the inverter 55. The output terminal of the NOR circuit 56 is connected to the other input terminal of the NAND circuit 57, and the output terminal thereof is connected to the output terminal 59 via the inverter 58.

Next, the operation of the semiconductor integrated circuit thus configured will be described. First, a control bit is written in the control register 37 according to a program from inside the semiconductor integrated circuit 1 or from the outside. Control bits are delay circuits 33, 34, 3
The control bits written in the delay circuit 3 are provided via the control lines 38, 39, 40 and 41, respectively.
Controls the amount of delay of 3,34,35,36.

Each of the delay circuits 33, 34, 35 and 36 is as shown in FIG. 7, and the control lines 38, 39, 40 and 41 are the delay circuits 33, 34, 35 and.
It is connected to 36 control terminals 49 separately. Therefore, when the control terminal 49 is at the L level, it will pass through the inverter 50 and NA
One input terminal of the ND circuit 43 becomes H level, while the other input terminal of the NAND circuit 44 becomes L level. Therefore, the signal from the input terminal 42 is output from the output terminal 48 via the NAND circuit 43 and the NAND circuit 47. Here, when the NAND circuits 43 and 44 have the same delay characteristics, the total delay amount increases by the delay amount of the inverters 45 and 46 when the control register 37 is at the H level.

For example, in the case of the noise canceller shown in FIG. 8, the noise cancellation amount is the sum of the delay amounts of the NAND circuit 52 and the NOR circuit 56 when the control terminal 60 is at the L level, and the control terminal 60 is at the H level. When, the NAND circuit 5
3. The sum of the delay amounts of the inverters 54 and 55 and the NOR circuit 56 can be changed respectively. Therefore, by configuring as described above, the change of the delay amount of the delay circuit provided in the semiconductor integrated circuit can be controlled by software.

FIG. 9 is a block diagram showing another structure of the delay circuit. The input terminal 113 has one end of a parallel circuit of a P-type MOS transistor (hereinafter referred to as a transistor) 115 and an N-type MOS transistor (hereinafter referred to as a transistor) 116 that constitute one delay circuit section via an inverter 114, and the other delay circuit section. Is connected to one end of a parallel circuit of a P-type MOS transistor (hereinafter referred to as transistor) 117 and an N-type MOS transistor (hereinafter referred to as transistor) 118, and the other end of each parallel circuit is connected to an output terminal via an inverter 119.
Connected with 120. The control terminal 121 is connected to the respective gates of the transistor 115 and the transistor 118, and the transistor 116 and the transistor 11 are connected via the inverter 122.
Connected with each of the 7 gates.

Here, the transistors 115 and 117 have the same gate width, the transistor 117 has a longer gate length, and the transistors 116 and 118 have the same gate width and the transistor 118 has a longer gate length. There is.

Next, the operation of this delay circuit will be described. When the control terminal 121 is at the L level, the gate of the transistor 115 is at the L level and the gate of the transistor 116 is the inverter.
It becomes H level by inversion by 122, and transistor 1
Both 15 and transistor 116 turn on. On the other hand, the gate of the transistor 117 is at H level, and the transistor 118
The gate of the transistor becomes L level, and the transistors 117 and 118 are both turned off. On the contrary, when the control terminal 121 is at the H level, the transistors 115 and 116 are both turned off, and the transistors 117 and 118 are both turned on. That is, when the control terminal 121 is at the L level, the signal input to the input terminal 113 is output to the output terminal 120 via the inverter 114, the transistors 115, 116 and the inverter 119, and when the control terminal 121 is at the H level, The signal input to the input terminal 113 is output to the inverter 114 and the transistors 117 and 11
8 and output to the output terminal 120 via the inverter 119.

FIG. 10 is an equivalent circuit diagram of the delay circuit from the input terminal 113 to the input terminal of the inverter 119 in FIG. Input terminal 113 is connected to switch 125 and switch 133.
And a resistor 128 or 129 through a series circuit
Connected to the input terminal 131 of 119. The switch 125 selects the resistor 124 connected to the power supply 111 or the resistor 126 connected to the ground potential 112. A capacitance 127 is interposed between the input terminal of the switch 133 and the ground potential 112. The resistor 128 or the resistor 129 is selected by the switch 133 according to the signal from the control terminal 121. A capacitor 130 is interposed between the input terminal 131 of the inverter and the ground potential 112. Resistance 124,12
6 is the equivalent resistance of the P-type MOS transistor forming the inverter 114 in the ON state and the equivalent resistance of the N-type MOS transistor in the ON state.

The capacitance 27 is the sum of the output capacitance of the inverter 114, the output wiring capacitance, and the input capacitance of the transistors 115, 116, 117, 118 connected to the inverter 114. The resistor 128 is an equivalent resistance that the transistors 115 and 116 are on,
129 is an equivalent resistance when the transistors 117 and 118 are in an ON state, and a capacitance 130 is a sum of output capacitances of the transistors 115, 116, 117 and 118, wiring capacitances and input capacitances of the inverter 119. When the control terminal 121 is at L level, the switch 13
3 switches to select the resistor 128 and the resistor 129 at the H level.

In this equivalent circuit, since the transistor 117 has a larger gate length than the transistor 115 and the transistor 118 has a larger gate length than the transistor 116 as described above, the resistance value of the resistor 129 is larger than that of the resistor 128. large. Therefore, the resistance 128
The time constant becomes larger and the delay amount becomes larger when the resistor 129 is selected than when is selected. Therefore, transistors 115, 116, 117,
By designing the gate size of 118 to an appropriate value,
A delay circuit with two types of delay can be configured, and control terminals
The delay amount can be switched by the signal of 121.

In this embodiment, the delay amount is set to two types, but the present invention is not limited to this, and the number of types of delay amount can be increased by providing a plurality of control terminals or adding a decoder.

[0030]

As described in detail above, according to the present invention, the delay amount can be changed by software and an appropriate delay amount can be obtained. Therefore, the noise pulse width and the port output noise allowable amount which are different for each system can be widely varied. It is possible to provide a semiconductor integrated circuit that does not require revision of the logic to cope with the above. In addition, there is an excellent effect that the revision of the logic is unnecessary for adjusting the clock skew.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 2 is a block diagram showing a configuration of a delay circuit.

FIG. 3 is a block diagram showing a configuration of an input circuit including a delay circuit.

FIG. 4 is a block diagram showing a configuration of an output circuit including a delay circuit.

5 is an equivalent circuit diagram of the delay circuit shown in FIG.

FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to the present invention.

FIG. 7 is a block diagram showing a configuration of a delay circuit whose delay amount can be changed.

FIG. 8 is a block diagram showing a configuration of a noise canceller including a delay circuit whose delay amount can be changed.

FIG. 9 is a block diagram showing another configuration of the delay circuit.

10 is an equivalent circuit diagram of the delay circuit shown in FIG.

[Explanation of symbols]

 1 semiconductor integrated circuit 2 input terminal 3 input circuit 4 signal processing circuit 5 output circuit 33,34,35,36 delay circuit 37 control register

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising: a delay circuit having a variable delay amount; and a control register, wherein the control register is configured to change the delay amount. 2. A plurality of delay circuits having different delay amounts and a selection circuit are provided, and the selection circuit is configured to selectively select the delay circuit to change the delay amount. Semiconductor integrated circuit.