JPH06112740A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To obtain two currents having an accurate electric ratio by supplying a part of the output current to the base of a 3rd transistor TR via a base current compensating TR. CONSTITUTION:The base of a base compensating TR Q4 is connected to the collector of a 1st TR Q1, and the emitter of the TR Q4 is connected to the collector of a 2nd TR Q2 and to the bases of the 1st-3rd TRs Q1-Q3 respectively. Then the collector of the TR Q4 is connected to the collector of the TR Q3. Thus the output current of the (n) side of 1:n is partly supplied to the TR Q4. The output current is partly supplied to the base of the TR Q3 via the TR Q4 and therefore the base current can be completely canceled. Thus it is possible to eliminate the error of the output current caused by the base current and also to eliminate the fluctuation of the output current due to the current amplification factor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a current mirror circuit,
In particular, the present invention relates to a current mirror circuit in which the output current does not depend on the base current of the transistor, and further on the current amplification factor.

[0002]

2. Description of the Related Art There is a current mirror circuit shown in FIG. 2A as a current mirror circuit that obtains two output currents, which are 1: n of a current I ₀ and an output current nI _O obtained by multiplying the current I ₀ by a positive number. This is the most basic current mirror circuit. Q1 is a first transistor having a grounded emitter, and Q2 is a second transistor having a grounded emitter which forms a pair with the first transistor. The emitter area is n times the emitter area of the first transistor Q1. The first transistor Q1 and the second transistor Q2 are in a current mirror relationship with each other by connecting the collector of the first transistor Q1 and the bases of the first transistor Q1 and the second transistor Q2. Since the first transistor Q1 and the second transistor Q2 receive the same base bias, a current nI _{0, which} is n times the current I ₀ flowing through the first transistor Q1, flows in the second transistor Q2, Therefore, it can be said that two output currents having a current ratio of 1: n can be obtained.

However, this is not exactly the case. Because the current I to be supplied to the first transistor Q1
_This is because part of ₀ becomes the base current of the first transistor Q1 and the second transistor Q2. Assuming that the base current flowing through the first transistor Q1 is I _B , the base current flowing through the second transistor Q2 having an n times larger emitter area is nI _B , and eventually (1 + n) I.
_B is divided from I ₀ . Therefore, the first transistor Q
1 of collector _{current, I O - (1 + n} ) I B becomes Then, the collector current of the second transistor Q2, the first
N times the collector current of the transistor Q1
_{nI 0 -n (1 + n)} I B becomes is not become a nI _0. That is, the error only -n (1 + n) I _B occurs. Since I _B exists as an error component, the output current on the n-fold side varies depending on the current amplification factor h _FE of the transistor. When n is small, this is not a big problem unless h _FE is small, but it cannot be ignored when n is large.

FIG. 2B shows a Wilson type current mirror circuit in which a base current compensating transistor Q4 is connected in series to a second transistor Q2, and the base of the second transistor Q2 is connected to the collector of the first transistor Q1. Connected to. In this case, the first transistor Q1
I ₀ to nI _B, which should be supplied to, are divided as the base current of the base current compensating transistor Q4. And
A first transistor Q1 is the sum of the base current of the second transistor Q2 (1 + n) I _B becomes, therefore, the first
The transistor Q1 I ₀ -ni collector current flows _B, resulting inevitably in the collector of the second transistor Q2 flows through the n times n (I ₀ -nI _B). Depending, the collector current of the base current compensation transistor Q4 is ^{_{nI 0 - (n 2 -1)}} I B becomes, which is the output current of the n-side. After all, the influence of the base current could be reduced but the influence of the base current could not be eliminated.

FIG. 2 (C) shows the effect of the base current being made smaller. In the current mirror circuit shown in FIG. 2 (B), the second transistor Q2 has the same emitter as the first transistor Q1. The area is changed, and a modification is added so that a third transistor Q3 having a current mirror connection with the first transistor Q1 and the second transistor Q2 and having an emitter area n times larger is provided separately. In the current mirror circuit shown in FIG. 2 (C), a value I ₀ −I _B obtained by subtracting the base current I _B from the current I ₀ flows to the first transistor, and the relationship between the first transistor Q1 and the current mirror is established. N (I
₀ -I _B) flows. Therefore, the error is reduced to -ni _B.

[0006]

However, as shown in FIG.
Also in the current mirror circuit shown in (C), an error of the output current due to the base current of nI _B occurs, and therefore,
The error could not be completely eliminated. In particular, when n becomes large, the error becomes n times as large, and an error that cannot be ignored occurs.

The present invention has been made to solve such a problem, and improves the current mirror circuit shown in FIG. 2C to improve the base current I _{B of} the output current and the current amplification factor h.
_The aim is to eliminate the dependence on _FE and obtain exactly two currents with a current ratio of 1: n.

[0008]

According to another aspect of the present invention, there is provided a current mirror circuit, wherein a part of an output current is caused to flow to a base of a third transistor via a base current compensating transistor. The current mirror circuit according to claim 2, wherein the collector of the base current compensating transistor and the collector of the third transistor are connected to each other, and the emitter area of the third transistor is n-1 times that of the first and second transistors. It is characterized in that two output currents having a current ratio of 1: n are obtained from the first transistor and the third transistor.

[0009]

According to the current mirror circuit of the first aspect, a part of the output current is caused to flow to the base of the third transistor through the base current compensating transistor, so that the base current can be completely canceled and the output The error due to the base current of the current and the variation due to h _FE can be eliminated.

According to the current mirror circuit of claim 2,
Since the collector of the base current compensation transistor and the collector of the third transistor are connected, part of the output current flows to the base current compensation transistor. The third transistor has an emitter area that is (n-1) times that of the first and second transistors. Therefore, the following can be said.

That is, the original current (1 side voltage at 1: n)
Flow) I₀ From the base current of the transistor for base current compensation
Flow I_B Current I minus₀ -I_B Is the first transistor,
Flow into the second transistor and then (n-1) (I₀ 
-I_B ) Flows into the collector of the third transistor. So
The base current compensating transistor Q4 from the first to
Current supplied as the base current to the third transistor
Is the sum of (1 + n) I_B Therefore, the base current compensation
The current flowing through the collector of the compensation transistor is I ₀ + (N
-1) I_B Became, and this flowed into the third transistor
Current (n + 1) (I₀ -I_B ), NI₀ Tona
This becomes the n-side output current at 1: n. Obey
Two with an exact current ratio of 1: n without any error
Output current I_O , NI_O Is obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The current mirror circuit of the present invention will be described in detail below with reference to the illustrated embodiments. FIG. 1 is a circuit diagram showing one embodiment of the current mirror circuit of the present invention. Q1 is the first
This is a transistor whose emitter is grounded. Q2 is a second transistor whose emitter is grounded and whose emitter area is equal to that of the first transistor Q1. Q3 is a third transistor, the emitter of which is grounded, and the emitter area of which is n− of that of the first transistor Q1 and the second transistor Q2.
1 times, and the bases of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are connected to each other. It is not only the third transistor Q3 that makes the emitter area of the third transistor Q3 n-1 times that of the first and second transistors Q1 and Q2 but also n-1 times that of the third transistor Q3. This is because the current is also supplied to the second transistor Q2 via the base current compensation transistor Q4 described below.

Q4 is a base current compensation transistor,
Its base is connected to the collector of the first transistor Q1, and its emitter is connected to the collector of the second transistor Q2 and the bases of the first to third transistors Q1 to Q3. The collector of the base current compensation transistor Q4 is connected to the collector of the third transistor 3 so that a part of the output current on the n side in 1: n is supplied to the base current compensation transistor Q4. Has become.

In this current mirror circuit, a part of the original current, that is, the current I ₀ on the 1 side at 1: n is divided as the base current of the base current compensating transistor Q4, and the first transistor Q1 receives the current. I ₀ -I _B flows. Therefore, the second transistor Q2 also has I ₀ -I _B
However, the third transistor Q3 has (n-1) (I
₀ -I _B) flows.

The first to third transistors Q
1, Q2, Q3 sum of the base current of (1 + n) I _B, and the current I ₀ flowing through the second transistor Q2 to
-I _B is added, and the base current I ₀ of the base current compensation transistor Q4 itself is subtracted from the current I ₀ + (n
-1) I _B is the collector current of the base current compensation transistor Q4. The collector current _{I 0 + (n-1)} I B and a third of the base current compensation transistor Q4
Collector current (n-1) (I ₀ -I
_The current obtained by adding _B ) is the output current on the n-fold side in 1: n, which is nI ₀ . Therefore, there is no error component due to the base current. Therefore, there is no variation due to h _FE .

As described above, this current mirror circuit divides a part of the output current on the n side with respect to the second transistor through the base current compensating transistor, and instead, the emitter area of the third transistor Q3. N times not n
To -1 times and, since to be supplied as a base current to the third transistor Q3 via the minute its base current compensation transistor Q4 whose base current is spared from the output current of the transistor, the base current I _B Can be canceled completely. Therefore, it is possible to accurately obtain two output currents having a current ratio of 1: n without being affected by the variation of h _FE .

[0017]

According to the present invention, the current mirror circuit has a 1:
It is characterized in that a part of the n-side output current of n is made to flow to the base of the third transistor via the base current compensation transistor. Therefore, according to the current mirror circuit of the first aspect, since a part of the output current is caused to flow to the base of the third transistor via the base current compensating transistor, the base current can be completely canceled and the output current Error due to the base current of
h The variation due to _FE can be eliminated.

According to another aspect of the current mirror circuit of the present invention, the collector of the base current compensation transistor and the collector of the third transistor are connected to each other, and the emitter area of the third transistor is n of that of the first and second transistors. It is characterized in that it is multiplied by -1. Therefore, according to the current mirror circuit of the second aspect, a part of the output current on the n side is divided with respect to the second transistor via the base current compensating transistor, and instead, the third transistor Q3 is used.
N-1 times the emitter area, and
The base current of the transistor is supplied as the base current to the third transistor Q3 via the base current compensating transistor Q4 by the amount obtained by dividing the output current. It is possible to obtain two currents with a current ratio of Therefore,
It is possible to obtain two currents having an exact current ratio of 1: n without being affected by the variation of h _FE at all.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a current mirror circuit of the present invention.

2A, 2B, and 2C are circuit diagrams showing other conventional examples.

[Explanation of symbols]

Q1 first transistor Q2 second transistor Q3 third transistor Q4 base current compensation transistor I _B base current 1: n current ratio I ₀ yuan become current (1: 1 side of the current in the n)

Claims (2)

[Claims] 1. A first transistor, a second transistor connected in series with a base current compensation transistor whose base is connected to the collector of the first transistor, and a third transistor, The connection point between the second transistor and the base current compensation transistor is connected to the bases of the first to third transistors to form a current mirror coupling, and the first and third transistors have a predetermined ratio to each other. A current mirror circuit for obtaining two output currents, wherein a part of the output current of the third transistor flows to the base of the third transistor via the base current compensating transistor. circuit 2. The collector of the base current compensating transistor and the collector of the third transistor are connected, and the emitter area of the third transistor is n (positive number) -1 times that of the first and second transistors. 2. The current mirror circuit according to claim 1, wherein