JPH06110583A - Reset circuit - Google Patents

Abstract

PURPOSE:To provide the reset circuit for normally resetting a synchronous logic circuit mounted in a package in the case of newly inserting the package under the operating state of the device. CONSTITUTION:A package 3 is inserted through a connector 2 to the device. A reset pulse generating circuit 5 outputs a reset pulse RST generated by inputting a power supply VCC. A reset signal generating circuit 6 outputs a reset signal XRST. This reset signal XRST is a signal continuing the reset pulse RST until the prescribed number of clocks CP required for resetting a synchronous logic circuit 4 are inputted while receiving the reset pulse RST.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit used in a multiplex transmission device or the like for resetting a synchronous logic circuit mounted in a package for increasing the number of channels during operation.

[0002]

2. Description of the Related Art In recent years, digital multiplexing of transmission devices has become popular. Along with this, it is necessary to flexibly change the number of channels that can be serviced and to the operating state (when active) of the device. In other words, it is necessary to insert a package according to the number of channels at the time of activation and without affecting other operation channels (lines). Normally, a plurality of channels corresponding to respective lines are housed in one device and controlled by a common control unit or the like. Therefore, when a channel is newly added, a new package is inserted into the device while the device is powered on. The inserted package receives the power supply and the clock output from the common control unit, and enters the operating state.

However, when the synchronous logic circuit 4 is used for the circuit of the package 3, the order of contact of the pins of the connector 2 and the contact time depend on the force applied when the package 3 is inserted and the inclination of the package 3. It wasn't constant and couldn't reliably reset the circuit. The synchronous logic circuit 4 includes a synchronous clear circuit, and requires a clock during reset (FIG. 5). In addition, an internal memory that requires a clock may be included for initialization.

FIG. 3 is a state diagram of the terminals of the connector 2 when the package 3 is inserted. Here, FIG.
The state is before the package 3 is inserted and all terminals are not connected. FIG. 3B shows a process of inserting the package 3,
The state where the power supply terminals S1 and S2 are connected is shown. Also,
FIG. 3C shows a state after the package insertion is completed and all the terminals including the clock terminal are connected.

[0005]

In this case, in the conventional reset circuit shown in FIG. 5, the reset signal from the power supply monitoring IC 5 ends earlier than the clock signal as shown in the time chart of FIG. , Synchronous logic circuit 4
Cannot be reset normally. Since the connection time between the power supply terminal and the clock terminal due to the insertion of the package 3 is unspecified, it cannot be dealt with only by increasing the reset signal width from the power supply monitoring IC 5. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a reset circuit that receives an output of the power supply monitoring IC 5 and outputs a reset signal according to a clock signal.

[0006]

In order to solve the above-mentioned problems, the principle of the reset circuit of the present invention is shown in FIG.
Shown in. By counting the clock signals after receiving the reset pulse generated at the time of power input, a reset signal that continues to the reset pulse and has a time width in which a predetermined number of clocks necessary for resetting the synchronous logic circuit 4 is input. Output. Specifically, it is shown below (Fig. 4).
(A)).

In the reset circuit mounted in the package 3 inserted through the connector 2 in the operating state of the device 1, a reset pulse generating circuit 5 for generating a reset pulse at the time of inputting a power source, and an output from the reset pulse generating circuit 5 And a reset signal generating circuit 6 for receiving a clock signal input from the device and outputting a reset signal after receiving the reset pulse.

[0008]

According to the reset circuit configured as described above,
The post-clock signal CP is counted by a predetermined number and the reset signal XRST is output, so that the synchronous logic circuit 4 (clock synchronous circuit 4) can be reliably reset (FIG. 4).
(B), (c)).

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram, and FIG. 2 shows the time chart. A power supply monitoring IC is used as the reset pulse generating circuit 5. When power is input through the connector 2 when the package 3 is inserted into the device 1, the power supply voltage Vcc is generated.
Has reached a certain threshold value, the reset pulse generating circuit 5 (power supply monitoring IC 5) outputs a reset pulse RS1 having a certain width.

In this embodiment, an 8 KHz clock C synchronized with each channel corresponding to the transmission circuit to be inserted.
P1 and a 2 MHz clock CP2 synchronized with it are input. The reset signal generation circuit 6 includes CP1 and CP2.
It operates on condition that both are input. Therefore, the CP1 clock is input to the D-type F / F 6a, the CP2 clock is detected, and the clock CP3 is output. Further, CP3 is input to the counter 6b to generate a clock CP4 which is divided into a predetermined number.

When this CP4 is input as the clock of the D-type F / F 6c, the D input terminal of the D-type F / F 6c becomes High.
It is pulled up to the h level and the inverted signal of RS1 is input to the reset terminal. Therefore, from the time the power is input until the first rise of the divided clock CP4,
The output XRST of the D-type F / F 6c is kept at the LOW level. Specifically, the frequency division ratio is 1024 (n = 10)
Then, the reset time is about 128 msec.

The output XRST of the D-type F / F 6c is input to the clock synchronizing circuit as a final reset signal. As a result, the clock synchronization circuit 4 inputs about 1024 8 KHz clock CPs while inputting the reset signal.

In this embodiment, 2 MHz and 8 KHz
However, if there is only one clock, CP1 or CP2 may be directly input to the counter 6b. When the frequency division ratio of the counter 6b is set to 1, the counter 6b can be omitted.

[0014]

As described above, according to the present invention, after receiving the reset pulse of the reset pulse generation circuit 5, the clock signal is received and the reset signal generation circuit 6 outputs the reset signal after a lapse of a predetermined time. Equipped with. Therefore, when the package 3 is inserted into the connector 2 mounted on the device 1 in the operating state of the device 1, even if the terminal of the clock signal is connected later than the power supply terminal, the synchronous logic circuit 4 (clock synchronous circuit 4) is not connected. It can be reliably reset.
As a result, the package 3 can be inserted into the device 1 without affecting other operating circuits (other lines).

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention.

FIG. 3 is a terminal state diagram when the package 3 is inserted into the device 1.

FIG. 4 is a diagram for explaining the principle of the present invention.

FIG. 5 is a block diagram showing a conventional reset circuit.

FIG. 6 is a time chart showing the operation of a conventional reset circuit.

[Explanation of symbols]

 1 device. 2 connectors. 3 packages. 4 Synchronous logic circuit (clock synchronization circuit). 5 Reset pulse generation circuit (power supply monitoring IC). 6 Reset signal generation circuit.

Claims (1)

[Claims] 1. A reset circuit for resetting a synchronous logic circuit (4) mounted on a package (3) inserted through a connector (2) when the device (1) is in operation, wherein a reset pulse is supplied when power is input. And a reset pulse generating circuit (5) for generating the reset pulse, and after receiving the reset pulse output from the reset pulse generating circuit, receiving the clock signal input from the device and outputting the reset signal after a lapse of a predetermined time. A reset circuit comprising a reset signal generation circuit (6).