JPH0611509Y2 - Matrix switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application field" The present invention relates to a matrix switch circuit used in a test device for an IC or the like.

"Background of the Invention" IC test methods include a functional test and a DC characteristic test. The functional test is a test for checking whether or not the IC is actually operated to operate normally.

The direct current characteristic test applies a voltage or current having a known value to each terminal of the IC under test. That is, in the voltage applied current measurement mode, the current flowing at that time is captured as data. In the current applied voltage measurement mode, the current I is applied.
In this test, the voltage at the C terminal is measured, and whether the voltage is within the specified range is checked to determine whether the voltage is good or not.

In order to perform the DC characteristic test, it is necessary to connect a plurality of DC current / voltage generators, current measuring means, and voltage measuring means to each terminal of the IC under test.

FIG. 2 shows the configuration of the current / voltage generator in the voltage applied current measurement mode, and FIG. 3 shows the configuration of the current / voltage generator in the current applied voltage measurement mode.

In FIGS. 2 and 3, IV indicates the whole current-voltage generator. Although one terminal B of the IC under test 12 is shown in the figure, the current voltage generator IV is similarly applied to the other terminals.
Are connected. Although the connection may differ depending on the measurement mode, the current / voltage generator IV is DA
Converter 1, operational amplifier 2, differential amplifier 3, current-
It is composed of a voltage converter 4, a buffer amplifier 5, and an AD converter 6.

A pattern signal is provided from an externally provided pattern generator 11 to the DA converter 1, and the pattern signal is DA-converted to give an analog signal that changes according to the pattern signal to the operational amplifier 2.

The operational amplifier 2 amplifies the analog signal supplied from the DA converter 1 and supplies it to one terminal of the IC under test 12, for example, the terminal B, through the cable L ₁ . The cable L ₂ supplies the voltage of the terminal B of the IC under test 12 to the buffer amplifier 5,
The output of the buffer amplifier 5 is fed back to the input side of the operational amplifier 2, the voltage at the terminal B of the IC under test 12 is balanced with the analog voltage given from the DA converter 1, and the analog signal given from the DA converter 1 is fed to the terminal B. The voltage of is set to follow and change. L ₃ is a shield conductor. The shield conductor L ₃ is connected to a potential point that changes at the same voltage as the output voltage of the current / voltage generator IV. Also L ₄ and L ₅
Indicates a cable for the ground circuit.

The current flowing (or attracting) from the operational amplifier 2 to the terminal B is converted into a voltage signal by the current-voltage converter 4, the voltage signal is taken out by the differential amplifier 3 as a current detection signal, and its output is the AD converter 6. Is converted into a digital signal, and the digital signal is input to the data processing device 7 to perform processing such as pass / fail judgment.

The above is a description of the configuration and operation of the voltage applied current measurement mode shown in FIG.

In the current applied voltage measurement mode shown in FIG. 3, the current value given from the operational amplifier 2 to the terminal B of the IC 12 to be measured is changed to the current −.
Detected by the voltage converter 4, the voltage signal is taken out by the differential amplifier 3 and fed back to the input side of the operational amplifier 2,
Is operated as a constant current source. Therefore, the operational amplifier 2
Supplies a current corresponding to the voltage signal supplied from the DA converter 1 to the terminal B of the IC 12 under test through the cable L ₁ .

The voltage generated at the terminal B is given to the buffer amplifier 5 through the cable L ₂ , the output of the buffer amplifier 5 is input to the AD converter 6, and the data processing device 7 outputs the voltage measurement signal.
Given to.

From the above, the DC characteristic test of the IC can be understood.

By the way, the direct current characteristic test includes a test performed in a weak current / voltage region and a test performed in a current / current / voltage region larger than this. Therefore, two types of current / voltage generators are prepared for the current / voltage generator IV. That is, a small current / voltage generator for the small current / voltage region and a large current / voltage generator for the large current / voltage region are prepared, and these are switched over to test the IC 1 under test.
It is connected to No. 2 and a test in a small current voltage region and a test in a large current voltage region are performed. A matrix switch circuit is used for this switching.

"Prior Art" FIG. 4 shows a connection relationship between a conventional matrix switch circuit, a current / voltage generator for a minute current / voltage region, a current / voltage generator for a large current voltage, and an IC 12 under test.

In the figure, 100 is a matrix switch circuit, 200 is a current / voltage generator group for a minute current / voltage region, and 300 is a current / voltage generator group for a large current / voltage region.

In the matrix switch circuit 100, 101 indicates a connection terminal of the IC under test 12, that is, a connection terminal. 10
Reference numeral 2 denotes a connection terminal of the small current / voltage generator group 200, and 103 denotes a connection terminal of the large current / voltage generator group 300. Tested I
The number of connection terminals 101 to be tested of C12 is the same as the number of terminals of the IC 12 to be tested. The figure shows a case where 25 terminals are provided, but actually, about 125 terminals are provided.

The minute current / voltage generator group 200 is provided with as many current / voltage generators IVA as the number of terminals of the IC 12 under test. Although this example shows the case where 25 current / voltage generators IVA are provided, actually, the same number of current / voltage generators IVA as the number of terminals of the IC 12 under test are provided.

On the other hand, the large-current-voltage generator group 300 is provided with a smaller number of current-voltage generators IVB than the number of terminals of the IC 12 under test.
A current / voltage generator IV provided in the large current / voltage generator group 300
The reason for reducing the number of B is that the large current voltage generator IVB is larger and more expensive than the minute current voltage generator IVA.
This small number of large current / voltage generators IVB is used as the IC1 to be tested.
A matrix switch circuit 100 is used to allow connection to any of the two terminals.

A switch group 201 is provided between the minute current / voltage generator group 200 and the terminal 102, and the switch 201 is selectively turned on / off to control the minute current / voltage generator group IVA via the matrix switch circuit 100. Test IC1
2 terminals A to Y.

The large current voltage generator IVB is connected to any of the terminals A to Y of the IC under test 12 by turning on a switch at any intersection of the matrix switch circuit 100. A fifth point is provided at each intersection of the matrix switch circuit 100.
As shown in the figure, three switches S ₁ , S ₂ and S ₃ are provided, and by controlling these three switches S ₁ and S _{2 to} be turned on, the cable L ₁ of the large current voltage generator IVB.
And L ₂ are connected to pins of the IC under test 12. The switch S ₃ is used as a switch for connecting and disconnecting the shield conductor L ₃ that covers the cables L ₁ and L ₂ . The ground circuit cables L ₄ and L ₅ are connected to the IC under test 12 without passing through the matrix switch circuit.

[Problems to be Solved by the Invention] The conventional matrix switch circuit 100 has a structure in which the row lines X and the column lines Y are provided throughout the matrix. For this reason, the row line X and the column line Y become long, and all the row lines X and the column lines Y are coupled through the matrix switch provided at the intersection, so that the stray capacitance of each row line X and the column line Y becomes large. However, there is a drawback that it is easy to pick up induced noise.

If a large stray capacitance is connected to the load in both the current / voltage generators IVA and IVB, there is a drawback in that the rise or fall of the current or voltage applied to the terminals of the IC under test 12 is delayed. The stray capacitance becomes a large load on the device under test, and some devices may oscillate.

In order to complete the DC test in a short time, it is necessary to change the current or voltage applied to the terminal of the IC under test 12 at a high speed and measure the voltage generated at the terminal or the current value flowing into the terminal according to the change.

Therefore, the current / voltage generator IVA or IVB and the IC under test 1
If there is a large stray capacitance between the two, the current and voltage waveforms given from the current / voltage generators IVA and IVB to the terminals of the IC under test 12 are delayed. As a result, the voltage generated at the terminal or the current flowing into the terminal must be measured after the current / voltage has stabilized, which is disadvantageous in that the measurement takes time.

Further, when the induced noise rides on the row line X and the column line Y, the induced noise is passed through the cables L ₁ and L ₂ to generate the current / voltage generator I.
Given to VA or IVB. If this noise is input to the buffer amplifier 3 and fed back to the feedback point of the operational amplifier 2, there is a risk of giving an error to the voltage value and the current value output from the current / voltage generator IV.

An object of the present invention is to reduce the stray capacitance generated in the matrix switch part and to provide a matrix switch in which induction noise is less mixed.

"Means for Solving the Problem" In this invention, each switch group forming a matrix switch is divided into a plurality of blocks, and the input side of each row line of each divided matrix switch block is divided into row direction block units. Commonly connected via a switch to the current voltage generators connected to each row line, and the input side of each column line of each of the divided matrix switch blocks is connected to each column line in column direction block units. Connected to each of the current and voltage generators via a switch in common, and the output side of these column lines is commonly connected to the connected terminals, and only the block to be used is connected to the output side of the current and voltage generator. It is the one.

According to the structure of the present invention, a matrix switch circuit of a relatively small block is connected to the output side of the current / voltage generator. As a result, the blocked matrix switch circuit can shorten the lengths of the row lines and the column lines. Therefore, the stray capacitance can be reduced. Furthermore, the rate of picking up induced noise can be reduced.

Therefore, according to this invention, a large stray capacitance is not connected to the output side of the current-voltage generator. Therefore DA
There is no delay in the current or voltage changing from the converter 1 to high speed, and the voltage generated at the terminal of the IC under test 12 or the current flowing into the terminal can be measured at high speed, and the test time can be shortened. can do.

Further, since the level of induced noise can be reduced, it is possible to apply a voltage or current without error to the terminals of the IC under test.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In the figure, 12 is an IC to be tested, 400 is a matrix switch circuit according to the present invention, 200 is a group of minute current voltage generators, and 300 is a group of large current voltage generators.

The matrix switch circuit 400 according to the present invention divides the switches constituting the matrix switch circuit 400 into a plurality of blocks MA to MO, and a row current X and a column wire Y of each block are supplied with a large current voltage generator through switches K _X and K _Y. It is configured to be connected to the IVB and the minute current voltage generator IVA.

The column line Y of each block MA to MO, that is, the output side, is commonly connected to a connected terminal 402 for connecting corresponding terminals of each block to the IC 12 under test by a crossover line 401, and the commonly connected connected terminals are connected. Connect the terminal 402 to the IC under test 1
2 terminals A to Y.

In this embodiment, a matrix switch circuit 400 consisting of 15 row lines X and 25 column lines Y is divided into 15 blocks MA to MO. Therefore, one block is a matrix block having five row lines and five column lines.

In this structure, in order to connect all of the minute current / voltage generator group IVA to the terminals A to Y of the IC under test 12, switches on the input side of each column line of all blocks in an arbitrary row direction, for example, the uppermost stage. Each switch K of block MA-ME
All _Y should be controlled to be on.

All small current voltage generator IVA is controlled to all switch on _{K Y} of the uppermost block MA~ME is connected to all terminals A~Y under test IC 12. Although each column line Y is shown as a single line in the drawing, the column line Y and the row line X form a set of three lines as described in FIG.

The voltage applied current measurement and the current applied current measurement in the minute current voltage region are performed in a state where all of the minute current voltage generator IVA are connected to all terminals of the IC under test 12.

On the other hand, when conducting a DC characteristic test in a large current region, for example, in order to connect the large current voltage generator IVB ₁ to the terminal A of the IC under test 12, turn on the top switch of the switch K _X of the block MA, The switch at the intersection of the row line and the column line to which the terminal A is connected may be controlled to be turned on.

To connect the large-current voltage generator IVB ₂ to the terminal Y of the IC under test 12, the intersection of the second switch from the top of the switch K _X of the block ME and the column line to which this row line and the terminal Y are connected is connected. It may be controlled by turning on the switch.

Further, in order to connect the large current voltage generator IVB ₁₁ to the terminal S of the IC under test 12, the top switch of the switch K _X of the block MN and the intersection of this row line and the column line to which the terminal S is connected are connected. The switch may be controlled to be turned on.

[Advantageous effects of the device] As described above, according to the present invention, the inside of a large matrix switch circuit is divided into a plurality of blocks, and the row lines and column lines of each block are shortened, so that each block is formed into a matrix switch block. The stray capacitance of MA to MO can be reduced. Also, since the size of the matrix is reduced, the rate of picking up induced noise can be reduced.
Therefore, it is possible to reduce the level of inductive noise induced in the voltage detection cables L _{2 and the} like of the minute current voltage generator IVA and the large current voltage generator IVB.

As a result, even if the current or voltage applied from the voltage / current generator to each terminal of the IC under test is changed at high speed, the influence of the stray capacitance is small, so that the rise and fall of the current and voltage waveforms are not delayed and the IC under test is not delayed. It is given to each terminal. Therefore, a high speed test becomes possible.

Further, since the level of the induced noise induced in the voltage detection cable L _{2 and the} like can be lowered, the noise is not fed back to the operational amplifier 2 (FIGS. 2 and 3) that outputs a current or a voltage. Therefore, a current and a voltage with a small error can be applied to the IC under test, and a highly reliable DC characteristic test can be performed.

In the above description, the row line X of each matrix block MA-MO
Although the example in which the column line Y is connected to the current / voltage generator has been described, it can be easily understood that the present invention can be applied to the case of connecting a device other than the current / voltage generator.

[Brief description of drawings]

FIG. 1 is a connection diagram for explaining one embodiment of the present invention,
2 and 3 are connection diagrams for explaining the method of DC characteristic test of the IC, FIG. 4 is a connection diagram for explaining a conventional matrix switch circuit, and FIG. 5 is a conventional matrix switch circuit. It is a connection diagram for explaining the connection structure of each intersection. 12: IC to be tested, 200: Micro current / voltage generation circuit group,
300: Large current voltage generator group, 400: Matrix switch circuit, MA to MO: Matrix block, X:
Row lines of the matrix block, Y: column lines of the matrix block, K _X: switch connecting the row lines of the matrix blocks to the plurality of devices, K _Y: switch connecting the column lines of the matrix blocks to the plurality of devices, 402: Connected terminal.

Claims (1)

[Scope of utility model registration request] 1. A matrix switch having a switch at each intersection of a plurality of row lines and a plurality of column lines, and the same number of row lines as the number of row lines connected to the input side of each row line of the matrix switch. A plurality of devices, a second plurality of devices having the same number as the column lines connected to the input sides of the column lines of the matrix switch, and column lines connected to the output sides of the column lines of the matrix switch, respectively. And a plurality of connected terminals, the number of which is the same as that of the second line connected to the column line.
Of the plurality of devices are directly connected to the connected terminals through the matrix switch regardless of their operation, and the first plurality of devices connected to the row line are selectively operated by the operation of the matrix switch. In the matrix switch circuit connected to the connected terminals, the matrix switch is divided into a plurality of blocks in a row direction and a column direction, and an input side of each row line of each divided matrix switch block is a row direction block unit. Then, the first device connected to each row line is commonly connected via a switch, and the input side of each column line of each of the divided matrix switch blocks is connected to each column in a column direction block unit. The second connected to a wire
The matrix switch circuit is characterized in that the output side of these column lines are connected to the connected terminals in common while being connected to each of the devices in common through switches.