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JPH06104413A - Manufacturing for semiconductor device - Google Patents

Manufacturing for semiconductor device

Info

Publication number
JPH06104413A
JPH06104413A JP27375092A JP27375092A JPH06104413A JP H06104413 A JPH06104413 A JP H06104413A JP 27375092 A JP27375092 A JP 27375092A JP 27375092 A JP27375092 A JP 27375092A JP H06104413 A JPH06104413 A JP H06104413A
Authority
JP
Japan
Prior art keywords
grinding
substrate
oxide film
bonding
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27375092A
Other languages
Japanese (ja)
Other versions
JP2866263B2 (en
Inventor
Shinsuke Sakai
慎介 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP4273750A priority Critical patent/JP2866263B2/en
Publication of JPH06104413A publication Critical patent/JPH06104413A/en
Application granted granted Critical
Publication of JP2866263B2 publication Critical patent/JP2866263B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To reduce a productive cost and make quality control easy, by using simple formation steps including a step for grinding and lapping a joining layer to form a flat face of an SIO-structured board. CONSTITUTION:A joining layer 4 made of polysilicon is formed on a side of an active layer substrate (A). After the joining layer 4 is put in a ductility-mode grinding step and a specular grinding face 4b is formed, an insulating layer 7 is formed on the grinding face 4b. Then, a base substrate (B) is bonded to the joining face 7a of the insulating layer 7 to form a semiconductor substrate in an SOI structure. The manufacturing step can be simplified without forming a joining layer in a multi-layered structure. The bonding face is made smooth by this insulating layer 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板上に単結晶
・多結晶若しくは非晶質シリコン層を鏡面状態で形成す
る半導体基板の製造方法に関し、特に、薄膜SOI構造
基板や誘電体分離基板の接合を容易にするための接合層
の形成工程と研削・研磨工程を簡略化し、機械的な研削
と研磨だけで鏡面状態の接合面を作製することができる
半導体基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate in which a monocrystalline / polycrystalline or amorphous silicon layer is formed on a semiconductor substrate in a mirror surface state, and more particularly to a thin film SOI structure substrate or a dielectric isolation substrate. The present invention relates to a method for manufacturing a semiconductor substrate, which simplifies the bonding layer forming step and the grinding / polishing step for facilitating the bonding, and can form a mirror-like bonded surface only by mechanical grinding and polishing.

【0002】[0002]

【従来の技術】集積回路を形成するにあたり、この集積
回路をバルク状の半導体基板につくり込む手法に比べる
と、酸化膜絶縁層上に設けられた薄膜半導体層に各種素
子(デバイス)を形成する手法の方が、α線障害の特性
や動作速度などの素子特性に優れ、しかも、素子間分離
の点でも有利となる。
2. Description of the Related Art When forming an integrated circuit, various elements (devices) are formed in a thin film semiconductor layer provided on an oxide film insulating layer, as compared with a method of forming this integrated circuit in a bulk semiconductor substrate. The method is superior in element characteristics such as α-ray interference characteristics and operating speed, and is also advantageous in terms of element separation.

【0003】この種の半導体基板は、SOI(シリコン
・オン・インシュレータ)ウィーハと称されているが、
かかるSOIウェーハにおいては、素子を形成するシリ
コン層を薄くすればするほど、pn接合の寄生容量を減
少させ素子の動作速度を高めることができるため、シリ
コン層の超薄膜化が検討されている。また、集積度を高
めるためには3次元構造を実現することが効果的である
が、その一手法として、酸化膜と半導体層とを重ね合わ
せた基本構造が構成できるSOIウェーハが注目されて
いる。
This type of semiconductor substrate is called an SOI (silicon on insulator) wafer,
In such an SOI wafer, the thinner the silicon layer forming the device is, the more the parasitic capacitance of the pn junction can be reduced and the operating speed of the device can be increased. Further, it is effective to realize a three-dimensional structure in order to increase the degree of integration, and as one method therefor, an SOI wafer that can form a basic structure in which an oxide film and a semiconductor layer are superposed is drawing attention. .

【0004】ところで、SOI構造基板を得るための手
法として、いわゆる張り合わせ法が知られている。従来
の張り合わせ法は、まず、シリコン基板1(以下、活性
層基板1あるいは活性層基板Aともいう)の一面にSi
2 からなる酸化膜3を形成し(図7(a)参照)、こ
の酸化膜3上にポリシリコンからなる接合層4を形成す
る(図7(b)参照)。次に、この接合層4の表面をメ
カノケミカル研磨して、平坦化したのち(図7(c)参
照)、この研磨面4aに別のシリコン基板5(以下、支
持体基板5あるいは支持体基板Bともいう)を張り合わ
せて(図9(g)参照)、最後に、活性層基板1の表面
を、酸化膜3が露出するまで研削および研磨する(図9
(h)参照)。
By the way, a so-called laminating method is known as a method for obtaining an SOI structure substrate. In the conventional bonding method, first, Si is formed on one surface of a silicon substrate 1 (hereinafter, also referred to as active layer substrate 1 or active layer substrate A).
An oxide film 3 made of O 2 is formed (see FIG. 7A), and a bonding layer 4 made of polysilicon is formed on the oxide film 3 (see FIG. 7B). Next, the surface of the bonding layer 4 is subjected to mechanochemical polishing to be flattened (see FIG. 7C), and then another silicon substrate 5 (hereinafter referred to as a support substrate 5 or a support substrate) is provided on the polishing surface 4a. (Also referred to as B) (see FIG. 9G), and finally, the surface of the active layer substrate 1 is ground and polished until the oxide film 3 is exposed (FIG. 9).
(See (h)).

【0005】ところが、このような張り合わせ法による
SOI基板の製造方法においては、フォトリソグラフィ
ー技術やエッチング技術によって予めパターニング2
(図7(a)参照)を施した活性層基板Aを用い、この
上に酸化膜3を形成すると、接合層4を構成するポリシ
リコンの表面が、グレインサイズの関係で、研削および
研磨によっても平滑にならないという問題があった。
However, in the method of manufacturing an SOI substrate by such a bonding method, patterning 2 is performed in advance by a photolithography technique or an etching technique.
When the active layer substrate A (see FIG. 7A) is used and the oxide film 3 is formed on the active layer substrate A, the surface of the polysilicon forming the bonding layer 4 is subjected to grinding and polishing due to the grain size. There was a problem that it was not smooth.

【0006】すなわち、本発明者が探求したところによ
れば、接合層4を構成するポリシリコン層は、一般に導
電性、不純物の拡散速度、膜の安定性、酸化速度等の特
性を高めるために高温の反応温度で成長させるが、ポリ
シリコンのグレインサイズは反応温度が高いほど大きく
なるため、得られる接合層4の粒径は比較的大きくな
り、しかも、結晶成長は表面に垂直な方向に生じること
から、酸化膜3の凹凸部分では異なる方向にポリシリコ
ンの結晶が成長し、これらが衝突する界面が形成されて
しまう。これに加えて、メカノケミカル研磨などの化学
的研磨を行うと、その研磨速度は結晶の粒径、面方位、
成長方向などの影響を受け易いため、ポリシリコンの表
面をメカノケミカル研磨すると全体的には選択的な研磨
が行われたような状況となる。そのため、接合面4aは
目的とする平坦性を得ることができず、支持体基板Bを
張り合わせても、予定する接合強度が得られないという
問題があった。
That is, according to what the inventors of the present invention have sought, the polysilicon layer forming the bonding layer 4 is generally used to improve the characteristics such as conductivity, impurity diffusion rate, film stability, and oxidation rate. Although grown at a high reaction temperature, the grain size of polysilicon becomes larger as the reaction temperature becomes higher, so that the grain size of the bonding layer 4 obtained becomes relatively large, and the crystal growth occurs in the direction perpendicular to the surface. Therefore, in the uneven portion of the oxide film 3, polysilicon crystals grow in different directions, and an interface with which these collide is formed. In addition to this, when chemical polishing such as mechanochemical polishing is performed, the polishing rate is
Since it is susceptible to the growth direction and the like, mechanochemical polishing of the surface of polysilicon results in a situation in which selective polishing is performed overall. Therefore, there is a problem that the desired flatness cannot be obtained on the bonding surface 4a, and the intended bonding strength cannot be obtained even when the support substrate B is bonded.

【0007】そこで、酸化膜3を形成した上に高温反応
により成長させたポリシリコンからなる第1の接合層4
を形成し、この第1の接合層4を研削・研磨して表面を
ある程度平滑にしたのち(図7(c)参照)、さらにこ
の第1の接合層4の表面に、低温反応により成長させた
ポリシリコン層(第2の接合層)6を形成して(図8
(d)参照)、これを研磨し、所定の平滑性を得るよう
にしている(図8(e)参照)。
Therefore, the first bonding layer 4 made of polysilicon grown by the high temperature reaction on the oxide film 3 is formed.
Is formed, and the first bonding layer 4 is ground and polished to make the surface smooth to some extent (see FIG. 7C), and then grown on the surface of the first bonding layer 4 by a low temperature reaction. And a polysilicon layer (second bonding layer) 6 is formed (see FIG. 8).
(See (d)), and this is polished to obtain a predetermined smoothness (see FIG. 8E).

【0008】かかる手法によれば、接合面6aとなる第
2の接合層6は、グレインサイズが小さいポリシリコン
から形成されているため、メカノケミカル研磨を施して
も、選択的な研磨は相対的に(見かけ上)減少し、その
結果、支持体基板Bを張り合わせた場合の接合強度が高
まり、剥がれを防止することができる。
According to this method, since the second bonding layer 6 which becomes the bonding surface 6a is formed of polysilicon having a small grain size, even if mechanochemical polishing is performed, selective polishing is relatively performed. (Apparently), and as a result, the bonding strength when the support substrate B is attached is increased, and peeling can be prevented.

【0009】なお、集積度を高めるために接合面6aに
SiO2 からなる第2の酸化膜7を形成し(図8(f)
参照)、この酸化膜7に支持基板5を張り合わせること
も行われている。
A second oxide film 7 made of SiO 2 is formed on the bonding surface 6a in order to increase the degree of integration (FIG. 8 (f)).
Also, the support substrate 5 is bonded to the oxide film 7.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、接合層
表面の平滑性を高めるために、接合層を多層構造(上述
した例では、第1の接合層4と第2の接合層6)にする
と、製造工程が増加し、製造コストや品質管理の点で問
題があった。
However, in order to improve the smoothness of the surface of the bonding layer, if the bonding layer has a multilayer structure (the first bonding layer 4 and the second bonding layer 6 in the above-mentioned example), The number of manufacturing processes increased, and there were problems in terms of manufacturing cost and quality control.

【0011】本発明は、このような従来技術の問題点に
鑑みてなされたものであり、SOI構造基板の接合面を
平坦化するにあたり、その接合層の形成工程および研削
・研磨工程を簡略化することにより、製造コストの低減
を図るとともに品質管理を容易にすることを目的とす
る。
The present invention has been made in view of the above problems of the prior art, and in flattening the bonding surface of the SOI structure substrate, the bonding layer forming step and the grinding / polishing step are simplified. By doing so, it is intended to reduce manufacturing cost and facilitate quality control.

【0012】[0012]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体基板の製造方法は、一方の半導体基
板の少なくとも片面に接合層を形成し、該接合層を研磨
して接合面を形成したのち、該接合面に他方の半導体基
板を張り合わせてSOI構造の半導体基板を作製する製
造方法において、前記接合層を延性モード研削により研
削して鏡面状態の研削面を形成したのち、この研削面に
酸化膜を形成することを特徴としている。
In order to achieve the above object, a method of manufacturing a semiconductor substrate of the present invention comprises forming a bonding layer on at least one surface of one semiconductor substrate and polishing the bonding layer to bond the bonding surface. In the manufacturing method of manufacturing the semiconductor substrate having the SOI structure by bonding the other semiconductor substrate to the bonding surface after the formation of the bonding layer, the bonding layer is ground by ductile mode grinding to form a mirror-finished ground surface. The feature is that an oxide film is formed on the ground surface.

【0013】[0013]

【作用】硬脆材料であるシリコンを研削すると、一般的
には、クラックをともなう脆性破壊加工となり、研削面
は破砕面となる。しかしながら、このような硬脆材料で
あっても、0.1μmオーダーの微小切込みなど、加工
単位を十分微少な範囲に限定すると、脆性破壊ではなく
塑性域での鏡面研削が可能となる。
When silicon, which is a hard and brittle material, is ground, brittle fracture processing with cracks is generally performed, and the ground surface becomes a crushed surface. However, even with such a hard and brittle material, if the processing unit is limited to a sufficiently small range such as a minute cut on the order of 0.1 μm, it is possible to perform mirror surface grinding in the plastic region instead of brittle fracture.

【0014】かかる硬脆材料の塑性域における研削は、
特に延性モード研削あるいは塑性流動型研削と呼ばれ、
この延性モード研削を実現するために最も重要なパラメ
ータは、脆性破壊と塑性変形破断との遷移点を表わす臨
界加工単位dc(延性・脆性圧力遷移点Pcともいう)
である。
Grinding of the hard and brittle material in the plastic region is
Especially called ductile mode grinding or plastic flow type grinding,
The most important parameter for realizing this ductile mode grinding is the critical processing unit dc (also referred to as ductile / brittle pressure transition point Pc) that represents the transition point between brittle fracture and plastic deformation fracture.
Is.

【0015】そして、この臨界加工単位は、材料固有の
値であって、臨界加工単位以下の押し込み荷重で制御し
ながら研削を行うと、脆性破壊を生じ易い硬脆材料であ
っても塑性的挙動を示すことになる。
This critical processing unit is a value peculiar to the material, and if grinding is performed while controlling the pushing load below the critical processing unit, even if the material is hard and brittle, brittle fracture is likely to occur Will be shown.

【0016】したがって、本発明では、研削・研磨しよ
うとする一方の半導体基板に形成した接合層を、少なく
とも研削・研磨の最終工程で、既述した延性モード研削
を行い、その結果得られる研削面を鏡面状態とし、この
研削面にさらに酸化膜を形成して、この面を接合面とし
ている。
Therefore, in the present invention, the bonding layer formed on one of the semiconductor substrates to be ground / polished is subjected to the above-described ductile mode grinding at least in the final step of grinding / polishing, and the resulting ground surface is obtained. Is mirror-finished, an oxide film is further formed on this ground surface, and this surface is used as a bonding surface.

【0017】これにより、従来、接合面を平坦化するた
めに形成していた接合層を多層構造とする必要がなくな
る。例えば、一方の半導体基板に、高温反応によってポ
リシリコンを成長させて接合層を形成し、この接合層を
延性モード研削すれば、それだけで鏡面状態の研削面を
得ることができ、この研削面にさらに酸化膜を形成して
接合面としたのち、他方の半導体基板を張り合わせてS
OI構造の半導体基板を作製することができる。
As a result, it is no longer necessary to have a multi-layer structure for the bonding layer which has been conventionally formed for flattening the bonding surface. For example, on one of the semiconductor substrates, polysilicon is grown by a high temperature reaction to form a bonding layer, and if this bonding layer is subjected to ductile mode grinding, it is possible to obtain a mirror-finished ground surface by itself. Further, after forming an oxide film to form a bonding surface, the other semiconductor substrate is bonded and S
A semiconductor substrate having an OI structure can be manufactured.

【0018】得られる接合面は、下層を構成する接合層
の研削面がきわめて平滑な面であり、これに加えて、こ
の平滑な面にさらに酸化膜を形成しているので、研削面
に生じる研削ダメージを酸化膜で緩和することができ、
これによって接合面の平滑性がさらに助長される。した
がって、張り合わせのための接合層の形成工程と、研削
・研磨工程を簡略化することが可能となり、製造コスト
の低減と品質管理の容易化を実現することができる。
In the obtained joint surface, the ground surface of the joint layer constituting the lower layer is an extremely smooth surface, and in addition to this, an oxide film is further formed on this smooth surface, so that it occurs on the ground surface. Grinding damage can be mitigated with an oxide film,
This further promotes the smoothness of the joint surface. Therefore, it becomes possible to simplify the step of forming the bonding layer for bonding and the step of grinding / polishing, and it is possible to reduce the manufacturing cost and facilitate the quality control.

【0019】[0019]

【実施例】本発明の半導体基板の製造方法について、好
ましい一実施例を挙げ、図面に基づいて具体的に説明す
る。ただし、以下に説明する実施例は、本発明の理解を
容易にするために記載されたものであって、本発明を限
定するために記載されたものではない。したがって、以
下の実施例に開示された各要素は、本発明の技術的範囲
に属する全ての設計変更や均等物をも含む趣旨である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor substrate according to the present invention will be specifically described with reference to the accompanying drawings with reference to a preferred embodiment. However, the examples described below are described for facilitating the understanding of the present invention, and not for limiting the present invention. Therefore, each element disclosed in the following embodiments is intended to include all design changes and equivalents within the technical scope of the present invention.

【0020】図1〜図3は、本発明の一実施例に係る半
導体基板の製造方法を説明する断面図であり、図1
(a)は酸化膜形成工程、図1(b)は接合層形成工
程、図1(c)は研削工程、図2(d)は延性モード研
削工程、図2(e)は第2の酸化膜の形成工程、図2
(f)は張り合わせ工程、図3(g)は活性層基板の研
削工程をそれぞれ説明する断面図である。
1 to 3 are sectional views for explaining a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.
1 (a) is an oxide film forming step, FIG. 1 (b) is a bonding layer forming step, FIG. 1 (c) is a grinding step, FIG. 2 (d) is a ductile mode grinding step, and FIG. 2 (e) is a second oxidation step. Membrane forming process, FIG.
FIG. 3F is a cross-sectional view illustrating the laminating step, and FIG. 3G is a cross-sectional view illustrating the grinding step of the active layer substrate.

【0021】まず、図1(a)に示すように、単結晶シ
リコンからなる半導体基板1(以下、活性層基板A、あ
るいは活性層基板1ともいう)の片面に、フォトリソグ
ラフィ技術やエッチング技術を用いて、例えば深さが
0.1μmの溝2を10μmの間隔で形成する。この表
面を熱酸化して、厚さ0.01μmのSiO2 膜を形成
し、さらに、この熱酸化によるSiO2 膜上に、CVD
法によって厚さ0.9μmのSiO2 膜を形成する。こ
れら1.0μmのSiO2 膜が、活性層基板の表面層3
(以下、酸化膜3ともいう)を構成するが、酸化膜3は
パターニングされた活性層基板Aの表面形状にしたがっ
て図示するように凹凸をもった膜として形成される。
First, as shown in FIG. 1A, a photolithography technique or an etching technique is applied to one surface of a semiconductor substrate 1 (hereinafter also referred to as an active layer substrate A or an active layer substrate 1) made of single crystal silicon. By using, for example, the grooves 2 having a depth of 0.1 μm are formed at intervals of 10 μm. This surface is thermally oxidized to form a SiO 2 film having a thickness of 0.01 [mu] m, further, the SiO 2 film by the thermal oxidation, CVD
A SiO 2 film having a thickness of 0.9 μm is formed by the method. These 1.0 μm SiO 2 films are used for the surface layer 3 of the active layer substrate.
The oxide film 3 (hereinafter also referred to as the oxide film 3) is formed as a film having irregularities as shown in the drawing according to the surface shape of the patterned active layer substrate A.

【0022】図1(a)に示す構造に、さらにこの酸化
膜3の表面に接合層としてのポリシリコン膜4を形成す
る(図1(b)参照)。このポリシリコン膜4は、例え
ば、CVD法により、反応温度を800℃〜1200℃
として、厚さ5μmだけ成長させる。高温で反応させて
ポリシリコン膜4を形成するのは、該ポリシリコン膜の
導電性、不純物の拡散速度、膜の安定性、酸化速度等の
特性を高めるためであるが、このポリシリコン層4も、
酸化膜3と同様に、酸化膜3の凹凸形状にしたがって僅
かに凹凸をもった膜として形成される。
In the structure shown in FIG. 1A, a polysilicon film 4 as a bonding layer is further formed on the surface of the oxide film 3 (see FIG. 1B). The polysilicon film 4 has a reaction temperature of 800 ° C. to 1200 ° C., for example, by a CVD method.
As a result, a thickness of 5 μm is grown. The reason why the polysilicon film 4 is formed by reacting at a high temperature is to enhance the properties of the polysilicon film such as conductivity, impurity diffusion rate, film stability, and oxidation rate. Also,
Like the oxide film 3, the oxide film 3 is formed as a film having a slight unevenness according to the uneven shape of the oxide film 3.

【0023】次に、図1(c)に示すように、ポリシリ
コン膜4の表面を研削して、該表面の凹凸を除去する。
この研磨は、いわゆるプロダクト・モード研削(PM
G)であり、例えば、不飽和ポリエステル製クロスに、
高純度シリカの微粒子を分散させたアルカリ溶液を滴下
しつつ、このクロスに研削面であるポリシリコン膜を圧
着させてメカノケミカルポリッシングを施す。
Next, as shown in FIG. 1C, the surface of the polysilicon film 4 is ground to remove irregularities on the surface.
This polishing is the so-called product mode grinding (PM
G), for example, with an unsaturated polyester cloth,
Mechanochemical polishing is performed by dropping an alkaline solution in which fine particles of high-purity silica are dispersed and pressing a polysilicon film, which is a grinding surface, onto this cloth.

【0024】図1(c)に示すようにして、ポリシリコ
ン膜4の表面にプロダクト・モード研削を施してある程
度平坦化すると、研削ダメージが数μm発生する。この
研削ダメージを除去して、張り合わせの接合面を構成す
るポリシリコン膜4の表面4aを鏡面状態にするため
に、図2(d)に示すように、さらに延性モード研削
(ダクタイル・モード研削、DMG)を施す。
As shown in FIG. 1C, when the surface of the polysilicon film 4 is subjected to product mode grinding to be flattened to some extent, grinding damage of several μm occurs. In order to remove this grinding damage and to make the surface 4a of the polysilicon film 4 which constitutes the bonded joint surface into a mirror surface state, as shown in FIG. 2D, ductile mode grinding (ductile mode grinding, DMG) is applied.

【0025】本研削工程では、プロダクト・モード研削
により発生した研削ダメージを除去するだけでよいの
で、その研削量は、数μmである。
In the main grinding step, since the grinding damage generated by the product mode grinding only needs to be removed, the grinding amount is several μm.

【0026】硬脆材料であるポリシリコンを研削する
と、一般的には、クラックをともなう脆性破壊加工とな
り、研削面は破砕面となって鏡面状態の接合面を得るこ
とはできない。しかしながら、このような硬脆材料であ
っても、0.1μmオーダーの微小切込みなど、加工単
位(具体的には加工圧力に起因する)を十分微少な範囲
に限定すると、脆性破壊ではなく塑性域での鏡面研削が
可能となる。
When polysilicon, which is a hard and brittle material, is ground, brittle fracture processing with cracks is generally performed, and the ground surface becomes a crushed surface, and a mirror-like bonded surface cannot be obtained. However, even with such a hard and brittle material, if the processing unit (specifically, due to the processing pressure) is limited to a sufficiently small range such as a micro-cut in the order of 0.1 μm, it is not a brittle fracture but a plastic region. It enables mirror surface grinding.

【0027】この延性モード研削を実現するために最も
重要なパラメータは、脆性破壊と塑性変形破断との遷移
点を表わす臨界加工単位dc(延性・脆性圧力遷移点P
cともいう)であり、かつ、この臨界加工単位は、材料
固有の値である。したがって、まず延性モード研削を施
そうとするポリシリコン膜4の臨界加工単位を求めてお
き、この臨界加工単位以下の押し込み荷重で研削装置を
制御しながら研削を行う。これにより、脆性破壊を生じ
易いポリシリコンであっても塑性的挙動を示すことにな
る。
The most important parameter for realizing this ductile mode grinding is the critical processing unit dc (ductile / brittle pressure transition point P which represents the transition point between brittle fracture and plastic deformation fracture).
Also referred to as c), and the critical processing unit is a value peculiar to the material. Therefore, first, the critical processing unit of the polysilicon film 4 to be subjected to the ductile mode grinding is obtained, and grinding is performed while controlling the grinding device with a pushing load equal to or less than this critical processing unit. As a result, even polysilicon that is prone to brittle fracture exhibits plastic behavior.

【0028】このような延性モード研削を施すと、研削
面4bの研削ダメージは、僅か、0.05μm〜0.2
μm(=500〜2000オングストローム)となる。
When such ductile mode grinding is performed, the grinding damage on the grinding surface 4b is only 0.05 μm to 0.2 μm.
μm (= 500 to 2000 angstrom).

【0029】本発明では、集積度を高めるために、およ
び、この研削面に生じる研削ダメージをさらに緩和する
ために、図2(e)に示すように、研削面4bに第2の
酸化膜7を形成している。この酸化膜7は、例えば、C
VD法または熱酸化法によるSOI絶縁層とするか、ま
たは熱酸化により破砕層を酸化した後、この酸化膜をエ
ッチオフする犠牲酸化膜とする。以上の工程により、S
OI構造ウェ−ハを構成する一方の基板である活性層基
板Aを得る。このとき、SOI構造を構成する接合面7
aは、鏡面状態の研削面4b上に酸化膜7が形成された
構造となっているので、鏡面状態よりさらに平滑性に優
れた面となっている。
In the present invention, the second oxide film 7 is formed on the ground surface 4b as shown in FIG. 2 (e) in order to increase the degree of integration and further alleviate the grinding damage generated on the ground surface. Is formed. This oxide film 7 is, for example, C
The SOI insulating layer is formed by the VD method or the thermal oxidation method, or the sacrificial oxide film is formed by etching off the oxide film after oxidizing the crushed layer by thermal oxidation. Through the above steps, S
An active layer substrate A, which is one of the substrates forming the OI structure wafer, is obtained. At this time, the bonding surface 7 forming the SOI structure
Since a has a structure in which the oxide film 7 is formed on the ground surface 4b in a mirror surface state, the surface a is more smooth than the mirror surface state.

【0030】図2(e)に示す状態で鏡面状態の接合面
7aを得ると、次に、この接合面7aに支持基板Bとな
る他の半導体基板5(以下、支持基板5ともいう)を密
着させ、水素結合により熱接合させて両者を張り合わせ
る(図2(f)参照)。張り合わせ強度は、例えば20
0kg/cm2 以上、張り合わせ温度は1100℃と
し、また、熱膨張差によるSOIウェーハのソリを防止
するために、支持基板5として活性層基板1と同一のシ
リコン基板を用いることが好ましい。
When the bonding surface 7a in a mirror state is obtained in the state shown in FIG. 2 (e), another semiconductor substrate 5 (hereinafter also referred to as the supporting substrate 5) to be the supporting substrate B is next formed on the bonding surface 7a. They are brought into close contact with each other and thermally bonded by hydrogen bonding to bond them together (see FIG. 2 (f)). The bonding strength is, for example, 20
0 kg / cm 2 or more, the bonding temperature is 1100 ° C., and it is preferable to use the same silicon substrate as the active layer substrate 1 as the support substrate 5 in order to prevent warping of the SOI wafer due to the difference in thermal expansion.

【0031】図2(f)に示すように活性層基板Aと支
持基板Bとを張り合わせたのちに、側周部分の面取りな
どを施すとともに、活性層基板1の厚さが約2μmとな
るように予め研削を施しておく。
As shown in FIG. 2 (f), after laminating the active layer substrate A and the supporting substrate B, chamfering of the side peripheral portion is performed and the thickness of the active layer substrate 1 becomes about 2 μm. Grind in advance.

【0032】最後に、図3(g)に示すように、活性層
基板1の選択研削を行う。この選択研削は、例えば、表
面粗さが0.01μmの高純度酸化アルミ製定盤を回転
させ、この定盤の表面に粒度が0.02μmの高純度シ
リカの微粒子を5.0wt%分散させたpH10.5の
アルカリ溶液(研磨液)を滴下しつつ、この定盤表面に
活性層基板1を100g/cm2 の圧力で圧着摩擦させ
ることにより行われる。
Finally, as shown in FIG. 3G, the active layer substrate 1 is selectively ground. In this selective grinding, for example, a high-purity aluminum oxide surface plate having a surface roughness of 0.01 μm is rotated, and 5.0 wt% of fine particles of high-purity silica having a particle size of 0.02 μm are dispersed on the surface of the surface plate. This is performed by dropping the alkaline solution (polishing solution) having a pH of 10.5 and pressingly rubbing the active layer substrate 1 on the surface plate surface at a pressure of 100 g / cm 2 .

【0033】選択研削を行うと、活性層基板1が徐々に
研削されてゆくが、定盤がSiO2からなる酸化膜3ま
で達すると、該酸化膜3は活性層基板1に比べてメカノ
ケミカル研磨され難いので、研削速度が急速に低下す
る。この研削速度を検出することにより、図3(g)に
示すような酸化膜3が活性層基板1の表面から露出した
状態、すなわち、活性層6が酸化膜3で分離され、しか
も、その下層に第2の酸化膜7が積層された状態のSO
I構造ウェーハを得ることができる。
When the selective grinding is performed, the active layer substrate 1 is gradually ground, but when the surface plate reaches the oxide film 3 made of SiO 2 , the oxide film 3 is more mechanochemical than the active layer substrate 1. Since it is difficult to be polished, the grinding speed decreases rapidly. By detecting this grinding speed, the oxide film 3 as shown in FIG. 3 (g) is exposed from the surface of the active layer substrate 1, that is, the active layer 6 is separated by the oxide film 3 and its lower layer. SO with the second oxide film 7 laminated on the
An I structure wafer can be obtained.

【0034】本発明の半導体基板の製造方法は、上述し
た薄膜SOI構造以外にも、例えば、張り合わせ誘電体
分離基板の製造にも適用することができる。
The semiconductor substrate manufacturing method of the present invention can be applied to, for example, manufacturing of a laminated dielectric isolation substrate, in addition to the above-described thin film SOI structure.

【0035】図4〜図6は、本発明の他の実施例に係る
半導体基板の製造方法を説明する断面図であり、図4
(a)は酸化膜形成工程、図4(b)は接合層形成工
程、図4(c)は研削工程、図5(d)は延性モード研
削工程、図5(e)は第2の酸化膜の形成工程、図5
(f)は張り合わせ工程、図5(g)は活性層基板の研
削工程をそれぞれ説明する断面図である。
4 to 6 are sectional views for explaining a method of manufacturing a semiconductor substrate according to another embodiment of the present invention.
4A is an oxide film forming step, FIG. 4B is a bonding layer forming step, FIG. 4C is a grinding step, FIG. 5D is a ductile mode grinding step, and FIG. 5E is a second oxidation step. Membrane forming process, FIG.
FIG. 5F is a cross-sectional view illustrating a laminating step, and FIG. 5G is a cross-sectional view illustrating an active layer substrate grinding step.

【0036】素子間の絶縁耐圧が数十V〜数百Vといっ
た高耐圧のLSIでは、それぞれの素子を酸化膜のよう
な誘電体膜で完全に分離する必要があり、このような技
術分野ではいわゆる誘電体分離基板が広く用いられてい
る。本実施例では、かかる誘電体分離基板の製造方法に
本発明を適用した具体例を示している。
In an LSI having a high withstand voltage of several tens V to several hundreds V between elements, it is necessary to completely separate each element by a dielectric film such as an oxide film. In such a technical field. A so-called dielectric isolation substrate is widely used. In this embodiment, a specific example in which the present invention is applied to the method for manufacturing such a dielectric isolation substrate is shown.

【0037】まず、単結晶シリコンからなる半導体基板
1(以下、活性層基板A、あるいは活性層基板1ともい
う)の片面を酸化して、全面にSiO2 膜を形成したの
ち、このSiO2 膜の予定の箇所を開口し、SiO2
をマスクとして例えば異方性エッチングなどによって、
例えば深さが約60μmの分離溝8を形成する。つい
で、マスクとして利用したSiO2 膜を除去したのち、
再び、半導体基板1の表面を酸化して、その全面に厚さ
1.2μmの絶縁用酸化膜3を形成する(図4(a)参
照)。この酸化膜3は分離溝8が形成された活性層基板
Aの表面形状にしたがって図示するように凹凸をもった
膜として形成される。
First, one side of a semiconductor substrate 1 (hereinafter also referred to as an active layer substrate A or an active layer substrate 1) made of single crystal silicon is oxidized to form a SiO 2 film on the entire surface, and then this SiO 2 film is formed. Is opened at a predetermined location, and the SiO 2 film is used as a mask, for example, by anisotropic etching,
For example, the separation groove 8 having a depth of about 60 μm is formed. Then, after removing the SiO 2 film used as a mask,
The surface of the semiconductor substrate 1 is again oxidized to form an insulating oxide film 3 having a thickness of 1.2 μm on the entire surface (see FIG. 4A). The oxide film 3 is formed as a film having irregularities as shown in the figure according to the surface shape of the active layer substrate A in which the separation groove 8 is formed.

【0038】図4(a)に示す構造に、さらにこの酸化
膜3の表面に接合層としてのポリシリコン膜4を形成す
る(図4(b)参照)。このポリシリコン膜4は、例え
ば、CVD法により、反応温度を800℃〜1200℃
として、少なくとも分離溝8が完全に埋まるまで(例え
ば、厚さ100μm)成長させる。このポリシリコン層
4も、酸化膜3と同様に、酸化膜3の凹凸形状にしたが
って僅かに凹凸をもった膜として形成される。
In the structure shown in FIG. 4A, a polysilicon film 4 as a bonding layer is further formed on the surface of the oxide film 3 (see FIG. 4B). The polysilicon film 4 has a reaction temperature of 800 ° C. to 1200 ° C., for example, by a CVD method.
As a result, the growth is performed until at least the separation groove 8 is completely filled (for example, the thickness is 100 μm). Similar to the oxide film 3, the polysilicon layer 4 is also formed as a film having slight unevenness according to the uneven shape of the oxide film 3.

【0039】次に、図4(c)に示すように、ポリシリ
コン膜4の表面を研削して、該表面の凹凸を除去する。
この研磨は、いわゆるプロダクト・モード研削(PM
G)であり、例えば、不飽和ポリエステル製クロスに、
高純度シリカの微粒子を分散させたアルカリ溶液を滴下
しつつ、このクロスに研削面であるポリシリコン膜を圧
着させてメカノケミカルポリッシングを施す。
Next, as shown in FIG. 4C, the surface of the polysilicon film 4 is ground to remove the irregularities on the surface.
This polishing is the so-called product mode grinding (PM
G), for example, with an unsaturated polyester cloth,
Mechanochemical polishing is performed by dropping an alkaline solution in which fine particles of high-purity silica are dispersed and pressing a polysilicon film, which is a grinding surface, onto this cloth.

【0040】図4(c)に示すようにして、ポリシリコ
ン膜4の表面にプロダクト・モード研削を施してある程
度平坦化すると、研削ダメージが数μm発生する。この
研削ダメージを除去して、張り合わせの接合面を構成す
るポリシリコン膜4の表面4aを鏡面状態にするため
に、図5(d)に示すように、さらに延性モード研削
(ダクタイル・モード研削、DMG)を施す。
As shown in FIG. 4C, when the surface of the polysilicon film 4 is flattened to some extent by performing product mode grinding, grinding damage of several μm occurs. In order to remove this grinding damage and to make the surface 4a of the polysilicon film 4 constituting the bonded joint surface into a mirror surface state, as shown in FIG. 5D, ductile mode grinding (ductile mode grinding, DMG) is applied.

【0041】本研削工程では、プロダクト・モード研削
により発生した研削ダメージを除去するだけでよいの
で、その研削量は、少なくとも数μmである。
In the main grinding step, since it is only necessary to remove the grinding damage caused by the product mode grinding, the grinding amount is at least several μm.

【0042】本実施例では、集積度を高めるために、お
よび、この研削面に生じる研削ダメージをさらに緩和す
るために、図5(e)に示すように、研削面4bに第2
の酸化膜7を形成している。この酸化膜7は、例えば、
CVD法または熱酸化法によるSOI絶縁層とするか、
または熱酸化により破砕層を酸化した後、この酸化膜を
エッチオフする犠牲酸化膜とする。以上の工程により、
SOI構造ウェ−ハを構成する一方の基板である活性層
基板Aを得る。このとき、SOI構造を構成する接合面
7aは、鏡面状態の研削面4b上に酸化膜7が形成され
た構造となっているので、鏡面状態よりさらに平滑性に
優れた面となっている。
In this embodiment, in order to increase the degree of integration and to further reduce the grinding damage that occurs on this ground surface, as shown in FIG.
Oxide film 7 is formed. This oxide film 7 is, for example,
An SOI insulating layer formed by CVD or thermal oxidation,
Alternatively, after the fractured layer is oxidized by thermal oxidation, this oxide film is used as a sacrificial oxide film that is etched off. By the above process,
An active layer substrate A, which is one of the substrates forming the SOI structure wafer, is obtained. At this time, since the bonding surface 7a forming the SOI structure has a structure in which the oxide film 7 is formed on the ground surface 4b in a mirror surface state, the bonding surface 7a is more smooth than the mirror surface state.

【0043】なお、図5(d)に示すように、本実施例
ではポリシリコン膜4を酸化膜3の表面から僅かに残す
ようにプロダクト・モード研削とダクタイル・モード研
削を行うが、目的とする誘電体分離ウェーハによって
は、ポリシリコン膜4を酸化膜3の表面が露出するまで
研削するようにしてもよい。
As shown in FIG. 5D, in this embodiment, the product mode grinding and the ductile mode grinding are performed so that the polysilicon film 4 is slightly left from the surface of the oxide film 3. Depending on the dielectric isolation wafer, the polysilicon film 4 may be ground until the surface of the oxide film 3 is exposed.

【0044】図5(e)に示す状態で鏡面状態の接合面
7bを得ると、次に、この接合面7bに支持基板Bとな
る他の半導体基板5(以下、支持基板5ともいう)を密
着させ、水素結合により熱接合させて両者を張り合わせ
る(図6(f)参照)。張り合わせ強度は、例えば20
0kg/cm2 以上、張り合わせ温度は1100℃と
し、また、熱膨張差によるSOIウェーハのソリを防止
するために、支持基板5として活性層基板1と同一のシ
リコン基板を用いることが好ましい。
When the mirror-bonded bonding surface 7b is obtained in the state shown in FIG. 5 (e), another semiconductor substrate 5 (hereinafter also referred to as the supporting substrate 5) to be the supporting substrate B is next formed on this bonding surface 7b. They are brought into close contact with each other and thermally bonded by hydrogen bonding to bond them together (see FIG. 6 (f)). The bonding strength is, for example, 20
0 kg / cm 2 or more, the bonding temperature is 1100 ° C., and it is preferable to use the same silicon substrate as the active layer substrate 1 as the support substrate 5 in order to prevent warping of the SOI wafer due to the difference in thermal expansion.

【0045】図6(f)に示すように活性層基板Aと支
持基板Bとを張り合わせたのちに、側周部分の面取りな
どを施すとともに、活性層基板1の厚さが約2μmとな
るように予め研削を施しておく。
As shown in FIG. 6 (f), after laminating the active layer substrate A and the supporting substrate B, chamfering of the side peripheral portion is performed and the thickness of the active layer substrate 1 becomes about 2 μm. Grind in advance.

【0046】最後に、図4(g)に示すように、活性層
基板1の選択研削を行う。この選択研削は、例えば、表
面粗さが0.01μmの高純度酸化アルミ製定盤を回転
させ、この定盤の表面に粒度が0.02μmの高純度シ
リカの微粒子を5.0wt%分散させたpH10.5の
アルカリ溶液(研磨液)を滴下しつつ、この定盤表面に
活性層基板1を100g/cm2 の圧力で圧着摩擦させ
ることにより行われる。
Finally, as shown in FIG. 4G, the active layer substrate 1 is selectively ground. In this selective grinding, for example, a high-purity aluminum oxide surface plate having a surface roughness of 0.01 μm is rotated, and 5.0 wt% of fine particles of high-purity silica having a particle size of 0.02 μm are dispersed on the surface of the surface plate. This is performed by dropping the alkaline solution (polishing solution) having a pH of 10.5 and pressingly rubbing the active layer substrate 1 on the surface plate surface at a pressure of 100 g / cm 2 .

【0047】選択研削を行うと、活性層基板1が徐々に
研削されてゆくが、定盤がSiO2からなる酸化膜3ま
で達すると、該酸化膜3は活性層基板1に比べてメカノ
ケミカル研磨され難いので、研削速度が急速に低下す
る。この研削速度を検出することにより、図4(g)に
示すような酸化膜3が活性層基板1の表面から露出した
状態、すなわち、活性層6が誘電体である酸化膜3で完
全に分離された状態の誘電体分離ウェーハを得ることが
できる。
When the selective grinding is performed, the active layer substrate 1 is gradually ground. However, when the surface plate reaches the oxide film 3 made of SiO 2 , the oxide film 3 is more mechanochemical than the active layer substrate 1. Since it is difficult to be polished, the grinding speed decreases rapidly. By detecting this grinding speed, the oxide film 3 as shown in FIG. 4G is exposed from the surface of the active layer substrate 1, that is, the active layer 6 is completely separated by the oxide film 3 which is a dielectric. It is possible to obtain the dielectrically separated wafer in the separated state.

【0048】なお、上述した実施例は、本発明を説明す
るための一つの具体例であって、説明中に示された製造
条件等の諸条件は、本発明の技術的範囲を減縮させるも
のではない。
The above-described embodiment is one specific example for explaining the present invention, and various conditions such as manufacturing conditions shown in the description reduce the technical scope of the present invention. is not.

【0049】[0049]

【発明の効果】以上述べたように本発明によれば、活性
層基板と支持基板とを張り合わせるための接合層を延性
モード研削により研削し、この研削面に酸化膜を形成し
て鏡面状態の接合面を形成するようにしているので、従
来、接合面を平坦化するために形成していた接合層を多
層構造とする必要がなく、これによって、張り合わせの
ための接合層の形成工程と、この接合層の研削・研磨工
程を簡略化することが可能となる。その結果、半導体基
板の製造コストを低減することができるとともに、工程
の簡略化にともなって品質管理も容易になる。
As described above, according to the present invention, the bonding layer for bonding the active layer substrate and the supporting substrate is ground by ductile mode grinding, and an oxide film is formed on the ground surface to form a mirror surface state. Since the joint surface is formed as described above, it is not necessary to form the joint layer, which has been conventionally formed to flatten the joint surface, into a multi-layer structure. It is possible to simplify the grinding / polishing process of the bonding layer. As a result, the manufacturing cost of the semiconductor substrate can be reduced, and the quality control is facilitated as the process is simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(c)は本発明の一実施例に係る半導
体基板の製造方法を説明する断面図である。
1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

【図2】(d)〜(f)は図1に示す製造方法の続きを
示す断面図である。
2 (d) to (f) are sectional views showing the continuation of the manufacturing method shown in FIG.

【図3】(g)は図2に示す製造方法の続きを示す断面
図である。
3G is a sectional view showing a sequel to the manufacturing method shown in FIG. 2; FIG.

【図4】(a)〜(c)は本発明の他の実施例に係る半
導体基板の製造方法を説明する断面図である。
4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to another embodiment of the present invention.

【図5】(d)〜(e)は図4に示す製造方法の続きを
示す断面図である。
5 (d) to (e) are cross-sectional views showing a continuation of the manufacturing method shown in FIG.

【図6】(f)〜(g)は図5に示す製造方法の続きを
示す断面図である。
6F to 6G are cross-sectional views showing the continuation of the manufacturing method shown in FIG.

【図7】(a)〜(c)は従来の半導体基板の製造方法
を説明する断面図である。
7A to 7C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor substrate.

【図8】(d)〜(f)は図7に示す製造方法の続きを
示す断面図である。
8D to 8F are cross-sectional views showing the continuation of the manufacturing method shown in FIG.

【図9】(g)〜(h)は図8に示す製造方法の続きを
示す断面図である。
9 (g) to (h) are sectional views showing the continuation of the manufacturing method shown in FIG.

【符号の説明】[Explanation of symbols]

A…活性層基板 B…支持基板 1…活性層基板側のシリコン基板 3…表面層(酸化膜) 4…接合層 5…支持基板側のシリコン基板 6…活性層 7…第2の酸化膜 7a…接合面 8…分離溝 A ... Active layer substrate B ... Support substrate 1 ... Active layer substrate side silicon substrate 3 ... Surface layer (oxide film) 4 ... Bonding layer 5 ... Support substrate side silicon substrate 6 ... Active layer 7 ... Second oxide film 7a … Joining surface 8… Separation groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一方の半導体基板の少なくとも片面に接合
層を形成し、該接合層を研磨して接合面を形成したの
ち、該接合面に他方の半導体基板を張り合わせてSOI
構造の半導体基板を作製する製造方法において、 前記接合層を延性モード研削により研削して鏡面状態の
研削面を形成したのち、この研削面に酸化膜を形成する
ことを特徴とする半導体基板の製造方法。
1. A bonding layer is formed on at least one surface of one semiconductor substrate, the bonding layer is polished to form a bonding surface, and the other semiconductor substrate is bonded to the bonding surface.
In a manufacturing method for manufacturing a semiconductor substrate having a structure, the bonding layer is ground by ductile mode grinding to form a ground surface in a mirror surface state, and then an oxide film is formed on the ground surface. Method.
JP4273750A 1992-09-17 1992-09-17 Semiconductor substrate manufacturing method Expired - Fee Related JP2866263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4273750A JP2866263B2 (en) 1992-09-17 1992-09-17 Semiconductor substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4273750A JP2866263B2 (en) 1992-09-17 1992-09-17 Semiconductor substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPH06104413A true JPH06104413A (en) 1994-04-15
JP2866263B2 JP2866263B2 (en) 1999-03-08

Family

ID=17532059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4273750A Expired - Fee Related JP2866263B2 (en) 1992-09-17 1992-09-17 Semiconductor substrate manufacturing method

Country Status (1)

Country Link
JP (1) JP2866263B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08340046A (en) * 1995-06-13 1996-12-24 Nec Corp Manufacture of semiconductor device
JP2010278160A (en) * 2009-05-27 2010-12-09 Shin Etsu Handotai Co Ltd Method for manufacturing soi wafer, and soi wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08340046A (en) * 1995-06-13 1996-12-24 Nec Corp Manufacture of semiconductor device
JP2010278160A (en) * 2009-05-27 2010-12-09 Shin Etsu Handotai Co Ltd Method for manufacturing soi wafer, and soi wafer

Also Published As

Publication number Publication date
JP2866263B2 (en) 1999-03-08

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