JPH0586674B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to the structure of a common electrode portion of a complementary thin film transistor circuit (hereinafter referred to as a thin film CMOS circuit) composed of thin film transistors (hereinafter referred to as TFT). be.

[Prior art]

N-type MOS formed on conventional silicon wafer
In a CMOS circuit composed of transistors and P-type MOS transistors, when forming each transistor on the same wafer, a P-type well is formed when an N-type wafer is used, and an N-type well is formed when a P-type wafer is used. After that, MOS transistors are formed separately in the well part and the non-well part in the wafer,
The common electrode area is connected with a conductive material such as aluminum to form a CMOS structure. This method always requires a wafer of a different type from the wafer, and two There were limitations in terms of the need for point contacts and the reduction in the distance between transistors, which caused problems in advancing miniaturization.

〔the purpose〕

The present invention solves these problems,
The purpose is to add N-type to the same semiconductor.
By forming TFTs and P-type TFTs to construct thin film CMOS circuits, the transistor spacing can be reduced and the common electrode can be made as a single contact.
The goal is to miniaturize CMOS circuits.

〔overview〕

The present invention is characterized in that a common electrode portion of a thin film CMOS circuit constituted by an N-type thin film transistor and a P-type thin film transistor is formed in the same semiconductor, and the electrode is formed by a unique contact.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

In the explanation, an inverter, which is a basic circuit, will be used as the circuit. FIG. 1 shows an inverter fabricated on a conventional silicon wafer, and FIG. 2 shows an inverter made of TFT. 1a and 2a are top views of the inverter, and FIGS. 1b and 2b are sectional views taken along AA' and BB', respectively.

The difference in structure and manufacturing between the CMOS circuits shown in FIG. 1 and FIG. 2 is that in the thin film CMOS circuit (FIG. 2b), an N-type Forming source and drain regions of TFT and P-type TFT;
Furthermore, among the electrodes of the N-type transistor and the P-type transistor, the common electrode (drain electrode and gate electrode in the figure) is taken out from the drain region of both transistors by the only contact. It is that you are.

Next, we will explain the manufacturing method of thin film CMOS circuits.

A semiconductor layer 12 is formed on an insulating substrate 11, etched into a suitable shape, and then a gate film is formed.
Next, a gate electrode 17 is formed by impurity diffusion after the semiconductor layer is formed or by using a highly conductive material, and an N-type gate electrode 17 is formed.
The source and drain regions of the TFT and P-type TFT are formed by ion implantation with an impurity ion beam. The source and drain regions are located on one side.
Mask the TFT with resist, etc., and turn it into an N-type TFT.
and P-type TFT. As shown in FIG. 2b, the source and drain regions of both transistors are formed in the same semiconductor layer, and in particular, the drain regions are made sufficiently close to each other between both transistors.
The structure is as shown in 4.15. Next, after forming an interlayer insulating layer 18, contact is made with a conductive material to form an inverter.

In addition, in FIG. 3, although the fabrication method is as described above, a common drain electrode is taken out from the overlap region 15 where P-type and N-type impurities coexist in the drain region formed by ion implantation etc. FIG.

The structure shown in FIG. 4 is manufactured in the same manner as described above except for the method of forming the source region and drain region. When implanting impurities into the source and drain regions, first implant N-type impurities or P-type impurities into the entire surface of the source and drain regions. P-type TFT
are masked with a resist or the like, and the opposite type impurity is implanted to form source and drain regions of an N-type TFT and a P-type TFT. Therefore,
Of the contacting regions 13 and 14, the region formed later by impurity implantation contains both N-type impurities and P-type impurities.

As described above, according to the present invention, thin film CMOS
By forming the source and drain regions of each N-type TFT and P-type TFT in the same semiconductor thin film, it is possible to significantly reduce the transistor spacing, allowing for miniaturization of the thin-film CMOS circuit itself and thin-film CMOS circuits. This has a great effect on increasing the degree of integration of integrated circuits using this method.

In addition, since the source region and drain region are formed in polycrystalline or amorphous non-single crystal layers,
Restrictions on the flow of carriers due to contact between the P-type region and the N-type region are relaxed compared to when forming a single crystal, and output can be sufficiently extracted by the common electrode.

In the configuration shown in Figure 4, there is also an N-type TFT and a P-type TFT.
Since the structure of the TFT boundary region is simplified, further miniaturization can be achieved compared to the case of FIG. 2.

[Effects of the Invention] By employing such a configuration, the present invention achieves the following remarkable effects.

(a) Even if source/drain regions of a P-type TFT and an N-type TFT are formed in a non-single crystal semiconductor layer, and a PN junction region is formed by directly contacting each drain region to obtain output, the Because current leaks along the crystal grain agglomerates in the single crystal semiconductor layer or through crystal defects in the crystal, the remarkable diode characteristics of the PN junction when formed using a single crystal semiconductor are Not shown. Therefore, a P-type TFT and an N-type TFT can be directly connected through a PN junction, there is no need to separate the P-type source/drain region from the N-type source/drain region, and it is also possible to connect a separate contact to each drain region. Since it is no longer necessary to provide a CMOS circuit with non-single-crystal thin film transistors, it is possible to significantly reduce the distance between transistors, making it possible to miniaturize the thin film CMOS circuit itself and increase the integration density of integrated circuits using thin film CMOS circuits. It has extremely significant effects.

(b) Since the source/drain regions are formed in a non-single crystal semiconductor thin film, the control of carrier flow due to contact between the P-type region and the N-type region is relaxed compared to when the source/drain regions are formed in a single crystal; Sufficient contact can be made by drawing out the electrode from the substrate.

That is, P-type in the non-single crystal semiconductor thin film.
Even if a region is formed in which the drains of the TFT and the N-type TFT are in contact, sufficient contact can be made because the leakage current is large in this region as described above.

[Brief explanation of the drawing]

Figure 1 shows the structure of a conventional CMOS inverter.
FIG. 2 shows a thin film CMOS inverter. In both figures, a is a top view and b is a cross-sectional view. FIG. 3 is a diagram showing a structure in which the contact position of the drain electrode is extracted from the overlapping portion of the drain in FIG. 2. FIG. 4 shows the structure of a thin film CMOS inverter in which the drain and source regions are formed in different ways. 1... Silicon wafer, 2... Well, 3...
Source (right) and drain (left) regions, 4...
Source (left) and drain (right) regions, 5...
Gate film, 6... Gate electrode, 7... Insulating film, 8
... Output line (drain electrode), 9 ... Power supply line (source electrode), 10 ... Input line (gate electrode), 11 ... Insulating substrate, 12 ... Semiconductor layer,
13... Source (right) and drain (left) region, 14... Source (left) and drain (right)
Area, 15... Drain overlap area, 16...
Gate film, 17... Gate electrode, 18... Insulating film, 19... Output line (drain electrode), 20
...Power line (source electrode), 21...Input line (gate electrode).

Claims (1)

[Claims] 1. Two thin film transistors formed in an island-shaped semiconductor layer provided on an insulating substrate, one thin film transistor having a first conductivity type region as a source and drain region, and the other thin film transistor having a first conductivity type region as a source and drain region. A complementary thin film transistor circuit comprising two thin film transistors each having a second conductivity type region as a source and a drain region, the semiconductor layer being a non-single crystal layer, one of the first conductivity type regions and the second conductivity type region. A complementary thin film transistor circuit comprising: a contact region that is in direct contact with one of the conductivity type regions; and a common electrode formed on the contact region and from which an output of the complementary thin film transistor circuit is taken out. 2. The contact region includes an impurity of a first conductivity type and an impurity of a second conductivity type.
2. The complementary thin film transistor circuit according to claim 1, wherein at least a portion thereof has a region in which conductive type impurities are mixed.