JPH0582786A - MOS type transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] Turn-off of an element that switches a current flowing between both electrodes provided facing both main surfaces of a semiconductor substrate by a gate electrode provided on one main surface through an insulating film. Speed up. Constitution: The conductivity type of the portion above the channel portion of the gate electrode and the other portion is changed, and a PN junction therebetween prevents current from flowing into the portion above the channel portion at the time of turning off, By connecting a coil to the gate electrode portion other than that and delaying the discharge of the electric charge from that portion, the electric charge of the gate electrode portion on the channel portion is promptly removed and the switching speed is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type in which a current flowing between both electrodes provided on both main surfaces of a semiconductor substrate is switched by a gate electrode provided on one main surface via an insulating film. Regarding transistors.

[0002]

2. Description of the Related Art A MOS field effect transistor (MOS) is used as a power switching element capable of voltage-driving a current flowing between both electrodes provided on both main surfaces of a semiconductor substrate.
FET) or insulated gate bipolar transistor
(IGBT) has become popular.

FIG. 2 shows the basic structure of a vertical MOSFET. That is, the P region 3 is selectively formed in the surface layer of the low impurity concentration N ⁻ layer 2 stacked on the N ⁺ layer 1,
Further, an N ⁺ source region 4 is selectively formed in the surface layer of the P region 3, and a portion of the surface portion of the P region 3 sandwiched by the N ⁻ layer 2 and the N ⁺ source region 4 is a channel. It will be Part 5. A gate electrode 7 made of polycrystalline silicon is provided from above the channel portion to above the exposed portion of the N ⁻ layer via a gate insulating film 6. The surface of the gate electrode 7 is covered with the oxide film 8, but a part thereof is removed by etching, and the gate connection electrode 11 is in contact therewith. The emitter electrode 9 insulated from the gate electrode 7 by the oxide film 8 is in common contact with the P region 3 and the N ⁺ source region 4, and the collector electrode 10 is provided on the opposite surface of the N ⁺ substrate 1. Are in contact.

In this device, the emitter electrode 9 is grounded, and a positive voltage is applied to the collector electrode 10 while the gate electrode 7 is being applied.
When a voltage higher than the threshold voltage is applied to the channel section 5,
Are inverted from P-type to N-type, and electrons are inverted from the emitter electrode 9 to the N ⁺ source region 4 and the channel portion 5, N ^−.
It becomes conductive by flowing into the collector electrode 10 through the layer 2 and the N ⁺ layer 1. On the other hand, when a voltage equal to or lower than the threshold voltage is applied to the gate electrode 7, the inversion of the channel portion 5 does not occur, so that the conduction state is not established. In the case of the IGBT, the P ⁺ layer is used instead of the N ⁺ layer 1 and the N ⁻ layer 2 is turned on when the IGBT is turned on.
Conductivity modulation is caused to lower the on-voltage.

The method of manufacturing the semiconductor device shown in FIG. 2 is performed in the following procedure. After a gate insulating film 6 and a polycrystalline gate electrode 7 are formed on the surface of a silicon wafer obtained by laminating an N ⁻ epitaxial layer 2 on an N ⁺ substrate 1, these two layers are patterned by selective etching. The P diffusion region 3 is formed by ion-implanting the acceptor impurity through the removed portion by the etching and thermally diffusing it. Further, the donor impurity is ion-implanted by using the gate electrode 7 as a mask to thermally diffuse the N ⁺ source region 4
To form. After that, an oxide insulating film 8 such as PSG serving as an interlayer insulating film is deposited, and a window is opened so that the gate electrode is not exposed. At this time, the N ⁺ source region is etched by using the mask used for the selective etching again to expose the P region 3. Next, the oxide insulating film 8 is over-etched to expose the N ⁺ source region 4. The oxide insulating film 8 is partially removed so that the gate electrode 7 and the gate connection electrode 11 will come into contact with each other later. Then, the emitter electrode 9 and the gate connection electrode 11 are formed by depositing aluminum by vapor deposition and patterning. Finally, metal is vapor-deposited on the opposite surface of the N ⁺ substrate 1 to complete the collector electrode 10.

[0006]

In recent years, as a demand for a MOS type transistor, development of an element capable of high-speed switching has been demanded in order to miniaturize the device. To that end, it is important to reduce the capacitance between the gate, emitter, and collector electrodes, and especially to reduce the capacitance between the gate and collector. Although the MOS type transistor is a voltage drive type element which is operated by applying a positive or negative voltage to the gate electrode as described above, charge and discharge of electric charges are required to fix the gate to a certain potential. The charge / discharge speed is determined by the time constant determined by the capacitance C between the gate electrode and the other electrodes and the resistance R between the gate electrode and the gate drive circuit, and this speed is an important factor for determining the switching speed of the device. As measures against this, there are reductions in capacitance C and reduction in gate resistance R. However, in order to reduce capacitance C, thickening the gate oxide film and narrowing the area of the portion that affects capacitance are both on. Increase the voltage and
The reduction of resistance R is reaching the limit at the current development stage.

An object of the present invention is to solve the above problems and provide a MOS transistor capable of high speed switching.

[0008]

To achieve the above object, the present invention provides a second conductivity type second layer selectively formed in a surface layer of a first region of the first conductivity type of a semiconductor substrate. Area and a third area of the first conductivity type selectively formed in the surface layer of the second area, and on the portion sandwiched between the first area and the third area of the second area surface portion. To a exposed region of the first region through a gate insulating film, and a MOS transistor having an emitter electrode insulated from the gate electrode and commonly contacting the second region and the third region, At least a portion of the gate electrode on the exposed surface of the first region is a first conductivity type, the remaining portion is a second conductivity type, the gate terminal directly to the first conductivity type portion of the gate electrode, Connected to the second conductivity type part via a coil To. It is effective that the gate electrode is made of polycrystalline silicon. It is also effective that the coil is formed of a conductor layer with the surface of the semiconductor substrate and an insulating film interposed.

[0009]

In order to simplify the description, the operation of the present invention will be described below for an N-channel MOS type transistor, that is, a MOS type transistor in which the first conductivity type is N type and the second conductivity type is P type. In that case, of the gate electrode, the portion above the channel is P-type, and the portion above the exposed surface of the first region is N-type. A coil is connected to the N-type portion. When turning off the element, it is necessary to apply a negative voltage to the gate electrode to remove positive charges from the gate electrode. In the conventional device, the electric charge of all the gate electrodes was removed at the same time, but in reality, when the current cannot be conducted even in a part of the passage, the current stops flowing. It is not necessary to instantly remove all the charges when turned off, and if only the charges of the gate electrode on the channel portion are surely instantly removed, the device turns off. In the case of this element, since the P-type portion in the gate electrode is directly connected to the gate circuit, the discharge ends immediately and the element turns off. However, since the coil is connected to the N-type portion, the current is delayed. Also, since it is in the opposite direction to the P-type part, it cannot flow around this part.
As a result, the N-type portion of the gate electrode is slowly discharged after the element is turned off, and finally has the same potential as the P-type portion. At the time of the on-operation, a delay occurs at the coil, but this time the junction between the p-type part and the n-type part is in the forward direction, so a current flows from the p-type to the n-type, and the on-operation is quickly performed. The same operation is performed in a P-channel MOS type transistor in which the conductivity types are exchanged and the polarity of the applied voltage is opposite.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawing in which the same reference numerals are given to the same parts as in FIG.

In the embodiment shown in FIG. 1, of the polycrystalline silicon gate electrode, a portion 71 having a channel portion below is a P-type and the other portion 72 is an N-type, which is a P-type. The part 71 is directly connected to the gate terminal 12, and the N-type part 72 is connected through the coil 13. In order to manufacture this N-channel vertical MOSFET, first, the surface of a silicon wafer having a low impurity concentration N ^- epitaxial layer 2 grown on a high impurity concentration N ⁺ substrate 1 has a thickness of 1000Å.
The gate oxide film 6 is oxidized to some extent. Next, polycrystalline silicon to be a gate electrode is deposited to a thickness of about 1 μm. Although a polycrystalline silicon gate electrode is usually N-type by introducing a single impurity in a large amount of about 1 × 10 ²⁰ / cm ³ so as to lower the resistance, a P-N junction is formed according to the present invention. Part 71 and N part 72 are covered with a protective film on each side, and each impurity is introduced to about 1 × 10 ¹⁹ / cm ³ by ion implantation or diffusion from the surface, activated by thermal diffusion and PN junction. Forming a gate electrode. The gate oxide film 6 and the gate electrodes 71 and 72 are etched using the same mask. Boron as an acceptor impurity is ion-implanted through the window formed at this time with a dose amount of about 1 × 10 ¹⁴ / cm ² to perform thermal diffusion to form a P diffusion region 3 having a depth of about 3 μm. Arsenic was used as a donor impurity at 1 × 10
Ions are implanted with a dose amount of about ¹⁵ / cm ² and thermal diffusion is performed to form an N ⁺ source region 4 having a depth of about 0.2 μm. Further, an interlayer insulating film 8 made of PSG, SPSG, or the like is deposited on the surface to a thickness of about 1 μm, and contact holes are opened to the extent that the gate electrodes 71 and 72 are not exposed. Using the photomask used at this time again, silicon is etched to form a recess, and the side surface of the N ⁺ source region 4 is exposed. Then, when the insulating film 8 is over-etched and the resist used at this time is removed, the surface of the P diffusion region 3 is also exposed. In the oxide insulating film 8, the gate electrodes 71 and 72 are connected to the gate connection electrode 11
Open a contact hole for connecting the. After that, a metal such as aluminum is deposited by vapor deposition, and unnecessary portions are removed by etching, whereby the gate connection electrode 11 and the emitter electrode 9 can be separated.

Although the coil 13 may be provided as a separate component externally, as shown in FIG. 3, a polycrystalline silicon layer 23 formed on the surface of the semiconductor substrate 21 of the device via an oxide film 22 and a polycrystalline silicon layer 23. It can also be formed by an aluminum layer 26 which is in contact with a contact hole 25 formed in the interlayer insulating film 24, one end of which is a gate connection electrode 11 which is in contact with the N-type gate electrode 72, and the other end is a gate terminal 12. Just connect.

FIG. 4 is an IGB having a surface structure similar to that of FIG.
The difference is that at T, the P ⁺ substrate 14 is used instead of the N ⁺ substrate 1. This IGB
The same effect can be obtained with T.

In the above embodiments, the N-channel type element in which the P-type channel portion is inverted by applying the voltage to the gate electrode has been described. However, the same operation is performed in the P-channel type element in which the conductivity type of each portion is reversed. The same effect can be obtained.

[0015]

According to the present invention, a PN junction is formed between a portion of the gate electrode on the semiconductor substrate other than the portion on the channel portion and a portion on the channel portion, and the voltage applied to the gate electrode when off is Reverse bias the PN junction,
When turned off, the charge on the gate electrode on the channel part is immediately discharged, and the charge on the remaining part where the coil is connected is discharged later, so that the charge in the gate electrode can be turned off. The discharge was started quickly, and a MOS type transistor with an improved switching speed could be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a vertical MOSFET according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional vertical MOSFET.

FIG. 3 shows an embodiment having a coil formed on a semiconductor substrate, (a) is a plan view, (b) is a sectional view taken along line AA of (a).

FIG. 4 is a sectional view of an IGBT according to another embodiment of the present invention.

[Explanation of symbols]

1 N ⁺ substrate 2 N ^- low impurity concentration layer 3 P region 4 N ⁺ source region 5 channel unit 6 the gate oxide film 71 P-type gate electrode 72 N-type gate electrode 8 interlayer insulating film 9 emitter electrode 10 collector electrode 11 gate connection Electrode 12 Gate terminal 13 Coil 14 P ⁺ Substrate

Claims (3)

[Claims] 1. A second region of a second conductivity type selectively formed in a surface layer of a first region of a first conductivity type of a semiconductor substrate and a surface region of the second region of the second region of a second conductivity type. The third region of the first conductivity type is provided, and is provided through the gate insulating film from above the portion sandwiched between the first region and the third region of the surface of the second region to the exposed surface of the first region. A gate electrode provided with the emitter electrode and an emitter electrode insulated from the gate electrode and commonly contacting the second region and the third region,
At least a portion of the gate electrode on the exposed surface of the first region is a first conductivity type, the remaining portion is a second conductivity type, the gate terminal directly to the first conductivity type portion of the gate electrode, A MOS transistor characterized in that it is connected to a portion of the second conductivity type through a coil. 2. The MOS transistor according to claim 1, wherein the gate electrode is made of polycrystal. 3. The MOS transistor according to claim 1, wherein the coil is formed of a conductor layer having a semiconductor substrate and an insulating film interposed therebetween.