JPH0582754A - Semiconductor device having double-layer structure and static ram - Google Patents

Abstract

PURPOSE:To suppress a leakage current and secure an ON current by a method wherein a drain region having an offset structure is formed and the electrode layers of a double-layer gate electrode overlap each other partially. CONSTITUTION:A first gate 14 is formed on the upper surface of a junction forming layer 12 provided on a substrate 11 with a first insulating layer 13 therebetween. A second gate 16 is formed so as to overlap the first gate 14 partially with a second insulating layer 15 therebetween. Further, the part of the junction forming layer 12 beneath the part of the second gate 16 which not overlap the first gate 14 is used as an offset region 19. A drain region 17 is formed in the junction forming layer 12 on the offset region 19 side with respect to the first gate 14 and a source region 20 is formed in the junction forming layer 12 on the side opposite to the side of the offset region 19 with respect to the first gate 14. Further, the load element of the memory cell of an SRAM is composed of the above described double-layer gate structure semiconductor device 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a two-layer gate structure and a static RAM in which a load element of an inverter of a laminated static RAM is formed of a semiconductor device having a two-layer gate structure.

[0002]

2. Description of the Related Art In a high-density static RAM (hereinafter referred to as SRAM) having a storage capacity of 4 Mbits or more, a cell portion (flip-flop portion) formed of a high resistance load element made of polycrystalline silicon has a laminated structure. It is becoming more and more thin film transistors. The SRAM in which the cell portion is formed of a thin film transistor having a laminated structure has a drawback that a thin film transistor made of polycrystalline silicon has a large leak current. Therefore, in order to eliminate this drawback, for example, an offset region is formed on the gate electrode side of the drain region to relax the electric field in the vicinity of the drain and reduce the leak current. Generally, the longer the offset length of the offset region, the more the electric field is relaxed.

[0003]

However, when the offset length becomes long, the offset resistance becomes large and the transconductance gm of the thin film transistor deteriorates, so that the ON current becomes small. Therefore, the operation of the thin film transistor becomes slow. Further, when the above-mentioned thin film transistor is used as a load element of an SRAM inverter, the operation performance of the SRAM is deteriorated because the operation of the thin film transistor becomes slow.

It is an object of the present invention to provide a semiconductor device having a two-layer gate structure which is excellent in operation performance and a static RAM using the semiconductor device having the two-layer gate structure as a load element of an inverter.

[0005]

SUMMARY OF THE INVENTION The present invention is a semiconductor device having a two-layer gate structure and a static RAM made to achieve the above object. That is, the first gate is formed on the upper surface of the junction forming layer provided on the substrate through the first insulating layer, and a part of the first gate is overlaid through the second insulating layer that covers the first gate. A second gate is formed in the wrapped state. Further, a junction forming layer below the second gate which does not overlap the first gate is used as an offset region, and a drain region is formed in the junction forming layer on the offset region side with respect to the first gate, and the opposite side thereof is formed. Formed by forming a source region in the junction forming layer of
The semiconductor device has a layered gate structure.

Alternatively, a first gate is formed on a substrate, and a first insulating layer, a junction forming layer, and a second insulating layer are laminated and formed so as to cover the first gate. Further, a second gate is formed on the upper surface of the second insulating layer so as to overlap a part of the first gate. The junction forming layer below the second gate, which does not overlap the first gate, is used as an offset region, and the drain region is formed in the junction forming layer on the offset region side with respect to the first gate. Is a semiconductor device having a two-layer gate structure formed by forming a source region in the junction forming layer.

Further, the load element of the inverter of the static RAM in which the memory cell is constituted by the flip-flop composed of a pair of inverters is formed by the semiconductor device having any one of the above two-layer gate structure.

[0008]

In the semiconductor device having the double-layered gate structure of each of the above structures, the drain voltage is relaxed at the first gate by forming the second gate so as to partially overlap the first gate. At the same time, the gate voltage is relaxed to reduce the leak current. Further, a decrease in ON current is prevented by turning ON the second gate. In the SRAM using the semiconductor device having the two-layer gate structure having the above action as the load element of the inverter, the electric field is relaxed in the offset region and the leak current is reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view shown in FIG. As shown in the figure, a junction forming layer 12 made of, for example, polycrystalline silicon is formed on the upper surface of the substrate 11. A first insulating layer 13 made of SiO ₂ is formed on the upper surface of the bonding forming layer 12. Furthermore the first
On the upper surface of the insulating layer 13 of
Gate 14 is formed. A second insulating layer 15 is formed on the upper surface of the first insulating layer 13 so as to cover the first gate 14. The second gate 16 is formed on the second insulating layer 15 so as to overlap the one side 14a of the first gate 14.

The end 16a of the second gate 16 on the side where the first gate 14 does not overlap is lower than the position 12a of the junction forming layer 12 where the end 16a of the second gate 16 is lowered. In the junction forming layer 12, for example, a drain region 17 in which boron fluoride (BF ₂ ⁺ ) is ion-implanted is formed. Therefore, the junction forming layer 12 below the first gate 14 becomes the channel 18,
The junction forming layer 12 between the drain region 17 and the drain region 17 becomes the offset region 19. In the junction formation layer 12 on the side opposite to the first gate 14 side from the one end 14b of the first gate 14 on the side where the second gate 16 does not overlap,
For example, the source region 20 in which boron fluoride (BF ₂ ⁺ ) is ion-implanted is formed.

A semiconductor device 1 having a two-layer gate structure having the above structure
At 0, a portion of the second gate 16 is the first gate 14
Since the first gate 14 is formed to be overlapped with the first gate 14, the drain voltage is relaxed and the gate voltage is also relaxed, so that the leak current is reduced. Further, the decrease of the ON current is prevented by turning on the second gate 16.

Next, a second embodiment will be described with reference to the schematic sectional view shown in FIG. As shown in the figure, a first gate 32 made of polycrystalline silicon is formed on the upper surface of the substrate 31. A first insulating layer 33 made of SiO ₂ is formed on the substrate 31 so as to cover the first gate 32.
A junction forming layer 34 made of polycrystalline silicon is formed on the upper surface of the first insulating layer 33. A second insulating layer 35 made of SiO ₂ is formed on the upper surface of the bond forming layer 34. A second gate 36 made of polycrystalline silicon is formed on the upper surface of the second insulating layer 35 so as to overlap a part of the first gate 32.

In the junction forming layer 34 on the side opposite to the first gate 32 side with respect to the one end 36a of the second gate 36 in which the first gate 32 does not overlap, for example, boron fluoride (BF ₂ ⁺ ) Ion-implanted drain region 3
7 are formed. Further, the junction forming layer 34 below the second gate 36 in the portion overlapping the first gate 32 becomes the channel 38, and the junction forming layer 34 between the channel 38 and the drain region 37 is the offset region 39.
become. Further, in the junction forming layer 34 on the side opposite to the drain region 37 side with respect to the second gate 36, a source region 40 in which, for example, boron fluoride (BF ₂ ⁺ ) is ion-implanted is formed.

A semiconductor device 3 having a two-layer gate structure having the above structure
At 0, by forming a part of the second gate 36 so as to overlap the first gate 32,
The first gate 32 relaxes the drain voltage and also relaxes the gate voltage to reduce the leak current.
Further, the decrease of the ON current is prevented by turning on the second gate 36.

Next, the semiconductor device 1 having the above-mentioned two-layer gate structure
An example in which either 0 or 30 is used for the static RAM will be described with reference to FIG. As shown in the circuit configuration diagram of FIG.
A stacked static RAM (SRAM) 50 has a memory cell composed of a flip-flop 51 and transfer transistors 52 and 53. The flip-flop 51 is formed by cross-connecting the input terminal and the output terminal of the pair of inverters 54 and 55. Each of the inverters 54, 55 has a driving transistor 56, 5
7 and load elements 58 and 59. The load elements 58 and 59 are the same as the load elements 58 and 59 described in the first and second embodiments.
It is formed of one of the semiconductor devices 10 and 30 having the layer gate structure. Each load element (thin film transistor) 5
A power supply line 61 is connected to 8 and 59, and a ground line 62 is connected to each of the driving transistors 56 and 57. A bit line 63 and a word line 64 are connected to the transfer transistors 52 and 53, respectively. Normally, a plurality of SRAMs 50 having the above configuration are arranged to form one large capacity SRAM.

As described above, in the SRAM 50 in which the load elements 58 and 59 of the inverters 54 and 55 are formed in the semiconductor device having the double-layered gate structure, the ON current is prevented from decreasing without increasing the cell area. Leakage current is reduced.

[0017]

As described above, according to the first or second aspect of the invention, the first gate is formed by forming the second gate in a state of overlapping with a part of the first gate. Since the transistor has an offset structure, the drain voltage can be relaxed. Further, since the gate voltage is relaxed, the leak current can be reduced. Further, by turning on the second gate, it is possible to prevent a decrease in ON current. According to the invention of claim 3, claim 1
Alternatively, in the semiconductor device having a two-layer gate structure according to claim 2, S
Since the load element of the inverter of the RAM is formed, the leak current can be reduced without increasing the cell area. Therefore, the electrical performance of the SRAM can be improved.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a first embodiment.

FIG. 2 is a schematic sectional view of a second embodiment.

FIG. 3 is a circuit configuration diagram of a static RAM.

[Explanation of symbols]

 10 semiconductor device having a two-layer gate structure 11 substrate 12 junction forming layer 13 first insulating layer 14 first gate 15 second insulating layer 16 second gate 17 drain region 19 offset region 20 source region 30 two-layer gate structure Semiconductor device 31 Substrate 32 First gate 33 First insulating layer 34 Junction forming layer 35 Second insulating layer 36 Second gate 37 Drain region 39 Offset region 40 Source region 50 Static RAM 51 Flip-flop 54 Inverter 55 Inverter 58 load element 59 load element

Claims (3)

[Claims] 1. A junction forming layer formed on an upper surface of a substrate, a first insulating layer formed on an upper surface of the junction forming layer, a first gate formed on an upper surface of the first insulating layer, A second insulating layer formed on the first insulating layer so as to cover the first gate; and a second insulating layer formed on the upper surface of the second insulating layer so as to overlap a portion of the first gate. Second gate, and the junction forming layer on the side opposite to the first gate side from the position below the second gate end on the side where the second gate does not overlap with the first gate. A drain region formed in the junction formation layer, an offset region formed in the junction formation layer between the drain formation region and the drain formation region below the first gate, and the offset region with respect to the first gate. Is the solder formed on the bonding formation layer on the opposite side. The semiconductor device having a two-layer gate structure, characterized by comprising by the source region. 2. A first gate formed on a substrate, a first insulating layer formed on the substrate so as to cover the first gate, and a bond formed on an upper surface of the first insulating layer. A forming layer, a second insulating layer formed on the upper surface of the junction forming layer, and a second gate formed on the upper surface of the second insulating layer so as to overlap a portion of the first gate, A drain region formed in the junction forming layer on the side opposite to the first gate side from the position below the second gate end on the side where the second gate does not overlap with the first gate. An offset region formed in the junction formation layer between the junction formation layer and the drain region above the first gate, and the offset region on the opposite side of the drain region with respect to the second gate. The source region formed in the junction forming layer The semiconductor device having a two-layer gate structure, characterized by comprising. 3. A static RAM in which a memory cell is composed of a flip-flop composed of a pair of inverters, wherein the load element of the inverter is formed by the semiconductor device having a two-layer gate structure according to claim 1 or 2. Characteristic static RAM.