JPH0580297A - Matrix driving method of plane type display device - Google Patents

Abstract

PURPOSE:To provide the matrix driving method of the plane type display device which sets a picture element having bistability in a light or dark state, makes a selection time 2tau long, and prevents a flicker to improve picture quality. CONSTITUTION:While the number of gradations is set to 2N, a frame period Tf is divided into (2N+x) (x: 0 or positive integer) equal-interval blocks and write blocks are provided at the heads of N fields each consisting of 2<n> (n: 0, 1,..., N-1) blocks respectively; while (x+1) blocks are regarded as reset blocks B(R), scanning electrodes are divided into groups of combination which does not generate plural write blocks at the same time, one group is selected for each write block, and respective picture elements on scanning electrodes in one group are stored in the light or dark state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix driving method for displaying multi-gradation by using a bistable flat display device such as a ferroelectric liquid crystal.

[0002]

2. Description of the Related Art A flat-panel display device using a ferroelectric liquid crystal or the like having high-speed switching characteristics and bistability (memory property) is known. Various driving methods utilizing the characteristic of the bistability have also been proposed.

For example, in the two-field method, one frame is divided into two.
It consists of two consecutive fields, a first field that draws black and holds white pixels, and a second field that draws white pixels and holds black pixels. This method requires two separate fields to write black and white, which increases the time (frame period) T _f required to write one frame. That is, if the pulse width (selection time) required for writing white or black is 2τ, this method requires a writing time of 4τ. For this reason, a liquid crystal capable of extremely shortening the selection time 2τ or the pulse width τ is inevitably required. However, it is very difficult to obtain such a high-speed response. Also, since the pulse width τ cannot be shortened,
The frame period T _f becomes long and flicker is likely to occur.

The equal division scanning method is also known. In this method, as shown in the explanatory view of FIG. 13, when one frame period T _{f is set} to n + 1 gradation (n = 15 in the figure), it is equally divided into n and all the scanning lines ( The number Y is set to, for example, 480), and writing is performed while the writing timing is set for each scanning line. RS in the drawing is a simplified representation of the timing of the write scan corresponding to each scan line. In this method, the number of blocks to be written in black or white is changed from 0 to 15 according to the gradation to be drawn. That is, for example, in gradation 1, black or white is written only for the time of block 1, and in gradation 10, blocks 1 to 1 are written.
Write for 10 hours.

However, this method has a problem that the writing pulse width τ for white or black becomes very short. That is, τ = T _f / (Y × n × 2) = T _f / 480 × 15 × 2 =
Since T _f / 14400, a liquid crystal having extremely high responsiveness is required.

A uniform division frame period shortening scanning method is also known (for example, Japanese Patent Laid-Open No. 62-56936). In this method, as shown in the example of 16 (= 2 ⁴ ) gradations in FIG. 14, each block 1 in which the frame period T _f is divided into four when 16 gradations is set.
To 4 are respectively associated with gradations of 8, 4, 2, and 1, and desired gradations are drawn by using blocks 1 to 4 as needed. In each of the blocks 1 to 4, the write scanning is performed at the timing shown by RS in the figure, while in the blocks 2, 3 and 4, R is performed after the time corresponding to 4, 2, 1 gradations from the writing of the RS, respectively. Reset scanning shown by is performed to forcibly reset all the pixels on the scanning line. As a result, each block 2, 3, 4 is changed to 4,
It corresponds to gradations of 2 and 1.

According to this method, the pulse width τ is significantly improved to τ = T _f / (480 · 4 · 2) = T _f / 3840. However, according to this method, there occurs a problem that the transmittance is significantly reduced. For example, in the brightest gradation 15, (15/32) × 100 = 46
Only% time is clear. Further, this causes a problem that the contrast is also lowered.

Therefore, it is considered that the time width of each of the blocks 1 to 4 is narrowed in accordance with the gradations that share the time width (frame cycle shortening scanning method). FIG. 15 is an explanatory diagram of the 16 gradations, and the frame cycle T _f is gradation 15 (= 2 ⁴ −1).
The first block of the four fields F ₁ , F ₂ , F ₃ , F ₄ consisting of 1, 2, 4, 8 blocks is set as a writing block for performing writing scanning indicated by RS. It is a thing. Therefore, in this case, the brightest gradation 15 is white for the entire frame period T _f , and the transmittance can be 100%.

However, in this case, the pulse width τ required for writing is τ = T _f / (480 × 15 × 2) = T _f / 14400, and it is necessary to make τ extremely short. However, as described above, it is very difficult to obtain such a high response liquid crystal.

Therefore, a method has been proposed in which Y scanning lines are divided into a plurality of groups and each group is scanned separately in parallel (JP-A-64-61180). In this method, as shown in FIG. 16, the leading write blocks of the fields F ₁ , F ₂ , F ₃ , and F ₄ do not overlap each other and the fields F ₁
Divide the scan line Y into a number M of possible combinations of ~ F ₄ . For example, when there are 16 (= 2 ⁴ ) gradations, three kinds of combinations are possible as shown in this figure, so Y = 480 is divided into three groups Y ₁ , Y ₂ , and Y ₃ each having 160 lines, and each group is divided into _three groups. Y _{1 to} F ₃ are simultaneously and separately scanned.

According to this method, τ = T _f / (160 × 15 × 2) = T _f / 4800, and the pulse width τ can be tripled as compared with the case of FIG. Similarly, in the case of 8 (= 2 ³ ) gradations, two combinations are possible as shown in FIG. 17, τ can be doubled, and in the case of 32 (= 2 ⁵ ) gradations, as shown in FIG. To 4
Since two combinations are possible, τ can be quadrupled.

On the other hand, in order to improve the display image quality, a block including the write scan (RS) (write block B)
(RS)) fields F _1-
To increase the number of combinations of F _n as much as possible, that is, in FIG.
It is desirable to increase the number M of the groups Y ₁ , Y ₂ , Y _3, ... Of the scanning lines Y in 6 to 18. However, the conventional frame period shortening method shown in FIGS. 16 to 18 has a problem that the number of possible combinations M cannot be increased, and the pulse width τ and the selection time 2τ cannot be increased.

It is also necessary to prevent screen flickering, that is, flicker, in order to improve image quality. In this flicker, the blinking of adjacent pixels is 1 frame cycle T
_Since it occurs when synchronizing within _f or when approaching in time, it is desirable that the blinking periods of adjacent pixels be as far apart as possible.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in the conventional frame cycle shortening scanning method shown in FIGS. 16 to 18 in which the scanning line group is divided into a plurality of fields, fields F ₁ and F _{2 are used.} , F ₃ ... Can be increased and the selection time 2τ can be lengthened. A first object of the present invention is to provide a matrix driving method for a flat panel display device. A second object of the present invention is to provide a matrix driving method for a flat panel display device capable of preventing flicker and improving image quality.

[0015]

SUMMARY OF THE INVENTION According to the present invention, it is an object of these inventions to form a matrix drive of a flat display device in which pixels having bistable characteristics are formed in the intersection region of scan electrodes and display electrodes, and each pixel is set to light or dark. In the method, the frame period T _f is divided into (2 ^N + x) (x is 0 or a positive integer) equally spaced blocks, where 2 ^N is the number of gradations, and each is 2
N consisting of ⁿ (n is 0, 1, ..., N-1) blocks
Writing blocks are provided at the beginning of each of the fields, and (x + 1) blocks are used as reset blocks, while the scanning electrodes are divided into groups each of which has a combination in which the writing blocks do not occur at the same time. A matrix driving method for a flat panel display device, characterized in that a predetermined one group is selected to store each pixel on the scanning electrodes in the one group in a bright or dark manner,
Achieved by.

The first purpose is to set N to 2 (4 gradations), 4 (16 gradations), 5 (when x is set to 0, that is, when one reset block is added. This can be achieved by increasing the number of dividable groups in the case of 32 gradations), 6 (64 gradations), and 8 (256 gradations). In addition, when the number of additional reset blocks is set to 1 where x is 1,
It is possible to increase the number of divisions of the group even when N is 8 gradations.

In order to achieve the second object,
Each group is arranged so that fields having the same number of blocks do not continue in the main scanning direction, and the scanning lines of each group are interlaced. In this case, by setting x to 0 and N to 3 (8 gradations), the phases of the two groups can be shifted by 180 °, and scanning lines of these groups are alternately arranged for interlaced scanning. This makes it possible to eliminate flicker better.

[0018]

EXAMPLE FIG. 1 is a conceptual diagram showing an electrode arrangement of a liquid crystal display panel,
FIG. 2 is a sectional view taken along the line II-II. Reference numeral 1 in these figures
Reference numeral 0 is an upper substrate made of a transparent glass plate, and 12 is a lower substrate. Reference numerals 14 and 16 denote transparent strip-shaped data electrodes and scanning electrodes formed on the surfaces of the upper and lower substrates 10 and 12 facing each other. These electrodes 14 and 16 are orthogonal to each other.

The electrodes 14 and 16 are covered with the alignment films 18 and 20, respectively, and are arranged so as to face each other, and the liquid crystal 22 is sandwiched between the electrodes. 24 is this liquid crystal 2
It is a spacer for keeping the gap of 2 constant. As a result, the region sandwiched between the electrodes 14 and 16 (for example, region A shown in FIG. 1) becomes a pixel region in which the amount of transmitted light changes depending on the voltage between the electrodes 14 and 16.

As the liquid crystal 22, for example, a ferroelectric liquid crystal is suitable. The ferroelectric liquid crystal 22 is a group of smectic liquid crystal materials exhibiting spontaneous polarization represented by a liquid crystal of a chiral smectic C phase, and exhibits a fast switching phenomenon and a memory phenomenon called bistability. That is, the molecular alignment state in which the orientation directions of the spontaneous polarization formed by the application of the electric field are uniformly aligned has the property of being stored as it is even when the electric field is cut off. The liquid crystal plate thus manufactured is placed between two polarizing plates (not shown) and controls the amount of transmitted light from the illumination device placed behind it.

[0021]

[Scanning Chart] A scanning chart used in the following description will be described. The signals supplied to the scanning electrode 16 (see FIGS. 1 and 2) and the data electrode 14, that is, the scanning signal v _c and the data signal v _I are composed of pulses having the waveforms shown in FIG.

The scanning signal v _c is produced by combining three kinds of signals of reset, selection and non-selection. The selection signal S has a class-like waveform having a potential of 0 and a potential of V _s each having a time width of τ. The time 2τ is a period in which the pixels on the scan electrode 16 are oriented in “bright” or “dark”, and is called a selection period. The non-selection signal N has a waveform of potentials 3V _s / 4 and V _s / 4 each having a time width of τ, and the time width 2τ is a period for scanning another scan electrode 16.

The reset signal R, and R ₁ which between the potential of 2τ is V _s, with two waveforms of R ₂ to between the potential of 2τ is zero. These three types of signals S, N and R are combined as described below and supplied to each scanning electrode 16. Data electrode 1
The data signal v _I supplied to 4 is 2 as shown in FIG.
It has two kinds of signals of ON and OFF having a time width of τ.

In the pixel area where the scan signal v _c on the scan electrode 16 and the data signal v _I on the data electrode 14 intersect,
As shown in FIG. 4, both signals v _c and v _I are combined to add the pixel voltage (v _c −v _I ). That is, when the scan signal v _c is the reset signal R, R ₁ and R ₂
Corresponding to the on / off state of the data signal v _I with respect to each time 2τ, four different pixel voltages [v _c −v _I ] _R are obtained. Here, it is the last voltage portion, that is, the shaded portion, that contributes to the change in the brightness of the pixel, and the area τ × V _S of this shaded portion is always a certain value or more, so that the pixel is forced to be “dark”. .. That is, the data signal v _I
It always "resets" to "dark" regardless of whether it is off.

When the scanning signal v _c is the selection signal S,
Data signal v 2 kinds of pixel voltage corresponding to the _I ON and OFF shown in FIG. 4 [v _c -v _{I] S} is obtained. Data signal v
_{When I} is on, the pixel voltage becomes V _S and the pixel is “bright”.
To When the data signal v _I is off, the pixel voltage is V _s
It becomes / 2 and the brightness of the pixel is not changed. When the scanning signal v _c is the non-selection signal N, the pixel voltage [v _c −v _I ] _N for changing the brightness of the pixel cannot be obtained regardless of whether the data signal v _I is on or off. Brightness does not change.

The scanning signal v _c is a combination of the selection signal S, the non-selection signal N, and the reset signal R as shown in FIG. Here, the scanning signals v _c1 , v _c2 , v _c3 ...
6 is applied. A reset signal R is added immediately before the selection signal S, and writing is performed with these signals (R ₁ R ₂ S) as a set. This write signal is indicated by RS.

As described above, the scanning signal v _c is composed of the write signal RS, the non-selection signal N and the reset signal R. Therefore, FIG. 5A is simplified as shown in FIG. As shown in (C) of the figure, the timing of writing scan is indicated by a straight line RS and the reset timing is indicated by a broken line R.

[0028]

[Embodiment with 4 gradations] FIG. 6 is a scanning chart of an embodiment applied in the case of 4 (= 2 ² ) gradations. In this embodiment, the frame period T _f is divided into 4 (= 2 ² ) blocks at equal intervals, and the leading block of _two fields F ₁ and F ₂ consisting of ₁ and ₂ blocks is used as a write signal RS.
And a remaining one block as a reset block B (R) having a reset signal R.

In this case, two combinations are possible as shown in the upper part of FIGS. 6A and 6B, and a plurality of write blocks are simultaneously generated for these (A) and (B). As the combinations of the fields F ₁ and F ₂ that are not performed, those shown in the lower part of FIGS. 6A and 6B are possible. That is, two combinations are possible in each of the cases (A) and (B). Therefore, the total number of scanning electrodes 16, that is, the total number of scanning lines Y of one screen (for example, 480) is set to two groups Y.
Divide into ₁ and Y ₂ and make each Y / 2 (= 240).

At the time of scanning, the two groups Y ₁ and Y ₂ are simultaneously scanned in parallel according to the scanning chart of FIG. 6A or 6B. As a result, the write blocks of different groups Y ₁ and Y ₂ do not overlap at all times. In other words, one group Y ₁ or Y ₂ is selected for each write block corresponding to a certain time, and each pixel on the scan electrode 16 in this group is stored in bright or dark. In the reset block B (R), the group Y ₁ or Y including this is included.
Each pixel on the _second scan electrode 16 is reset.

According to this embodiment, the transmittance is reduced from 100% to 75% (= 3/4) by adding one reset block B (R), but the pulse width τ required for writing is , Τ = T _f / (240 × 4 × 2) = T _f / 1920. When the reset block B (R) is not added, that is, when the scan electrode 16 is not divided into _two groups Y ₁ and Y ₂ , τ = T _f / (480 × 3 × 2) = T _f / 2880 It can be seen that τ can be made 1.5 times longer according to the present invention.

[0032]

[Embodiment with 8 gradations] FIG. 7 is a scanning chart of an embodiment with 8 (= 2 ³ ) gradations. In this embodiment, by adding two reset blocks B (R), the scan electrodes 16
Can be divided into _three groups Y ₁ , Y ₂ and Y ₃ . That is, the transmittance is 100 compared with the conventional method shown in FIG.
% To (7/9) × 100 = 77%, but τ
Is τ = T _f / (160 × 9 × 2) = T _f / 2880, which is 1.16 times that of τ = T _f / (240 × 7 × 2) = T _f / 3360 in the case of FIG. become.

[0033]

[Example of 16 gradations] FIG. 8 is a scanning chart of an example of 16 (= 2 ⁴ ) gradations. In this embodiment, by adding one reset block B (R), the scanning electrodes 16 can be divided into _four groups Y ₁ , Y ₂ , Y ₃ and Y ₄ . That is, compared with the conventional method shown in FIG. 16, the transmittance is reduced from 100% to (15/16) × 100 = 93%, but τ is τ = T _f / (120 × 16 × 2) = T _f / 3840, which is 1.25 times that of τ = T _f / (160 × 15 × 2) = T _f / 4800 in the case of FIG.

[0034]

[Embodiment of 32 gradations] FIG. 9 is a scanning chart of an embodiment of 32 (= 2 ⁵ ) gradations. In this embodiment, by adding one reset block B (R), the scanning electrodes 16 can be divided into _six groups Y _{1 to} Y ₆ . That is, the transmittance is 100% as compared with the conventional method shown in FIG.
To 96% ((31/32) × 100),
τ is τ = T _f / (80 × 32 × 2) = T _f / 5120, which is 1.45 times that of τ = T _f / (120 × 31 × 2) = T _f / 7440 in the case of FIG. become.

As described above, according to the present invention, as the number of display gradations increases to 64 and 256, the decrease in transmittance becomes slight and the increase in τ increases. In the above embodiment, the selection time τ is lengthened by adding the reset block B (R) so that the scanning line Y can be divided into as many groups Y ₁ , Y _2, ... As possible.

[0036]

[Embodiment of Preventing Flicker] Next, it will be explained that the present invention is effective for increasing the selection time τ while preventing flicker under certain conditions. FIG. 10 is a scanning chart diagram of an embodiment with 8 gradations. In this embodiment, by adding one reset block B (R), the two groups Y ₁ ,
The phase of Y ₂ is shifted 180 ° to make it opposite phase. As a result, the blinking timing between the two adjacent groups Y ₁ and Y _{2 is set} to 180
Since they can be shifted, it is possible to suppress flicker by interlacing (sequentially) scanning lines of these groups Y ₁ and Y ₂ arranged alternately or every predetermined number such as every two lines.

In the interlaced scanning, one group Y
_{It is also possible} to display _one field and then display the other group Y ₂ field so that both fields are alternately scanned to form one screen. A method of scanning all in order may be used. FIG. 11 is a scanning chart diagram when the density level is set to “6” in the case of interlacing with 8 gradations, and FIG. 12 is a diagram showing a change in lightness represented by two adjacent scanning lines in that case. Is.

The first scanning line of the scanning lines for example the group Y ₁ adjacent from 11 and (Y ₁ -1), than the first scanning line of the group Y ₂ (Y ₂ -1), flashing timing reversed It turns out that Each group Y _1, Y ₂ of the n-th scan line (Y ₁ -
n) and (Y ₂ -n), the contrast is as shown by I in FIG. It can be seen from FIG. 12 that the change cycle of light and dark is T _F / 2, which is half the frame period T _F (spatial integration effect). As a result, the blinking period becomes 1/2 (the blinking frequency is doubled), and the frame period T _F and the pulse width τ are set to 2
The effect that can be doubled is obtained.

Although the above-described embodiments use the ferroelectric liquid crystal, the present invention maintains the state of writing in bright or dark until the rewrite signal RS or the reset signal R is input (bistability (memory property). The present invention includes these, as long as it is a flat-panel display device having a), and is applicable not only to liquid crystals but also to other display devices such as a plasma display panel.

[0040]

As described above, the present invention divides the frame period T _f into (2 ^N + x) (where x is 0 or a positive integer) equally spaced blocks with the number of gradations being 2 ^N. , N each consisting of 2 ⁿ (n is 0, 1, ... N) blocks
The write block B (RS) is provided at the beginning of each field, and (x + 1) blocks are set as the reset block B (R). On the other hand, a combination in which a plurality of write blocks do not occur simultaneously is formed. As described above, the scan electrodes are divided into a plurality of groups so that a plurality of writing blocks do not overlap at all time points. Therefore, the number of dividable groups of scan electrodes can be increased by adding an appropriate number of reset blocks. Therefore, the pulse width τ required for writing can be lengthened, and the response required for a display device such as a liquid crystal can be suppressed low (claim 1).

For example, by setting x to 0 (that is, to add one reset block B (R)), scanning with four gradations of N = 2, which is impossible with the conventional frame period shortening method. The electrodes can be divided, and by setting N = 4, 5, etc., the number of possible divisions can be increased as compared with the conventional frame period shortening method (claim 2). Also x
Is set to 1 (that is, the reset block B to be added)
By (R) being two), the number of dividable groups can be increased as compared with the conventional frame cycle shortening method even when N = 3 and 8 gradations (claim 3).

When the groups are arranged so that the fields having the same number of blocks do not continue in the main scanning direction and the scanning lines of the groups are interlaced, the occurrence of flicker can be suppressed (claim 4). For example, when x = 0 and N = 3 (8 gradations), the two groups can have a phase difference of 180 ° (claims 5 and 6). In this case, the effect of preventing flicker is further enhanced. The pulse width can be increased and the pulse width can be lengthened. A display panel using a ferroelectric liquid crystal is suitable as the display device (claim 7).

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an electrode arrangement of a liquid crystal display panel.

FIG. 2 is a sectional view taken along line II-II.

FIG. 3 is a waveform diagram of pulses of a scanning signal and a data signal.

FIG. 4 is a waveform diagram of a pixel voltage

FIG. 5 is an explanatory diagram of a scanning chart.

FIG. 6 is a scan chart diagram of an embodiment with four gradations.

FIG. 7 is a scanning chart diagram of an example of 8 gradations.

FIG. 8 is a scanning chart diagram of an example of 16 gradations.

FIG. 9 is a scan chart diagram of an example of 32 gradations.

FIG. 10 is a scan chart of an embodiment for preventing flicker.

FIG. 11 is a scanning chart diagram in the case of interlacing.

FIG. 12 is a diagram showing a change in brightness due to adjacent scanning lines.

FIG. 13 is an explanatory diagram of a conventional equal division scanning method.

FIG. 14 is an explanatory diagram of a conventional equal division frame period shortening scanning method.

FIG. 15 is an explanatory diagram of a conventional frame period shortening scanning method.

FIG. 16 is an explanatory diagram of a conventional improved frame period shortening scanning method for 16 gradations.

FIG. 17 is an explanatory diagram of a conventional improved frame period shortening scanning method for 8 gradations.

FIG. 18 is an explanatory diagram of a conventional improved frame period shortening scanning method for 32 gradations.

[Explanation of symbols]

10 Upper Substrate 12 Lower Substrate 14 Data Electrode 16 Scanning Electrode 22 Liquid Crystal _Tf Frame Period F ₁ , F ₂ ... Field Y ₁ , Y ₂ ... Group RS Write Signal R Reset Signal

Claims (7)

[Claims] 1. A form pixels having bistability at intersections of the scanning electrodes and display electrodes, the matrix drive method of a flat type display device for setting the pixel bright or implicitly, a 2 ^N as the number of gradations , The frame period T _f is (2 ^N
+ X) (x is 0 or a positive integer) equally divided blocks, each of which is at the beginning of N fields consisting of 2 ⁿ (n is 0, 1, ..., N-1) blocks A write block is provided, and (x + 1) blocks are used as reset blocks. On the other hand, the scan electrodes are divided into groups each having a combination in which a plurality of write blocks do not occur at the same time, and one predetermined group is provided for each write block. A matrix driving method for a flat-panel display device, characterized in that each pixel on the scanning electrodes in the one group is selected and stored in a bright or dark manner. 2. x is 0 and N is 2, 4, 5, 6, 7
2. The matrix driving method for a flat panel display device according to claim 1. 3. The matrix driving method for a flat panel display device according to claim 1, wherein x is 1 and N is 3. 4. A flat-panel display device according to claim 1, wherein each group is arranged so that fields having the same number of blocks do not continue in the main scanning direction, and scanning lines of each group are interlaced. Matrix driving method. 5. The method for driving a matrix of a flat panel display device according to claim 4, wherein x is 0 and N is 3. 6. The matrix driving method for a flat panel display device according to claim 5, wherein the phases of adjacent scanning lines are shifted by approximately 180 °. 7. The matrix driving method for a flat display device according to claim 1, wherein the flat display device is a display panel using a ferroelectric liquid crystal.