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JPH0575237A - Conductor pattern formation - Google Patents

Conductor pattern formation

Info

Publication number
JPH0575237A
JPH0575237A JP23168791A JP23168791A JPH0575237A JP H0575237 A JPH0575237 A JP H0575237A JP 23168791 A JP23168791 A JP 23168791A JP 23168791 A JP23168791 A JP 23168791A JP H0575237 A JPH0575237 A JP H0575237A
Authority
JP
Japan
Prior art keywords
plating
film
pattern
conductor
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP23168791A
Other languages
Japanese (ja)
Inventor
Susumu Aoyama
進 青山
Kazumasa Hosono
和真 細野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23168791A priority Critical patent/JPH0575237A/en
Publication of JPH0575237A publication Critical patent/JPH0575237A/en
Withdrawn legal-status Critical Current

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  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To realize easy formation of a fine pattern regarding a formation method of a conductor pattern by a plating method which is used for formation of a coil of a thin film magnetic head, etc. CONSTITUTION:A conductor pattern formation method for forming a thin film conductor 16 of a specified pattern on an insulator 15A by a plating method. The method includes a process for providing a plating mask layer 32 whose pattern width w2 of a mask part is larger than a pattern interval (d) of the thin film conductor 16 on a plating foundation conducting film 31a which coats the insulator 15A, a first plating process for providing a plating film 33 to fill a non-masked part of the plating mask layer 32, a process for removing a part which is exposed by removal of the plating mask layer 32 inside the plating foundation conducting film 31a and a second plating process for forming the thin film conductor 16 by providing the plating film 34 to coat a surface of the plating film 33.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、メッキ法による導体パ
ターンの形成方法に関し、薄膜磁気ヘッドのコイルの形
成などに利用される。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductor pattern by a plating method and is used for forming a coil of a thin film magnetic head.

【0002】コンピュータシステムの外部記憶装置とし
て用いられている磁気ディスク装置においては、記録密
度を高める上で小型の磁気ヘッドが要求されている。そ
れ故、薄膜磁気ヘッドについてはコイルパターンの微細
化が進められている。
In a magnetic disk device used as an external storage device of a computer system, a small magnetic head is required to increase the recording density. Therefore, for thin-film magnetic heads, miniaturization of coil patterns is being promoted.

【0003】[0003]

【従来の技術】図2(a)及び(b)は一般的な薄膜磁
気ヘッド1の構造を示す図である。図2(a)は要部の
断面図であり、図2(b)は要部の平面図である。な
お、図2(a)は図2(b)のA−A矢視断面に対応す
る。
2A and 2B are views showing the structure of a general thin film magnetic head 1. 2A is a cross-sectional view of the main part, and FIG. 2B is a plan view of the main part. Note that FIG. 2A corresponds to a cross section taken along the line AA of FIG.

【0004】薄膜磁気ヘッド1は、アルミナ・チタンカ
ーバイドからなる支持体11、アルミナからなる絶縁層
12、Ni−Feからなる下部及び上部の磁極13,1
7、二酸化珪素からなるギャップ層14、熱硬化性樹脂
などの層間絶縁体15、Cuメッキ膜からなる渦巻き状
のコイル16、及びアルミナからなる保護膜18などか
ら構成されている。
The thin film magnetic head 1 includes a support 11 made of alumina / titanium carbide, an insulating layer 12 made of alumina, and lower and upper magnetic poles 13, 1 made of Ni--Fe.
7, a gap layer 14 made of silicon dioxide, an interlayer insulator 15 made of a thermosetting resin, a spiral coil 16 made of a Cu plating film, a protective film 18 made of alumina, and the like.

【0005】磁極13,17は、コンタクト部137で
一体化して磁気コアを構成している。コイル16の内端
及び外端はそれぞれ図示しない外部接続端子に接続され
ている。
The magnetic poles 13 and 17 are integrated by a contact portion 137 to form a magnetic core. The inner end and the outer end of the coil 16 are connected to external connection terminals (not shown).

【0006】従来において、薄膜磁気ヘッド1のコイル
16は、以下の導体パターン形成方法によって形成され
ていた。図3は従来の導体パターン形成方法によるコイ
ル形成の各段階の状態を示す要部断面図である。なお、
同図では、非断面の図示を省略してある。
Conventionally, the coil 16 of the thin film magnetic head 1 has been formed by the following conductor pattern forming method. FIG. 3 is a cross-sectional view of an essential part showing the state of each stage of coil formation by the conventional conductor pattern forming method. In addition,
In the figure, the illustration of the non-section is omitted.

【0007】ここでは、既に、上述の支持体11上に、
絶縁層12、下部の磁極13、及びギャップ層14が設
けられ、さらに層間絶縁体15の一部(コイル16の下
側の部分)となる絶縁体15Aが設けられているものと
する。
Here, already on the above-mentioned support 11,
It is assumed that the insulating layer 12, the lower magnetic pole 13, and the gap layer 14 are provided, and further that an insulator 15A that is a part of the interlayer insulator 15 (a portion below the coil 16) is provided.

【0008】まず、絶縁体15Aの表面を一様に被覆す
るように、真空蒸着又はスパッタ蒸着などによって、
0.01μm程度の厚さのTi層と0.1μm程度の厚
さのCu層とからなる二層構造のメッキ用下地導電膜
(メッキベース)31aを設ける[図3(a)]。
First, the surface of the insulator 15A is uniformly covered by vacuum vapor deposition or sputter vapor deposition.
A base conductive film (plating base) 31a for plating having a two-layer structure, which is composed of a Ti layer having a thickness of about 0.01 μm and a Cu layer having a thickness of about 0.1 μm, is provided [FIG. 3 (a)].

【0009】次に、フォトレジスト液を4μm程度の厚
さに塗布し、フォトリソグラフィ法を用いて、コイル1
6のパターン(渦巻き状)に相当した開口パターン(非
マスク部の平面形状)を有するメッキ用マスク層32を
形成する[図3(b)]。
Next, a photoresist solution is applied to a thickness of about 4 μm, and the coil 1 is formed by photolithography.
The plating mask layer 32 having an opening pattern (planar shape of the non-mask portion) corresponding to the pattern 6 (spiral shape) is formed [FIG. 3 (b)].

【0010】続いて、メッキ用下地導電膜31aをメッ
キ用電極として用いる電解メッキ法によって、メッキ用
マスク層32の非マスク部を埋めるように、膜厚が3μ
m程度のCuメッキ膜33を形成する[図3(c)]。
Subsequently, the film thickness is 3 μm so as to fill the non-masked portion of the plating mask layer 32 by an electrolytic plating method using the plating underlying conductive film 31a as a plating electrode.
A Cu plating film 33 of about m is formed [FIG. 3 (c)].

【0011】そして、メッキ用マスク層32を除去した
後、Cuメッキ膜33をエッチングマスクとして、ドラ
イエッチング法の中でも特に微細加工に適したイオンミ
リングによって、メッキ用下地導電膜31aの露出部分
を除去する[図3(d)]。これにより、メッキ用下地
導電膜31aは渦巻き状にパターンニングされ、Cuメ
ッキ膜33が渦巻きの径方向に絶縁されてコイル16と
なる[図3(e)]。
After removing the plating mask layer 32, the exposed portion of the plating underlying conductive film 31a is removed by ion milling, which is particularly suitable for fine processing among dry etching methods, using the Cu plating film 33 as an etching mask. [Fig. 3 (d)]. As a result, the plating underlying conductive film 31a is spirally patterned, and the Cu plating film 33 is insulated in the radial direction of the spiral to form the coil 16 [FIG. 3 (e)].

【0012】[0012]

【発明が解決しようとする課題】薄膜磁気ヘッド1の小
型化などのためにコイル16のパターンの微細化を図る
場合には、必然的にコイル16の巻き線幅(パターン
幅)w及び巻き線間隔(パターン間隔)dを小さい値に
選定することになる。しかし、コイル16の膜厚は抵抗
値の増大を抑える上で所定値以下に薄くすることができ
ない。
When the pattern of the coil 16 is miniaturized in order to miniaturize the thin-film magnetic head 1, the winding width (pattern width) w of the coil 16 and the winding are inevitable. The interval (pattern interval) d is selected to be a small value. However, the film thickness of the coil 16 cannot be made thinner than a predetermined value in order to suppress an increase in resistance value.

【0013】したがって、従来の形成方法では、Cuメ
ッキ膜33を形成した後に、メッキ用下地導電膜31a
の不要部分の除去、すなわちメッキ用下地導電膜31a
のパターンニングを行うが、このとき、Cuメッキ膜3
3で挟まれた細く且つ深い溝の底部にメッキ用下地導電
膜31aが存在することになり、イオンミリングを用い
てもパターンニングが困難であるという問題があった。
Therefore, in the conventional forming method, after the Cu plating film 33 is formed, the plating underlying conductive film 31a is formed.
Unnecessary portions of the film, that is, the underlying conductive film 31a for plating
Patterning is performed. At this time, the Cu plating film 3
Since the underlying conductive film 31a for plating is present at the bottom of the thin and deep groove sandwiched by 3, there is a problem that patterning is difficult even if ion milling is used.

【0014】つまり、イオンの照射角度の調整に高精度
が要求されるとともに、メッキ用下地導電膜31aに入
射するイオンの密度が小さいことから、パターンニング
に長時間を要することになる。
That is, high precision is required for adjusting the irradiation angle of the ions, and since the density of the ions incident on the plating base conductive film 31a is low, it takes a long time for patterning.

【0015】また、イオンミリングに際してCuメッキ
膜33がエッチングマスクとして用いられることから、
Cuメッキ膜33も削られてコイル16の巻き線間隔d
が拡がるので、これを見込んで予めCuメッキ膜33の
幅を広く設定した場合には、さらにメッキ用下地導電膜
31aのパターンニングが困難になる。
Since the Cu plating film 33 is used as an etching mask during ion milling,
The Cu plating film 33 is also scraped and the winding spacing d of the coil 16 is increased.
Therefore, if the width of the Cu plating film 33 is set wide in advance in consideration of this, the patterning of the plating underlying conductive film 31a becomes more difficult.

【0016】本発明は、上述の問題に鑑み、メッキ用下
地導電膜を容易にパターンニングすることができ、形成
パターンの微細化に適した導体パターン形成方法を提供
することを目的としている。
In view of the above problems, it is an object of the present invention to provide a conductor pattern forming method which can easily pattern a plating base conductive film and is suitable for miniaturization of a formation pattern.

【0017】[0017]

【課題を解決するための手段】本発明は、上述の課題を
解決するため、図1に示すように、絶縁体15A上にメ
ッキ法によって所定パターンの薄膜導体16を形成する
導体パターン形成方法であって、前記絶縁体15Aを被
覆するメッキ用下地導電膜31a上に、マスク部分のパ
ターン幅w2が前記薄膜導体16のパターン間隔dより
大きいメッキ用マスク層32を設ける工程と、前記メッ
キ用マスク層32の非マスク部分を埋めるようにメッキ
膜33を設ける第1のメッキ工程と、前記メッキ用下地
導電膜31aの内の前記メッキ用マスク層32の除去に
より露出した部分を除去する工程と、前記メッキ膜33
の表面を被覆するようにメッキ膜34を設けて前記薄膜
導体16を形成する第2のメッキ工程とを含む。
In order to solve the above problems, the present invention provides a conductor pattern forming method for forming a thin film conductor 16 of a predetermined pattern on an insulator 15A by a plating method as shown in FIG. And a step of providing a plating mask layer 32 having a pattern width w2 of the mask portion larger than the pattern interval d of the thin film conductors 16 on the plating underlying conductive film 31a covering the insulator 15A, and the plating mask. A first plating step of providing a plating film 33 so as to fill a non-masked portion of the layer 32, and a step of removing a portion of the plating underlying conductive film 31a exposed by the removal of the plating mask layer 32, The plating film 33
And a second plating step of forming the thin film conductor 16 by providing a plating film 34 so as to cover the surface of the.

【0018】[0018]

【作用】メッキ用マスク層32のマスク部分のパターン
幅w2は、形成すべき薄膜導体16のパターン間隔dよ
り大きめに選定される。これにより、メッキ用下地導電
膜31aのパターンニングに際しては、除去すべき領域
が最終的に形成される薄膜導体16のパターン間隔領域
に比べて広いことから、イオンミリングなどのエッチン
グ手法を用いて容易にパターンニングを行うことができ
る。
The pattern width w2 of the mask portion of the plating mask layer 32 is selected to be larger than the pattern distance d of the thin film conductor 16 to be formed. As a result, when patterning the underlying conductive film 31a for plating, since the region to be removed is wider than the pattern interval region of the thin film conductor 16 to be finally formed, it is easy to use an etching method such as ion milling. Can be patterned.

【0019】[0019]

【実施例】以下、図2に示した薄膜磁気ヘッド1のコイ
ル16の形成を例に挙げて本発明の導体パターン形成方
法を説明する。
EXAMPLES The method for forming a conductor pattern of the present invention will be described below by taking the formation of the coil 16 of the thin film magnetic head 1 shown in FIG. 2 as an example.

【0020】図1は本発明に係るコイル形成の各段階の
状態を示す要部断面図である。なお、同図において、図
3と同一の機能を有する構成要素には、形状及び材質の
差異に係わらず同一の符号を付してある。また、非断面
の図示を省略してある。
FIG. 1 is a cross-sectional view of an essential part showing the state of each stage of coil formation according to the present invention. In the figure, components having the same functions as those in FIG. 3 are designated by the same reference numerals regardless of the difference in shape and material. Further, the illustration of the non-section is omitted.

【0021】まず、従来と同様に絶縁体15Aの表面を
一様に被覆するように、真空蒸着又はスパッタ蒸着など
によって、Ti層とCu層とを順に重ねた二層構造のメ
ッキ用下地導電膜31a(膜厚は0.1μm程度)を設
ける[図1(a)]。
First, as in the conventional case, the underlying conductive film for plating has a two-layer structure in which a Ti layer and a Cu layer are sequentially stacked by vacuum deposition or sputter deposition so as to uniformly cover the surface of the insulator 15A. 31a (film thickness is about 0.1 μm) is provided [FIG. 1 (a)].

【0022】次に、ポジ型のフォトレジスト液を4μm
程度の厚さに塗布し、フォトリソグラフィ法を用いて、
コイル16のパターン(渦巻き状)に対応した開口パタ
ーン(非マスク部の平面形状)を有するメッキ用マスク
層32を形成する[図1(b)]。
Next, a positive photoresist solution was added to 4 μm.
Apply to a thickness of about, and use photolithography method,
A plating mask layer 32 having an opening pattern (planar shape of the non-mask portion) corresponding to the pattern (coil shape) of the coil 16 is formed [FIG. 1 (b)].

【0023】ただし、メッキ用マスク層32の開口パタ
ーンは、コイル16のパターンに比べて細幅のパターン
とされている。つまり、開口パターン幅w1はコイル1
6のパターン幅wに比べて小さく、逆にみれば、メッキ
用マスク層32のマスク部のパターン幅w2はコイル1
6のパターン間隔dに比べて大きい。
However, the opening pattern of the plating mask layer 32 is narrower than the pattern of the coil 16. That is, the opening pattern width w1 is equal to the coil 1
6 is smaller than the pattern width w of FIG. 6, and conversely, the pattern width w2 of the mask portion of the plating mask layer 32 is the coil 1
6 is larger than the pattern interval d.

【0024】続いて、上述のようにポジ型フォトレジス
トからなるメッキ用マスク層32が感光しない環境で、
メッキ用下地導電膜31aをメッキ用電極として用いる
電解メッキ法によって、メッキ用マスク層32の非マス
ク部を埋めるように、膜厚が数μm程度のCuメッキ膜
33を形成する[図1(c)]。
Then, in an environment in which the plating mask layer 32 made of a positive photoresist is not exposed as described above,
A Cu plating film 33 having a thickness of about several μm is formed by an electrolytic plating method using the plating underlying conductive film 31a as a plating electrode so as to fill the non-mask portion of the plating mask layer 32 [FIG. )].

【0025】そして、後のメッキ時に必要となる通電の
ための図示しない引き出し配線パターンを残すようにメ
ッキ用マスク層32に対してパターン露光を行い、メッ
キ用下地導電膜31aの一部(引き出し配線パターン)
の上部以外についてメッキ用マスク層32を除去した
後、Cuメッキ膜33及び残ったメッキ用マスク層32
をエッチングマスクとして、イオンミリングによって、
メッキ用下地導電膜31aの露出部分を除去する[図1
(d)]。
Then, pattern exposure is performed on the plating mask layer 32 so as to leave a lead-out wiring pattern (not shown) for energization that is required during later plating, and a part of the plating base conductive film 31a (lead-out wiring). pattern)
After removing the plating mask layer 32 except for the upper part, the Cu plating film 33 and the remaining plating mask layer 32 are removed.
Using as an etching mask, by ion milling,
The exposed portion of the plating conductive film 31a is removed [FIG.
(D)].

【0026】このとき、除去すべき領域は、その幅が上
述のパターン幅w2に等しく、薄膜導体16のパターン
間隔dに比べて広いことから、薄膜導体16の微細化の
ためにパターン間隔dを小さい値としても、従来のよう
に除去すべき領域の幅が薄膜導体16のパターン間隔d
と等しい場合に比べて除去が容易である。
At this time, the region to be removed has a width equal to the above-mentioned pattern width w2 and is wider than the pattern interval d of the thin film conductor 16, so that the pattern interval d is set to be fine for the thin film conductor 16. Even if the value is small, the width of the region to be removed as in the conventional case is the pattern spacing d of the thin film conductor 16.
Is easier to remove than when

【0027】不要のメッキ用下地導電膜31aの除去に
より、メッキ用下地導電膜31aは渦巻き状の導電膜3
1bにパターンニングされ、Cuメッキ膜33は渦巻き
の径方向に絶縁される[図1(e)]。
By removing the unnecessary plating base conductive film 31a, the plating base conductive film 31a is formed into a spiral conductive film 3.
1b, the Cu plating film 33 is insulated in the radial direction of the spiral [FIG. 1 (e)].

【0028】最後に、上述の引き出し配線パターンを電
源に接続し、再び電解メッキ法によって、Cuメッキ膜
33の表面を被覆するように所定膜厚のCuメッキ膜3
4を設けてコイル16を完成する。
Finally, the above-mentioned lead-out wiring pattern is connected to a power source, and the Cu plating film 3 having a predetermined thickness is coated again by electrolytic plating to cover the surface of the Cu plating film 33.
4 is provided to complete the coil 16.

【0029】[0029]

【発明の効果】本発明によれば、メッキ法による導体パ
ターンの形成に必要となるメッキ用下地導体を導体パタ
ーンに合わせて容易にパターンニング形成することがで
き、導体パターンの微細化を図ることができる。
According to the present invention, it is possible to easily form a plating base conductor, which is necessary for forming a conductor pattern by a plating method, in accordance with the conductor pattern, and to miniaturize the conductor pattern. You can

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るコイル形成の各段階の状態を示す
要部断面図である。
FIG. 1 is a sectional view of an essential part showing a state of each stage of coil formation according to the present invention.

【図2】一般的な薄膜磁気ヘッドの構造を示す図であ
る。
FIG. 2 is a diagram showing a structure of a general thin film magnetic head.

【図3】従来の導体パターン形成方法によるコイル形成
の各段階の状態を示す要部断面図である。
FIG. 3 is a cross-sectional view of a main part showing a state of each stage of coil formation by a conventional conductor pattern forming method.

【符号の説明】[Explanation of symbols]

15A 絶縁体 16 コイル(薄膜導体) 31a メッキ用下地導電膜 32 メッキ用マスク層 33 Cuメッキ膜(メッキ膜) 34 Cuメッキ膜(メッキ膜) w2 パターン幅 d パターン間隔 15A Insulator 16 Coil (thin film conductor) 31a Plating underlying conductive film 32 Plating mask layer 33 Cu plating film (plating film) 34 Cu plating film (plating film) w2 Pattern width d Pattern spacing

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁体(15A)上にメッキ法によって所
定パターンの薄膜導体(16)を形成する導体パターン
形成方法であって、 前記絶縁体(15A)を被覆するメッキ用下地導電膜
(31a)上に、マスク部分のパターン幅(w2)が前
記薄膜導体(16)のパターン間隔(d)より大きいメ
ッキ用マスク層(32)を設ける工程と、 前記メッキ用マスク層(32)の非マスク部分を埋める
ように、メッキ膜(33)を設ける第1のメッキ工程
と、 前記メッキ用下地導電膜(31a)の内の前記メッキ用
マスク層(32)の除去により露出した部分を除去する
工程と、 前記メッキ膜(33)の表面を被覆するようにメッキ膜
(34)を設けて前記薄膜導体(16)を形成する第2
のメッキ工程とを含むことを特徴とする導体パターン形
成方法。
1. A conductor pattern forming method for forming a thin film conductor (16) having a predetermined pattern on an insulator (15A) by a plating method, which comprises a base conductive film for plating (31a) covering the insulator (15A). ), A step of providing a plating mask layer (32) having a pattern width (w2) of the mask portion larger than the pattern interval (d) of the thin film conductor (16), and a non-mask of the plating mask layer (32). A first plating step of providing a plating film (33) so as to fill the portion, and a step of removing the portion of the plating underlying conductive film (31a) exposed by the removal of the plating mask layer (32); And a second step of forming a thin film conductor (16) by providing a plating film (34) so as to cover the surface of the plating film (33).
And a plating step.
JP23168791A 1991-09-11 1991-09-11 Conductor pattern formation Withdrawn JPH0575237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23168791A JPH0575237A (en) 1991-09-11 1991-09-11 Conductor pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23168791A JPH0575237A (en) 1991-09-11 1991-09-11 Conductor pattern formation

Publications (1)

Publication Number Publication Date
JPH0575237A true JPH0575237A (en) 1993-03-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP23168791A Withdrawn JPH0575237A (en) 1991-09-11 1991-09-11 Conductor pattern formation

Country Status (1)

Country Link
JP (1) JPH0575237A (en)

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JP2002280219A (en) * 2001-03-16 2002-09-27 Sony Corp Inductor and/or circuit wiring near in vicinity and its manufacturing method
JP2003101240A (en) * 2001-09-20 2003-04-04 Mitsubishi Gas Chem Co Inc Method of manufacturing high-density printed wiring board
KR100487364B1 (en) * 1997-11-26 2005-06-16 엘지전자 주식회사 Method of manufacturing for thin film inductor
JP2008251640A (en) * 2007-03-29 2008-10-16 Tdk Corp Method of forming conductor pattern
JP2013054213A (en) * 2011-09-05 2013-03-21 Dainippon Printing Co Ltd Method for manufacturing optical transmission line fixing member including through-electrode
JP5294288B1 (en) * 2012-10-30 2013-09-18 株式会社Leap Method of manufacturing a coil element by electroforming using a resin substrate
US20160343500A1 (en) * 2015-05-19 2016-11-24 Samsung Electro-Mechanics Co., Ltd. Chip electronic component
CN107331491A (en) * 2013-08-02 2017-11-07 乾坤科技股份有限公司 Magnetic device
CN112262446A (en) * 2018-07-04 2021-01-22 斯天克有限公司 Coil device and method for manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487364B1 (en) * 1997-11-26 2005-06-16 엘지전자 주식회사 Method of manufacturing for thin film inductor
JP2002280219A (en) * 2001-03-16 2002-09-27 Sony Corp Inductor and/or circuit wiring near in vicinity and its manufacturing method
JP2003101240A (en) * 2001-09-20 2003-04-04 Mitsubishi Gas Chem Co Inc Method of manufacturing high-density printed wiring board
JP2008251640A (en) * 2007-03-29 2008-10-16 Tdk Corp Method of forming conductor pattern
JP2013054213A (en) * 2011-09-05 2013-03-21 Dainippon Printing Co Ltd Method for manufacturing optical transmission line fixing member including through-electrode
JP5294288B1 (en) * 2012-10-30 2013-09-18 株式会社Leap Method of manufacturing a coil element by electroforming using a resin substrate
WO2014068614A1 (en) 2012-10-30 2014-05-08 株式会社Leap Method for producing coil element using resin substrate and using electroforming
CN107331491A (en) * 2013-08-02 2017-11-07 乾坤科技股份有限公司 Magnetic device
US20160343500A1 (en) * 2015-05-19 2016-11-24 Samsung Electro-Mechanics Co., Ltd. Chip electronic component
US10319515B2 (en) * 2015-05-19 2019-06-11 Samsung Electro-Mechanics Co., Ltd. Chip electronic component
CN112262446A (en) * 2018-07-04 2021-01-22 斯天克有限公司 Coil device and method for manufacturing the same
US12100540B2 (en) 2018-07-04 2024-09-24 Stemco Co., Ltd. Coil device and method for manufacturing the same

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