JPH0575601A - Pseudo random noise generator - Google Patents

Abstract

PURPOSE:To provide a secure PN generating circuit from which the structure of a PN signal and of the PN generating circuit are not analyzed. CONSTITUTION:The PN generating circuit is provided with noise generating means 1a, 1b, 1c, a replacement section 3 and a control section 7. The noise generating means 1 is constituted of a linear feedback shift register means 11 outputting plural pseudo random noise sequences with a control signal selecting plural sequences and a nonlinear logic 13 fetching plural output signals from the register means 11 and outputting one noise signal. The noise signal from each of the noise generating means 1a, 1b, 1c is given to the replacement section 3, in which various combinations are selected by using a switching signal Sk from the control section 7. The setting of the revision, switching and replacement of the noise generating means 1a, 1b, 1c and the replacement section 3 is revised at any time via the control section 7 and the analysis of the structure of a PN signal and a PN generating circuit is disable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo random noise generator for generating pseudo random noise used for scrambling digital data or audio data strings.

[0002]

2. Description of the Related Art Conventionally, a pseudo random noise generator is
It is provided as a generator of pseudo random noise (hereinafter, simply abbreviated as PN) used for scrambling a digital data stream or a voice data stream. Specifically, this PN generating circuit is used, for example, in order to realize the charge for satellite broadcasting. That is, in satellite broadcasting, audio is transmitted as PCM digital data, but when paying for this, it is generally the audio PCM.
Exclusive OR (EXO of digital data and PN series)
R) circuit scrambles by taking exclusive OR to prevent wiretapping.

FIG. 4 is a block diagram showing a simple configuration example of the above-mentioned PN generation circuit. The PN generation circuit shown in FIG. 4 is a linear feedback shift register (LFSR;
linear feedback shift register), and shift registers 401, 403, 405, 407.
And an EXOR circuit 109, and the shift register 40
When 1 is X, the shift register 403 is X ² , the shift register 405 is X ³ , and the shift register 407 is X ⁴ , the output is (X ⁴ + X + 1).

The output of the PN generation circuit is as follows. That is, for example, all "1" are read and LF
When SR is operated, each register 401, 403, 4
The contents of 05 and 407 are as shown in Table 1.

[0005]

[Table 1]

The 16th clock in Table 1 above returns to the original state of all "1", and this is repeated thereafter.
At this time, the output (X ⁴ ) of the register 407 is “1110.
It is a repetition of 00100110101 ". Such P
Even if the number of register stages is increased to n stages and the cycle is lengthened, the N generation circuit has only at most (2 ⁿ -1),
There is a risk that the PN sequence will be searched very easily.

In order to solve this point, the PN shown in FIG.
A generator circuit has been proposed. The PN generation circuit shown in FIG. 5 has LFSRs 511, 513, 515,
The LFSRs 511, 513, and 515 are input with 13 [bits], 11 [bits], and 8 [bits] of the initial value IK that is a scramble key of 32 [bits]. The load timing LT and the shift clock SCk are input to each of the LFSRs 511, 513, and 515. Non-linear logic (NF) 517, 519, 521 is connected to each LFSR 511, 513, 515, and each NF 517, 519, 521 turns each 6 [bit] input into one output. The NF 519 outputs a switching signal to switch the switch 523. NF51
The outputs of 7 and 121 are selected by the switch 523 to be EX.
It is input to the OR circuit 525. In the EXOR circuit 525, the signal selected by the switch 523 and the LFSR 511
Is output as a PN signal.

By using the PN generating circuit which has been made non-linear and has a long period as described above, and further by making it into a custom IC, the PN signal configuration is not actually searched (see "Telecommunications Technology Discussion"). Meeting report, consultation first
No. 7, November 28, 1988 ”). According to the PN generation circuit, even if the PN signal structure is analyzed by using the method of searching the PN signal structure by analyzing the output sequence, the analysis is extremely difficult, and it can be said that the safety is extremely high. ..
However, it cannot always be said that the internal structure of the custom IC chip can be viewed safely with a microscope.

[0009]

As described above, the conventional PN is used.
According to the generation circuit, however complicated the PN signal structure is, it is not safe for the method of analyzing the IC chip after the PN generation circuit is integrated.

Therefore, an object of the present invention is to solve this drawback and provide a safe PN generation circuit in which the configurations of the PN signal and the PN generation circuit itself are not analyzed.

[0011]

In order to achieve the above object, the pseudo random noise generator of the first invention of the present application is
A plurality of linear feedback shift register means capable of changing an output according to an input control signal, and a non-linear logic means constituted by a non-linear logic capable of changing an output according to an inputted control signal and connected to the linear feedback shift register means The gist is to have a linear feedback shift register means and a control means for giving a control signal to the non-linear logic means by a signal inputted from the outside.

In the pseudo random noise generator of the second invention of the present application, a plurality of linear feedback shift register means capable of changing the output according to the input control signal, and the control input to the linear feedback shift register means. And a switching means for switching the signals from the plurality of linear feedback shift register means by a signal, and a control means for giving a control signal to the linear feedback shift register means and the switching means by a signal input from the outside. To do.

The pseudo random noise generator of the third invention of the present application comprises a plurality of linear feedback shift register means capable of changing the output according to the input control signal, and a non-linear logic capable of changing the output according to the input control signal. Non-linear logic means configured and connected to the linear feedback shift register means, exchange means connected to the non-linear logic means for exchanging signals from the plurality of non-linear logic means by a control signal input, and input from the outside It is characterized in that it has a linear feedback shift register means, a non-linear logic means, and a control means for giving a control signal to the exchange means according to the signal.

[0014]

According to the above construction, the constructions of the plurality of linear feedback shift register means and the non-linear logic means can be changed by the control signal, and further, the setting of the exchange of these output signals can be changed at any time. Even if the chip of the IC is analyzed by a microscope, the structure of the PN signal and the PN generation circuit cannot be analyzed and the safety is improved.

[0015]

The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of a PN generating circuit as a pseudo random noise generating device according to the present invention. The PN generating circuit shown in FIG. 1 includes three types of noise generating means 1a, 1b, 1c, and these means 1a, 1b,
Switching unit 3 for switching the output signals from 1c
And a switch 5 for switching the output from the replacement unit 3,
The control unit 7 controls the generation sequence of the means 1a, 1b and 1c and the switching of the replacement unit 3.

The noise generating means 1a is a linear feedback shift register means 11 for outputting a plurality of pseudo random noise sequences in response to a control signal Sc from the control section 7.
a, two non-linear logics 13ax, 13ay that take in a plurality of output signals from the register means 11a and output one noise signal, and the non-linear logics 13ax, 1
A switch 15 for selecting one of the outputs of 3ay according to the switching signal Sk from the control unit 7. The noise generating means 1b takes in a plurality of output signals from the linear feedback shift register means 11b which outputs a plurality of pseudo random noise sequences according to a control signal for selecting a plurality of sequences, and a plurality of output signals from the linear feedback shift register means 11b. It is composed of a nonlinear logic 13b that outputs a noise signal of a book. The noise generating means 1c takes in a linear feedback shift register means 11c for outputting a plurality of pseudo random noise sequences by a control signal for selecting a plurality of sequences, and a plurality of output signals from the linear feedback shift register means 11c. It is composed of a nonlinear logic 13c that outputs a noise signal of a book. The replacing unit 3 replaces the noise signals from the noise generating means 1a, 1b, 1c into various combinations by the replacement signal Se from the control unit 7, and the selectors 31a, 31.
b, 31c. Each selector 31a, 3
1b and 31c take in the output signals from the respective noise generating means 1a, 1b and 1c and select one by the replacement signal Se. One of the outputs of each selector 31a, 31b, 31c is selected by the switch 5. The signals shown in Table 2 are input to the switch 5.

[0018]

[Table 2]

The control unit 7 can be realized by a simple latch. Then, the control signal Sc output from the control unit 7
One is input to each of the register means 11a, 11b, 11c, and a total of three are input. If one switching signal Sk and six replacement signals Se are combined, this configuration has 2 ³ × 2.
¹ × 6 = 96 kinds can be taken. The combination of the control signal Sc, the switching signal Sk, and the replacement signal Se of the control unit 7 can be changed at any time by the control signal CTL from the transmitting station side, and the receiver incorporating this IC can be operated by some key operation. The combination can be changed by the constructed control signal CTL.

FIG. 2 is a block diagram showing a configuration example of the linear feedback shift register means. In FIG. 2, the linear feedback shift register means 11a, 1
Since the configurations of 1b and 11c are basically the same, reference numerals a, b and c will be described. The linear feedback shift register means 11 includes shift registers 111 and 11
3,115,117 and EXOR circuits 119,121
And AND circuits 123 and 125. When the control signal Sc input to the AND circuits 123 and 125 is “1”, the output of (X ⁴ + X ³ +1) is when the control signal Sc is “0”. The output of (X ⁴ + X + 1) is obtained. Generally, M-stage register means 11a, 11
b and 11c, some configurations in which the cycle is (2 ^M −1) are known, and when three or more types are used, the control signal Sc
Need to be multiple. In general, the number of "1" s and "0s" is set to 50% each so that an output with little correlation with an input change is output.

FIG. 3 is a block diagram showing a configuration example of the non-linear logic. The non-linear logics 13ax, 13ay, the non-linear logic 13b, and the non-linear logic 13c can be generally composed of a combination of an AND circuit, an OR circuit, and an EXOR circuit, but a read-only memory (ROM) can be used most easily. In FIG. 3, the switch 131 is connected to the input terminal.
Is provided to enable input of 7 addresses. 6 address inputs obtained through the switch 131 are stored in the ROM 13
Taken in 3 and got one output. ROM 133
Stores the data example shown in Table 3. ROM13
3 can output a value corresponding to 2 [bits] of the upper address and 4 [bits] of the lower address shown in Table 1.

[0022]

[Table 3]

The operation of the embodiment thus constructed will be described.

The control unit 7 includes register means 11a and 11a.
A control signal Sc is given to b and 11c. Further, each of the register means 11a, 11b, 11c receives the control signal Sc from the control signal Sc, as can be seen from the configuration of FIG. 2, for example.
Is “1”, the output of (X ⁴ + X ³ +1) is the control signal S
If c is "0", (X ⁴ + X + 1) is obtained. That is, when the control signal Sc is “0”, the AND circuit 125.
Output becomes "0" regardless of the feedback signal 127, and the input on one side of the EXOR circuit 121 becomes "0".
That is, the EXOR circuit 121 simply serves as a buffer. When the control signal Sc is "1", the output of the AND circuit 123 and the input on one side of the EXOR circuit 119 are "0", and the EXOR circuit 119 serves as a simple buffer. At this time, another PN sequence will be generated. From the register means 11a which outputs such an output signal, a plurality of outputs are output from the non-linear logic 13ax,
13ay, a plurality of outputs from the register means 11b are input to the non-linear logic 13b, and a plurality of outputs from the register means 11c are input to the non-linear logic 13c. Non-linear logic 13ax, 13ay, non-linear logic 1
The 3b and the non-linear logic 13c each output one output. One of the non-linear logics 13ax and 13ay is selected by the switch 15 that is switched by the switching signal Sk from the control unit 7, and is output as the noise signal a. The noise signal b from the non-linear logic 13b is
A noise signal c is output from c. The noise signals a, b, and c are output to the three selectors 31 of the replacement unit 3.
a, 31b, 31c, respectively. Replacement part 3
The selectors 31a, 31b, 31c are provided with the replacement signal Se from the control unit 7, whereby one of the noise signals a, b, c is selected, and six kinds of states as shown in Table 2 are selected. Will be replaced by. Each selector 31a, 31
The outputs of b and 31c are "0", "1" of the switch 5,
It is supplied to the "S" input. That is, the three selectors 31a, 31b, 31c are the three noise generating means 1
The noise signals a, b, and c from a, 1b, and 1c are input to the switch 5 to select any one of six combinations.

As described above, in this embodiment, the control signals Sc,
The combination of the switching signal Sk and the replacement signal Se can be changed by the control signal CTL from the transmitting station side at any time, or the combination can be changed by the control signal CTL configured by some key operation in the receiver incorporating this IC. Since it is possible to easily change the configuration of the PN generation circuit even if the contents of the IC are analyzed, it is almost impossible to search the configuration of the PN generation circuit. is there.

Although three types of methods have been described in the above embodiment, it is of course possible to use two types of switching.

Further, according to the present embodiment, the configuration of the PN generation circuit can be easily changed even if an IC is copied and a pirated copy is circulated. Therefore, the investment of several hundred million yen for scrambled broadcasting is completely wasted. It has a great effect that it can be prevented.

[0028]

As described above, according to the present invention, the configuration of the PN generating circuit itself can be easily changed by adding a few circuits. Therefore, even if the IC is analyzed, the PN generating circuit is sufficiently safe. Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of register means used in the present invention.

FIG. 3 is a block diagram showing a configuration example of a non-linear logic used in the present invention.

FIG. 4 is a block diagram showing a conventional PN generation circuit.

FIG. 5 is a block diagram showing another conventional PN generation circuit.

[Explanation of symbols]

 1a noise generating means 1b noise generating means 1c noise generating means 3 switching section 5 switch 7 control section 11a register means 11b register means 11c register means 13ax non-linear logic 13ay non-linear logic 13b non-linear logic 13c non-linear logic 31a selector 31b selector 31c selector

Claims (3)

[Claims] 1. A plurality of linear feedback shift register means capable of changing an output according to an input control signal and a non-linear logic capable of changing an output according to an input control signal, and connected to the linear feedback shift register means. And a non-linear logic means, a linear feedback shift register means by a signal inputted from the outside, and a control means for giving a control signal to the non-linear logic means. 2. A plurality of linear feedback shift register means capable of changing an output according to an input control signal, and a plurality of linear feedback shift register means connected to the linear feedback shift register means, the control signals being input from the linear feedback shift register means. A pseudo-random noise generating device, comprising: a switching means for switching the signals of (1), a linear feedback shift register means by a signal input from the outside, and a control means for giving a control signal to the switching means. 3. A plurality of linear feedback shift register means capable of changing an output according to an input control signal, and a non-linear logic capable of changing an output according to an input control signal, and connected to the linear feedback shift register means. And a non-linear logic means connected to the non-linear logic means for exchanging signals from the plurality of non-linear logic means according to an input control signal, and a linear feedback shift register means for non-linear with the externally input signal. A pseudo random noise generator comprising: a control means for applying a control signal to the logic means and the replacement means.