JPH0574945A - Semi-custom integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semi-custom integrated circuit in which a pad vacant space cab be effectively used if the number of power source terminals is increased, an increase in the area of a chip more than required upon increase of the number of the terminals is prevented and a chip manufacturing cost can be suppressed. CONSTITUTION:In a semi-custom integrated circuit, pads 12 are disposed on a pad disposing region of the periphery of a chip, peripheral circuit cells 13 are disposed on a region inside the pads, inner circuits 14 are disposed on a region inside the cells 13, and a power source line 15 is so disposed as to be superposed on the cells 13. Further, a power source supply cell 20 is so disposed as to be superposed on the cell in which connections to the pads are not required on the disposing region of the cells 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semi-custom integrated circuit (IC) such as a gate array or a standard cell type LSI (large scale integrated circuit), and more particularly to its chip layout.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a pattern layout of output buffer cells 60 arranged in a peripheral circuit region inside a peripheral pad arrangement region on a conventional semi-custom IC chip.

Here, the output cells 61 ... Are composed of, for example, inverter circuits connected in two stages. Generally, when a large current output that is insufficient with the output current of the output cell alone is required, a method of connecting two output cells 61 ... In parallel is adopted. That is, each input of the two output cells 61 ... Is commonly connected by the wiring 62, and each output is commonly connected by the wiring 63 to the pad 64. In this case, the pad 64 is placed in the pad placement area corresponding to the output cell 61 on one side.
Are arranged, but the pad arrangement area corresponding to the output cell 61 on the other side is a space where no pads are arranged (pad empty space 65). Similarly, when a plurality of input cells are connected in parallel, a space in which pads are not arranged (pad empty space) occurs.

FIG. 7 shows an example of the pattern layout of the internal circuit driving cells 71 arranged in the peripheral circuit area inside the peripheral pad arrangement area on the chip of the conventional semi-custom IC.

The internal circuit driving cell 71 is composed of, for example, two-stage connected inverter circuits, and is connected to the internal circuit by a wiring 72. Generally, when a large current output is required to drive a clock line having a large load, or when power supply noise at the time of switching a buffer must be taken into consideration, the internal circuit driving cell 71 is used.
Is arranged in the peripheral circuit area. In this case, since the internal circuit driving cell 71 does not need to be connected to the pad, the pad arrangement area corresponding to the internal circuit driving cell 71 is the pad empty space 73.

By the way, in recent years, the number of terminals of a chip has been increasing more and more as the degree of integration of LSI is improved by the development of miniaturization technology. On the other hand, due to the parasitic inductance of the wiring and the resonance circuit composed of the load capacitance connected to the output line of the output cell, a large voltage fluctuation occurs in the power supply line and the output line during driving, and as a result, the power supply voltage fluctuates,
Malfunction or CMO of other elements connected to the same power line
There is a problem that the latch-up phenomenon of the S circuit is induced. In order to prevent this, the number of power supply terminals of the chip tends to increase for the purpose of stabilizing the power supply voltage.

However, in the conventional semi-custom IC as described above, a part of many input / output cells and the internal circuit driving cell 71 have the pad empty spaces 65 and 73 as described above. Regardless, he was not using the area effectively.

Even if the predetermined number of terminals required for using the above semi-custom IC is realized in such a state, the chip area unnecessarily increases as the number of power supply terminals increases, and as a result, However, there is a problem that the manufacturing cost of the chip becomes high.

[0009]

As described above, since the conventional semi-custom integrated circuit does not effectively utilize the pad empty space even though it has the empty space, the chip area becomes larger than necessary. Therefore, there is a problem that the manufacturing cost of the chip becomes high.

The present invention has been made to solve the above-mentioned problems, and when the number of power supply terminals is increased, the pad empty space can be effectively utilized, and the chip area becomes larger than necessary as the number of power supply terminals increases. It is an object of the present invention to provide a semi-custom integrated circuit which can prevent the increase and suppress the manufacturing cost of chips.

[0011]

According to the present invention, pads are arranged in a pad arrangement area around a chip, peripheral circuit cells are arranged in an area inside the pad, and an internal circuit is arranged in an area inside the pad. In a semi-custom integrated circuit in which a power supply line is arranged so as to overlap with the peripheral circuit cell, a power supply cell is arranged so as to overlap with a cell that does not need to be connected to a pad in the arrangement region of the peripheral circuit cell. It is characterized by

[0012]

In the peripheral circuit cell arrangement area, the power supply cells are arranged so as to overlap the specific cells which do not need to be connected to the pads, and the pad empty space corresponding to the specific cells is effectively used. ing. Therefore, even if the number of power supply terminals of the chip is increased in order to stabilize the power supply voltage in order to prevent large voltage fluctuations in the power supply line and output line when driving the high current input / output buffer, the chip area Can be prevented from increasing more than necessary, and the manufacturing cost of the chip can be reduced. Moreover, it becomes possible to supply the power to the cell for the large current input / output buffer through the power supply cell and the power supply line arranged thereon, and suppress the voltage fluctuation occurring in the power supply line at the time of driving the buffer, It is possible to suppress the malfunction of other elements connected to the same power line and the induction of the latch-up phenomenon of the CMOS circuit.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a chip layout in one embodiment of a semi-custom IC according to the present invention.

In the chip 11 shown in FIG. 1, pads 12 are arranged in a pad arrangement area around the chip, and peripheral circuit cells 13 such as input / output circuit cells are arranged in a peripheral circuit area inside thereof at a constant pitch. Further, the internal circuit 14 is arranged in the area inside thereof. The power supply line 15 is arranged so as to overlap the peripheral circuit cells 13 ...

In this embodiment, the input / output cells and / or cells which do not need to be connected to the pad 12 in the peripheral circuit area are provided.
Alternatively, the power supply cells are arranged so as to overlap the internal circuit driving cells.

FIG. 2 shows an example of a pattern layout of the output buffer cells in the peripheral circuit area in FIG. 1 and the power supply lines and power supply cells arranged so as to overlap therewith. Here, 60 is an output buffer cell, 151 is a VDD power supply line, 152 is a VSS power supply (ground potential) line, and 20 is a power supply cell.

As the output buffer cell 60, for example, an output cell 61 composed of two-stage connected inverter circuits is used as in the conventional example described with reference to FIG. Then, when a large current output that is insufficient with the output current of the output cell alone is required, a method of connecting two output cells 61 in parallel is adopted. That is, each input of the two output cells 61 is commonly connected by the wiring 62, and each output is commonly connected to the pad by the wiring 63. In this case, the pads 12 are arranged in the pad arrangement area corresponding to the output cells 61 on one side, but the pads are arranged in the pad arrangement area corresponding to the output cells 61 on the other side (pad empty space). ).

On the other hand, the power supply cell 20 includes a power supply pad 12 and the power supply pad 12 connected to the VDD power supply line 1.
The wiring 22 and the contact hole 23 for connecting to 51 are provided. In this case, the power supply pad 12 is arranged in the pad empty space corresponding to the output cell.
Further, the power supply cells can be arranged in the pad vacant space generated when a plurality of input cells are connected in parallel. FIG. 3 is a diagram showing an example of a sectional structure of the wiring layers of the output buffer cell 60, the VDD power supply line 151 and the power supply cell 20 of FIG.

Reference numeral 30 denotes a semiconductor substrate (for example, a silicon substrate), 31 denotes a drain / source region of an output cell MOS transistor which is diffused and formed in a part of a substrate surface layer portion, and 32.
Is a gate insulating film formed on the surface of the substrate, 33 is a gate electrode of the output cell MOS transistor, 34 is a first-layer metal wiring connected to the drain / source region 31, 3
5 is an interlayer insulating layer, 36 is a second-layer metal wiring for the VDD power supply line 151, 12 is a power supply pad of the power supply cell 20,
23 is a contact hole opened in the interlayer insulating layer 35,
22 is the power supply pad 1 through the contact hole 23
A second layer metal wiring 36 for connecting 2 to the second layer metal wiring 36 for the VDD power supply line 151, and 37 is a surface protective film. Here, the power supply pad 12 and the third-layer metal wiring 22 forming the power supply cell 20 are separated from the other elements and wiring layers by the interlayer insulating layer 35, and a defect such as a short circuit does not occur.

FIG. 4 shows an example of a pattern layout of the internal circuit driving cells in the peripheral circuit region in FIG. 1 and the power supply lines and the power supply cells arranged so as to overlap therewith.

Here, the internal circuit driving cell 71 is composed of, for example, two-stage connected inverter circuits as in the conventional example described above with reference to FIG. 7, and is connected to the internal circuit by the wiring 72. And when a high current output is required to drive a clock line with a large load,
When it is necessary to consider the power supply noise when the buffer switches, a method of arranging the internal circuit driving cell 71 in the peripheral circuit region is used. in this case,
Since the internal circuit driving cell 71 does not need an input / output pad for interfacing with the outside, the pad arrangement area corresponding to the internal circuit driving cell 71 is a pad empty space.

On the other hand, the power supply cell 20 includes a power supply pad 12 and the power supply pad 12 connected to the VDD power supply line 1.
The wiring 22 and the contact hole 23 for connecting to 51 are provided. In this case, the power supply pad 12 is arranged in a pad empty space corresponding to the internal circuit driving cell 71. In addition, the power supply pad 12 and the wiring 2
2 is a cell 71 for driving an internal circuit and a VDD power supply line 151
It is formed in a wiring layer different from that of the above, and is separated from other elements and wiring layers by an interlayer insulating layer, so that a defect such as a short circuit does not occur.

As described above, according to the semi-custom IC of the present embodiment, the power supply cells are arranged so as to overlap with the specific cells which need not be connected to the pads in the peripheral circuit cell arrangement area. The pad empty space corresponding to a specific cell is effectively used. Therefore, even if the number of power supply terminals of the chip is increased in order to stabilize the power supply voltage in order to prevent large voltage fluctuations in the power supply line and output line when driving the high current input / output buffer, the chip area Can be prevented from increasing more than necessary, and the manufacturing cost of the chip can be reduced. Moreover, it becomes possible to supply power to the high-current input / output buffer cell through the power supply cell and the power supply line arranged above the cell, and suppress the voltage fluctuation occurring in the power supply line when the buffer is driven. It is possible to suppress the malfunction of other elements connected to the power supply line and the induction of the latch-up phenomenon of the CMOS circuit.

FIG. 5 shows another example of the pattern layout of the internal circuit driving cells in the peripheral circuit region in FIG. 1 and the power supply lines and power supply cells arranged so as to overlap therewith.

In this example, as compared with the example shown in FIG. 4, the wiring 22 'of the power supply cell 20 has the VSS power supply line 152.
4 is the same as that of FIG. 4 except that the power supply pad 12 is connected to the VSS power supply line 152 and that the power supply pad 12 is connected to the VSS power supply line 152. In this example, the same effect as the above example can be obtained.

[0026]

As described above, according to the present invention, it is possible to effectively use the pad empty space when increasing the number of power supply terminals, and to increase the chip area more than necessary as the number of power supply terminals increases. It is possible to realize a semi-custom integrated circuit which can prevent the cost and suppress the manufacturing cost of the chip.

[Brief description of drawings]

FIG. 1 is a diagram showing a chip layout in one embodiment of a semi-custom IC according to the present invention.

FIG. 2 is a diagram showing an example of a pattern layout of output buffer cells in a peripheral circuit area in FIG. 1, power supply lines arranged so as to overlap therewith, and power supply cells.

FIG. 3 is a diagram showing an example of a cross-sectional structure of an output buffer cell, a power supply line, and a wiring layer of a power supply cell of FIG. 2;

FIG. 4 is a diagram showing an example of a pattern layout of internal circuit driving cells in a peripheral circuit region in FIG. 1 and power supply lines and power supply cells arranged so as to overlap therewith.

5 is a diagram showing another example of the pattern layout of the internal circuit driving cell in the peripheral circuit region in FIG. 1 and the power supply line and the power supply cell arranged so as to overlap therewith.

FIG. 6 is a diagram showing a pattern layout of output buffer cells in a conventional semi-custom IC.

FIG. 7 is a diagram showing a pattern layout of cells for driving an internal circuit in a conventional semi-custom IC.

[Explanation of symbols]

11 ... Chip, 12 ... Pad, 13 ... Peripheral circuit cell, 1
4 ... Internal circuit, 15 ... Power supply line, 151 ... VDD power supply line, 152 ... VSS power supply line, 20 ... Power supply cell,
22, 22 '... Wiring, 23 ... Contact hole, 30 ...
Semiconductor substrate, 31 ... Drain / source region of output cell MOS transistor, 32 ... Gate insulating film, 33 ... Gate electrode of output cell MOS transistor, 34 ... First-layer metal wiring, 35 ... Interlayer insulating layer, 36 ... Two Layer metal wiring, 37 ... Surface protective film, 60 ... Output buffer cell, 6
2 ... Input wiring, 63 ... Output wiring, 64 ... Output cell pad, 71 ... Internal circuit driving cell, 72 ... Internal circuit connecting wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 27/04 D 8427-4M E 8427-4M

Claims (4)

[Claims] 1. A pad is arranged in a pad arrangement area around a chip, and a peripheral circuit cell is arranged in an area inside thereof.
Further, in the semi-custom integrated circuit in which the internal circuit is arranged in the area inside thereof and the power supply line is arranged so as to overlap with the peripheral circuit cell, it is not necessary to connect to the pad in the arrangement area of the peripheral circuit cell. A semi-custom integrated circuit in which power supply cells are arranged so as to overlap with the cells. 2. The semi-custom integrated circuit according to claim 1, wherein the cell that does not need to be connected to the pad is a part of input / output cells connected in parallel. 3. The semi-custom integrated circuit according to claim 1, wherein the cell that does not need to be connected to the pad is an internal circuit driving cell. 4. The semi-custom integrated circuit according to claim 1, wherein the power supply cell is
A semi-custom integrated circuit comprising: a power supply pad arranged in a pad arrangement area corresponding to a cell that does not need to be connected to the pad; and a wiring for connecting the power supply pad to the power supply line.