JPH0571129B2 - - Google Patents
Info
- Publication number
- JPH0571129B2 JPH0571129B2 JP16285A JP16285A JPH0571129B2 JP H0571129 B2 JPH0571129 B2 JP H0571129B2 JP 16285 A JP16285 A JP 16285A JP 16285 A JP16285 A JP 16285A JP H0571129 B2 JPH0571129 B2 JP H0571129B2
- Authority
- JP
- Japan
- Prior art keywords
- mask material
- etching
- groove
- silicon
- layer mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000463 material Substances 0.000 claims description 59
- 238000005530 etching Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 29
- 238000001020 plasma etching Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 47
- 229910052710 silicon Inorganic materials 0.000 description 47
- 239000010703 silicon Substances 0.000 description 47
- 239000010410 layer Substances 0.000 description 25
- 238000002955 isolation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- IRPGOXJVTQTAAN-UHFFFAOYSA-N 2,2,3,3,3-pentafluoropropanal Chemical compound FC(F)(F)C(F)(F)C=O IRPGOXJVTQTAAN-UHFFFAOYSA-N 0.000 description 1
- KLZUFWVZNOTSEM-UHFFFAOYSA-K Aluminum fluoride Inorganic materials F[Al](F)F KLZUFWVZNOTSEM-UHFFFAOYSA-K 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に能
動素子間の分離領域の形成に好適な半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device suitable for forming isolation regions between active elements.
従来、半導体装置における能動素子間分離法と
しては、LOCOS（選択酸化法）が広く採用されて
きた。
Conventionally, LOCOS (selective oxidation method) has been widely adopted as a method for separating active elements in semiconductor devices.
しかし、この方法では、熱酸化により素子間分
離領域が膨脹して実効的に拡大し、半導体装置の
高集積化の妨げとなつていた。また、素子間分離
領域のシリコン酸化膜と素子領域のシリコン基板
との間には、シリコン酸化膜厚の約半分の表面段
差があり、配線歩留りを低下させていた。 However, in this method, the isolation region between elements expands and becomes effectively enlarged due to thermal oxidation, which hinders higher integration of semiconductor devices. Furthermore, there is a surface step difference of approximately half the thickness of the silicon oxide film between the silicon oxide film in the element isolation region and the silicon substrate in the element region, which reduces wiring yield.
このような問題点を解決する一方法として、シ
リコン基板の表面層に溝を形成し、熱酸化により
溝の内壁にシリコン酸化膜を形成することにより
溝を充填する方法（特開昭51−31186号）や、多
結晶シリコン膜を溝の内壁に形成し、これを熱酸
化することにより溝を充填する方法（特開昭58−
33851号）などが考案され、近年このようなシリ
コン基板に深い溝を形成し、シリコン酸化物でこ
れを充填する素子間分離法（溝分離法と呼称す
る）が注目されてきている。 One method to solve these problems is to form a groove in the surface layer of a silicon substrate and fill the groove by forming a silicon oxide film on the inner wall of the groove by thermal oxidation (Japanese Patent Laid-Open No. 51-31186). (No.), and a method of filling the groove by forming a polycrystalline silicon film on the inner wall of the groove and thermally oxidizing it (Japanese Unexamined Patent Publication No. 1983-
33851), and in recent years, an element isolation method (referred to as trench isolation method), in which deep trenches are formed in such silicon substrates and filled with silicon oxide, has been attracting attention.
このような溝分離法を実現するには、例えばシ
リコンからなる基板表面に深く且つ、垂直な溝を
形成する必要がある。深い垂直な溝を形成するに
は、反応性ガスのプラズマ放電による反応性イオ
ンエツチング法が適している。しかし、この反応
性イオンエツチング法を用いても、反応ガスの選
択とエツチング条件を適切にしないと溝の側壁に
アンダカツトが生じたり、溝の側壁がテーパ状に
なつたりしてしまう。
In order to realize such a trench separation method, it is necessary to form deep and perpendicular trenches in the surface of a substrate made of silicon, for example. Reactive ion etching using plasma discharge of a reactive gas is suitable for forming deep vertical grooves. However, even if this reactive ion etching method is used, if the selection of the reactive gas and etching conditions are not appropriate, undercuts may occur on the sidewalls of the grooves, or the sidewalls of the grooves may become tapered.
溝の側壁にアンダカツトがあると、溝内部に充
填すべき例えば多結晶シリコン膜を一様に形成す
ることができず、製造歩留りを低下させるととも
に、素子分離特性を不安定にする原因となる。 If there is an undercut on the side wall of the trench, it is not possible to uniformly form, for example, a polycrystalline silicon film to be filled inside the trench, which lowers the manufacturing yield and causes instability of device isolation characteristics.
また、溝の側壁がテーパ状になると、溝の断面
形状がＶ字状になつてしまい、深い微細溝が形成
できなくなり、高集積化は不可能となる。 Furthermore, if the side walls of the groove become tapered, the cross-sectional shape of the groove becomes V-shaped, making it impossible to form deep fine grooves and making it impossible to achieve high integration.
また、深いシリコン溝を形成するために、単層
マスクを用いて長時間エツチングする場合には、
マスク材の膜減りが進行するにつれて、マスク材
の横方向の後退が生じ、これに起因して溝の側壁
に、溝の中程から上に向つてテーパ状の傾斜がつ
いてしまい、溝形状の寸法精度が得られなくな
る。 In addition, when etching is performed for a long time using a single layer mask to form deep silicon grooves,
As the film thinning of the mask material progresses, the mask material recedes in the lateral direction, causing the side walls of the groove to taper upward from the middle of the groove, resulting in a change in the groove shape. Dimensional accuracy cannot be obtained.
本発明はこのような従来の問題点を解決するた
めになされたものである。 The present invention has been made to solve these conventional problems.
上記問題点を解決するため、本発明は、基板上
に上層マスク材と、上記基板の下記エツチング中
にマスク開口端で上に向かつて広がる傾斜が得ら
れる酸化シリコン材料でできた下層マスク材とか
らなるマスクパターンを形成する工程と、上記基
板を反応性イオンエツチング法により上記上層マ
スク材をマスクとして該上層マスク材がなくなる
までエツチングし、上記基板に断面形状がほぼ矩
形の溝を形成する工程と、上記基板を反応性イオ
ンエツチング法により上記下層マスク材をマスク
として該下層マスク材の膜厚が初期膜厚のほぼ1/
２より小さくなるまでエツチングし、上記溝の開
口端近傍の側壁に上に向かつて広がる傾斜をつけ
る工程とを具備することを特徴とする。
In order to solve the above-mentioned problems, the present invention provides an upper layer mask material on a substrate, and a lower layer mask material made of a silicon oxide material that obtains an upwardly widening slope at the mask opening edge during the following etching of the substrate. a step of etching the substrate using a reactive ion etching method using the upper layer mask material as a mask until the upper layer mask material is removed, and forming a groove having a substantially rectangular cross section in the substrate; Then, using the lower layer mask material as a mask, the substrate is etched by reactive ion etching until the film thickness of the lower layer mask material is approximately 1/1/1 of the initial film thickness.
The method is characterized by comprising a step of etching the groove to a size smaller than 2, and forming an upwardly widening slope on the side wall near the opening end of the groove.
上記のように基板をエツチングすることによ
り、開口端近傍の側壁に上に向かつて広がる傾斜
を有し、その下部の側壁の断面形状がほぼ矩形の
溝を形成することができる。このような溝には、
該溝に充填すべき物質を該溝の内部全体にわたつ
て均質に充填することができる。
By etching the substrate as described above, it is possible to form a groove in the side wall near the opening end, which has a slope that widens upward, and whose lower side wall has a substantially rectangular cross-sectional shape. In such grooves,
The substance to be filled into the groove can be filled uniformly throughout the interior of the groove.
第１図Ａ〜Ｅはそれぞれ本発明の実施例を示す
工程断面図である。
FIGS. 1A to 1E are process cross-sectional views showing embodiments of the present invention.
第１図Ａはシリコン基板１上に上層マスク材
２、および下層マスク材３からなるマスクパター
ンが形成されている断面構造を示すものである。 FIG. 1A shows a cross-sectional structure in which a mask pattern consisting of an upper layer mask material 2 and a lower layer mask material 3 is formed on a silicon substrate 1.
すなわち、まずシリコン基板１を熱酸化して厚
さ4000〜5000ÅのSiO2膜を形成して下層マスク
材３とし、次にこの上にスパツタリング法により
厚さ5000Åのモリブデン、タンタル等の金属膜を
形成して上層マスク材２とする。 That is, first, a silicon substrate 1 is thermally oxidized to form a SiO 2 film with a thickness of 4,000 to 5,000 Å to serve as the lower mask material 3, and then a metal film of molybdenum, tantalum, etc. with a thickness of 5,000 Å is deposited on top of this by sputtering. The upper layer mask material 2 is formed by forming the upper layer mask material 2.
このようにして形成した上層マスク材２及び下
層マスク材３から成るマスク材を上層マスク材２
の上に形成したレジストパターンをマスクにし
て、通常のホトエツチング法により選択エツチン
グを行ない、レジストパターンをマスク材に転写
する。 The mask material consisting of the upper layer mask material 2 and the lower layer mask material 3 formed in this way is used as the upper layer mask material 2.
Using the resist pattern formed on the mask as a mask, selective etching is performed using a conventional photoetching method to transfer the resist pattern to the mask material.
このようにしてパターン化したマスク材を用い
て、シリコン基板１をエツチングした場合のマス
ク材及びシリコン基板１のエツチングプロフアイ
ルについて説明する。 The mask material and the etching profile of the silicon substrate 1 when the silicon substrate 1 is etched using the mask material patterned in this manner will be described.
まず、反応性イオンエツチング法により、第１
図Ａに示すようなマスクパターンを有する試料を
エツチングすると、シリコン基板１は上層マスク
材２をエツチングマスクにして選択エツチされ
る。上層マスク材２によるシリコン基板１のエツ
チング過程を第１のエツチング過程と呼称する。 First, by reactive ion etching method, the first
When a sample having a mask pattern as shown in FIG. A is etched, the silicon substrate 1 is selectively etched using the upper layer mask material 2 as an etching mask. The process of etching the silicon substrate 1 using the upper mask material 2 is referred to as a first etching process.
第１のエツチング過程において、シリコン基板
１のエツチレートが上層マスク材２のエツチレー
トより数倍大きければ、上層マスク材２の膜厚の
ほぼ数倍の深さのシリコン溝を形成することがで
きる。しかも、上層マスク材２に対するシリコン
の選択比が大きければ、マスク材の横方向の後退
が少ないのでシリコン溝の断面形状にほぼ矩形に
形成される。例えば、本実施例のように、上層マ
スク材２としてモリブデン膜を用いた場合、反応
ガスにCBrF3とO2との混合ガスを用い、圧力
20mTorr、RF電力密度0.18W／cm2のエツチング
条件において、モリブデンのエツチレートは700
Å／minであつた。この条件で膜厚4000Åのモリ
ブデン膜が消失するまでエツチングしたところ、
第１図Ｂに示すように、深さ約2μmのほぼ垂直側
壁を有する断面形状がほぼ矩形のシリコン溝４を
形成することができた。 In the first etching process, if the etching rate of the silicon substrate 1 is several times greater than the etching rate of the upper mask material 2, a silicon groove with a depth approximately several times the thickness of the upper mask material 2 can be formed. Furthermore, if the selection ratio of silicon to the upper mask material 2 is large, the mask material recedes less in the lateral direction, so that the cross-sectional shape of the silicon groove is substantially rectangular. For example, when a molybdenum film is used as the upper layer mask material 2 as in this example, a mixed gas of CBrF 3 and O 2 is used as the reaction gas, and the pressure is
Under etching conditions of 20mTorr and RF power density of 0.18W/ cm2 , the etching rate of molybdenum is 700
The temperature was Å/min. Etching was performed under these conditions until the molybdenum film with a thickness of 4000 Å disappeared.
As shown in FIG. 1B, it was possible to form a silicon groove 4 having a depth of about 2 μm and a substantially rectangular cross-sectional shape and having substantially vertical side walls.
つぎに、さらに、エツチングを継続して、下層
マスク材３によるシリコン基板１のエツチングを
行なう。このエツチング過程を第２のエツチング
過程と呼称する。 Next, etching is continued to etch the silicon substrate 1 using the lower mask material 3. This etching process is called a second etching process.
第２のエツチング過程において、例えば、本実
施例において、下層マスク材３にシリコンに対す
るエツチレート比が1/2ないし1/3のSiO2膜を使
用すると、第１図Ｃに示すように下層マスク材３
の開口端（肩部）３０ではイオンのスパツタ収率
が高いために、角がとれて傾斜３１がつく。この
傾斜３１はエツチングの進行とともに強調され、
かつ、下層マスク材３の膜減りに伴つて下方へ移
動していく。 In the second etching process, for example, in this embodiment, if a SiO 2 film with an etching rate of 1/2 to 1/3 to silicon is used as the lower mask material 3, the lower mask material 3 is etched as shown in FIG. 3
Since the sputtering yield of ions is high at the open end (shoulder part) 30 of the opening end (shoulder part), the angle is rounded and a slope 31 is formed. This slope 31 is emphasized as the etching progresses,
Moreover, as the film of the lower mask material 3 decreases, it moves downward.
さらに、つづけてエツチングを行ない、ある一
定時間経過すると、第１図Ｄに示すように、傾斜
３１の下端がシリコン基板１の表面に達する。す
ると、この時点を境にして下層マスク材３が横方
向に後退しはじめる。 Further, etching is continued, and after a certain period of time has elapsed, the lower end of the slope 31 reaches the surface of the silicon substrate 1, as shown in FIG. 1D. Then, after this point, the lower mask material 3 begins to recede in the lateral direction.
下層マスク材３が横方向に後退すると、シリコ
ン溝４の開口端におけるシリコンは、反応性イオ
ン種にさらされるため急速にエツチングされ、第
１図Ｅに示すように、シリコン溝４の開口端近傍
に傾斜４１がつく。 When the lower mask material 3 recedes laterally, the silicon at the open end of the silicon groove 4 is exposed to reactive ion species and is rapidly etched, as shown in FIG. A slope 41 is added to the line.
この傾斜４１の角度は膜減りした下層マスク材
３の開口端における傾斜３１の角度と下層マスク
材３に対するシリコンのエツチレート比に依存
し、これらはエツチング条件によつて変る。例え
ば、本実施例のように、下層マスク材３にSiO2
膜を用いた場合、上記のエツチング条件において
は、SiO2膜に対するシリコンのエツチレート比
は約３であつた。また、このときのシリコン基板
１表面とシリコン溝４の開口端近傍の傾斜４１と
のなす角度θは約75°であつた（第１図Ｆ）。 The angle of this inclination 41 depends on the angle of the inclination 31 at the open end of the lower mask material 3 whose thickness has been reduced and the etching rate ratio of silicon to the lower mask material 3, and these change depending on the etching conditions. For example, as in this embodiment, SiO 2 is added to the lower mask material 3.
When a film was used, the etching rate ratio of silicon to SiO 2 film was about 3 under the above etching conditions. Further, at this time, the angle θ between the surface of the silicon substrate 1 and the slope 41 near the opening end of the silicon groove 4 was about 75° (FIG. 1F).
したがつて、シリコン溝４の開口端近傍に傾斜
４１を形成するには、下層マスク材３の開口端３
０に傾斜３１がつくことが必要である。しかし、
下層マスク材３の膜厚があまり薄いとマスク開口
端３０に傾斜３１がつく前に下層マスク材３は消
失してしまうために、シリコン溝４の開口端近傍
に明瞭な傾斜４１を形成するに至らない。 Therefore, in order to form the slope 41 near the opening end of the silicon groove 4, the opening end 3 of the lower layer mask material 3 must be
It is necessary that the slope 31 be added to 0. but,
If the film thickness of the lower layer mask material 3 is too thin, the lower layer mask material 3 will disappear before the slope 31 is formed at the mask opening end 30. Therefore, it is difficult to form a clear slope 41 near the opening end of the silicon groove 4. Not enough.
なお、下層マスク材３の傾斜３１の下端が、シ
リコン基板１面に達し、シリコン溝４の側壁に傾
斜４１がつき始める時間は、下層マスク材３の膜
厚が初期膜厚の1/2に膜減りする時間とほぼ一致
することをSiO2膜を用いた実験により確認した。
したがつて、シリコン基板１表面と傾斜４１の下
端との距離ｌ、すなわち、シリコン溝４の開口端
近傍の広がり具合は下層マスク材３の膜厚を変え
ることにより制御することができる。 The lower end of the slope 31 of the lower mask material 3 reaches the surface of the silicon substrate and the slope 41 begins to form on the side wall of the silicon groove 4 when the film thickness of the lower mask material 3 becomes 1/2 of the initial film thickness. It was confirmed through an experiment using a SiO 2 film that this time almost coincides with the time for film thinning.
Therefore, the distance l between the surface of the silicon substrate 1 and the lower end of the slope 41, that is, the degree of expansion of the silicon groove 4 near the opening end, can be controlled by changing the thickness of the lower mask material 3.
上記の工程を経たシリコン基板１の表面には膜
減りした下層マスク材３が残つており、これをフ
ツ化アルミニウムにフツ酸を混合した液を用いた
ウエツトエツチングにより除去すると、第１図Ｆ
に示すような開口端近傍の側壁に上に向つて広が
る傾斜４１を有し、その下部の側壁の断面形状が
ほぼ矩形のシリコン溝４を形成することができ
る。 After the above process, the lower layer mask material 3 remains on the surface of the silicon substrate 1, and this is removed by wet etching using a mixture of aluminum fluoride and fluoric acid, as shown in Fig. 1F.
It is possible to form a silicon groove 4 having an upwardly widening slope 41 on the side wall near the opening end and having a substantially rectangular cross section of the lower side wall as shown in FIG.
以上述べたように、本実施例では、上層マスク
材２と下層マスク材３で構成されるマスクを用
い、上層マスク材２による第１のエツチング過程
で主要なシリコン溝４の深さと形状を制御し、さ
らに、エツチングを継続して、下層マスク材３に
よる第２のエツチング過程でシリコン溝４の開口
端近傍の側壁に傾斜４１を形成するものである。 As described above, in this embodiment, a mask composed of the upper layer mask material 2 and the lower layer mask material 3 is used, and the depth and shape of the main silicon grooves 4 are controlled in the first etching process using the upper layer mask material 2. Then, etching is continued to form a slope 41 on the side wall near the opening end of the silicon groove 4 in a second etching process using the lower mask material 3.
また、反応ガスにCBrF3を使用する場合、イオ
ン照射による影響が強い、すなわち単位面積当り
に照射されるイオンの数の多いシリコン基板１平
面では、イオンアシステツドエツチングによりシ
リコンがエツチングされるが、イオン照射による
影響が弱いシリコン溝４の側壁では、プラズマ重
合反応を起し易いのでプラズマ重合膜が生成さ
れ、これがシリコン溝４のアンダカツトを防止す
る。したがつて、第１のエツチング過程及び第２
のエツチング過程の前半においては、シリコン溝
４側壁におけるこのアンダカツトを防止する膜の
効果により、望ましい、ほぼ垂直形状のシリコン
溝４を形成することができる。しかし、第２のエ
ツチング過程の後半、すなわち、シリコン溝４の
側壁に傾斜４１を形成する工程においては、傾斜
４１面におけるエツチングとプラズマ重合物の生
成との共合により、シリコン表面が荒れてしまう
ことがしばしば起きる。このような傾斜４１にお
ける荒れを防止するためにCBrF3いO2を添加し、
プラズマ重合反応を制御することによりシリコン
表面を平滑に保つことができる。 Furthermore, when CBrF 3 is used as the reaction gas, silicon is etched by ion-assisted etching on one plane of the silicon substrate where the influence of ion irradiation is strong, that is, the number of ions irradiated per unit area is large. On the side walls of the silicon groove 4, which are weakly affected by ion irradiation, a plasma polymerization reaction is likely to occur, so a plasma polymerized film is formed, which prevents the silicon groove 4 from undercutting. Therefore, the first etching process and the second etching process
In the first half of the etching process, the desired substantially vertical shape of the silicon groove 4 can be formed due to the effect of the film that prevents undercutting on the side walls of the silicon groove 4. However, in the second half of the second etching process, that is, in the step of forming the slope 41 on the side wall of the silicon groove 4, the silicon surface becomes rough due to the combination of the etching on the slope 41 and the generation of plasma polymer. It happens often. In order to prevent such roughness on the slope 41, CBrF 3 and O 2 are added,
By controlling the plasma polymerization reaction, the silicon surface can be kept smooth.
以上説明したように、深いシリコン溝の加工形
状が、開口端近傍の側壁に上に向かつて広がる傾
斜を有し、その下部の溝の断面形状をほぼ矩形に
形成することができるので、溝に充填する物質、
例えば多結晶シリコンあるいはCVDシリコン酸
化膜などを溝内部まで容易に且つ均質に充填する
ことができる。したがつて、安定した素子分離特
性が得られ、半導体装置の歩留りと信頼性の向上
を図ることができる。また、この方法を溝キヤパ
シタ形成工程に適用すれば、溝側壁の開口端近傍
がテーパ状に形成されるので、電界の集中が大き
い開口端での耐圧劣化を抑制し、絶縁耐圧の向上
に寄与する。
As explained above, the processed shape of a deep silicon groove has a slope that widens upward on the side wall near the opening end, and the cross-sectional shape of the groove at the bottom can be formed to be approximately rectangular. filling substance,
For example, polycrystalline silicon or a CVD silicon oxide film can be easily and uniformly filled into the trench. Therefore, stable element isolation characteristics can be obtained, and the yield and reliability of semiconductor devices can be improved. Additionally, if this method is applied to the trench capacitor formation process, the trench sidewalls are formed in a tapered shape near the opening end, which suppresses breakdown voltage deterioration at the opening end where electric field concentration is large, contributing to improvement of dielectric strength voltage. do.
第１図Ａ〜Ｆは、それぞれ本発明の実施例を示
す工程断面図である。
１……シリコン基板、２……上層マスク材、３
……下層マスク材、４……溝、３１……下層マス
ク材の開口端に形成される傾斜、４１……シリコ
ン溝開口端近傍に形成される傾斜。
FIGS. 1A to 1F are process cross-sectional views showing embodiments of the present invention, respectively. 1...Silicon substrate, 2...Upper layer mask material, 3
... lower layer mask material, 4 ... groove, 31 ... slope formed at the opening end of the lower layer mask material, 41 ... slope formed near the opening end of the silicon groove.
Claims (1)
ツチング中にマスク開口端で上に向かつて広がる
傾斜が得られる酸化シリコン材料でできた下層マ
スク材とからなるマスクパターンを形成する工程
と、上記基板を反応性イオンエツチング法により
上記上層マスク材をマスクとして該上層マスク材
がなくなるまでエツチングし、上記基板に断面形
状がほぼ矩形の溝を形成する工程と、上記基板を
反応性イオンエツチング法により上記下層マスク
材をマスクとして該下層マスク材の膜厚が初期膜
厚のほぼ1/2より小さくなるまでエツチングし、
上記溝の開口端近傍の側壁に上に向かつて広がる
傾斜をつける工程とを具備することを特徴とする
半導体装置の製造方法。 ２ 上記上層マスク材が金属からなることを特徴
とする特許請求の範囲第１項記載の半導体装置の
製造方法。 ３ 上記反応性イオンエツチング法に用いるエツ
チングガスがCBrF3もしくはCBrF3とO2との混
合ガスであることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。[Scope of Claims] 1. A mask pattern consisting of an upper layer mask material and a lower layer mask material made of a silicon oxide material is provided on a substrate, and a slope that widens upward at the opening end of the mask is obtained during the following etching of the substrate. etching the substrate using a reactive ion etching method using the upper layer mask material as a mask until the upper layer mask material is removed, forming a groove having a substantially rectangular cross section in the substrate; Etching the lower layer mask material using a reactive ion etching method as a mask until the film thickness of the lower layer mask material becomes less than approximately 1/2 of the initial film thickness,
A method of manufacturing a semiconductor device, comprising the step of: forming an upwardly widening slope on a side wall near an opening end of the groove. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the upper layer mask material is made of metal. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas used in the reactive ion etching method is CBrF 3 or a mixed gas of CBrF 3 and O 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16285A JPS61159737A (en) | 1985-01-07 | 1985-01-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16285A JPS61159737A (en) | 1985-01-07 | 1985-01-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61159737A JPS61159737A (en) | 1986-07-19 |
| JPH0571129B2 true JPH0571129B2 (en) | 1993-10-06 |
Family
ID=11466340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16285A Granted JPS61159737A (en) | 1985-01-07 | 1985-01-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61159737A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4361620A1 (en) | 2022-10-28 | 2024-05-01 | ARKRAY, Inc. | Method for analyzing sample comprising hemoglobin a2 by capillary electrophoresis |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0407077A3 (en) * | 1989-07-03 | 1992-12-30 | American Telephone And Telegraph Company | Trench etching in an integrated-circuit semiconductor device |
| JPH07326659A (en) | 1994-06-02 | 1995-12-12 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JP7328276B2 (en) | 2021-05-27 | 2023-08-16 | 京セラ株式会社 | Nonreciprocal waveguide, isolator, optical switch, optical transceiver, data center, and manufacturing method |
-
1985
- 1985-01-07 JP JP16285A patent/JPS61159737A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4361620A1 (en) | 2022-10-28 | 2024-05-01 | ARKRAY, Inc. | Method for analyzing sample comprising hemoglobin a2 by capillary electrophoresis |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61159737A (en) | 1986-07-19 |
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