JPH0566922A - Decimal arithmetic circuit - Google Patents

Abstract

PURPOSE:To increase the speed of a decimal arithmetic instruction by performing automatically the pre-matching of digits of the decimal arithmetic data, the decimal computing operation, and the transformation of the computing result into eight bits within a decimal arithmetic circuit. CONSTITUTION:When the computed data on a decimal arithmetic instruction is not matched with the lowest order digit position of the computing data, the computed data outputted from a selector 1 are inputted as they are to the decimal ALU (arithmetic logic computing part) 4 and 5. However the computing data outputted from a selector 2 are switched between the higher and lower order digits and then inputted to the ALU 4 and 5. If the valid digit of the computed data is set in a lower order, the ALU 5 performs the decimal arithmetic and holds this computing result in a register 6. If the valid digit of the computed data is set in a higher order, the ALU 5 just transmits a carry 38 and the ALU 4 carries out the decimal arithmetic. Then the outputs of the ALU 4 and 6 are added together and outputted as the 8-bit computing result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal arithmetic circuit,
In particular, the present invention relates to a decimal arithmetic circuit for automatically performing a mixed operation of decimal data starting from upper 4 bits of 8-bit data and decimal data starting from lower 4 bits of 8-bit data.

[0002]

2. Description of the Related Art Conventionally, a decimal arithmetic circuit of this kind performs digit alignment of data to be operated and arithmetic data in advance, and thereafter inputs arithmetic data for executing decimal arithmetic,
Align with the position of the upper 4 bits or lower 4 bits in the byte address where the least significant digit of the operand data exists 4
A shift circuit capable of shifting bit by bit and a local memory for temporarily storing the result are provided, and operation data is read from the local memory and 1 is set between the operation data and the operation data.
It was a circuit that performed 0-ary operation. In addition, the general-purpose register that directly reads out the operation data that has been digitized by the shift circuit without providing a local memory, and writes it back to the same address position or another address position of the main memory as the operation data and re-reads it as the operation data. It was a circuit for performing a decimal operation.

[0003]

The above-described conventional decimal arithmetic circuit adjusts the least significant digit of the operand data and the arithmetic data to the same position in the byte data before performing the decimal arithmetic operation. After performing digit alignment according to the instructions of the firmware or software and temporarily storing the result in the local memory or main memory,
It was necessary to perform a radix operation. Therefore, there are drawbacks in that the performance of the decimal operation as a whole decreases due to the digit alignment and the temporary storage, the number of circuits of the digit alignment circuit and the memory for the temporary storage increases, and the load of firmware or software increases.

[0004]

According to the decimal arithmetic circuit of the present invention, decimal data and lower 4 bits starting from upper 4 bits of 8-bit data in which 4 bits are 1 digit and the least significant digit is divided for each byte address. In a decimal arithmetic device for performing arithmetic operation by combining the decimal data starting from 8 as the operand data or the operand data, the first selector means for dividing the operand data every 8 bits and outputting it, and the operand data 8 Second selection means for dividing and outputting for each bit;
Third selection means for exchanging the upper 4 bits and the lower 4 bits of the output of the second selection means, and an 8-bit type capable of performing decimal addition / subtraction and logical operation and changing the operation mode for every 4 bits Decimal ALU and the decimal ALU
A register for holding the output of the lower 4 bits of
A fourth selecting means for switching and outputting the lower 4 bits of the base ALU and the value of the register, and data information indicating the data digit number of the operated data and the arithmetic data and the position of the least significant digit are input. Control means for selecting and setting the operation mode of the decimal ALU, upper 4 bits of the decimal ALU, and a control circuit for outputting a valid instruction of the operation result output from the fourth selecting means are configured. ..

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 is a selector for dividing the data to be calculated into 8-bit data and outputting the same.
A selector that divides and outputs each bit, 3 is a selector that switches the upper 4 bits and lower 4 bits of the output of the selector 2, 4 and 5 are 4-bit decimal ALUs (arithmetic logic operation unit), and 6 is a decimal ALU 5. , A selector for holding the output of 7 and a selector for switching the output of the decimal ALU 5 and the output of the register 6 to output the lower 4 bits of the operation result,
8 is a control circuit for generating control signals for each selector and each decimal ALU, 10 is data to be operated, 11 is operation data,
Reference numerals 12 and 13 are calculation results, 20 is data information of the calculation target data and the calculation data, 21 is a control signal of each selector, 2
2 is an operation mode signal of the decimal ALUs 4 and 5, 23 is an output enable instruction signal indicating that the operation results 12 and 13 are valid data, 30 and 31 are output signals of the selector 1, 32 and 33 are of the selector 2. Output signal, 34 and 3
Reference numeral 5 is an output signal of the selector 3, 36 is an output signal of the decimal ALU 5, 37 is an output signal of the register 6, and 38 and 39 are carry signals of the decimal ALUs 5 and 4.

There are four combinations of the positions of the least significant digits of the operand data and the arithmetic data input to the decimal arithmetic circuit shown in FIG. The operation will be described for each case.

First, when the least significant digit is in the least significant 4 bits of both the operated data and the operational data, the control circuit 8 instructs the following operation by decoding the data information 20 indicating the position of the least significant digit. The selector 3 outputs the output of the selector 2 as it is, the decimal ALUs 4 and 5 perform decimal operation, and the selector 7 outputs the output 36 of the decimal ALU 5 as it is. Then, the 2-digit decimal operation result is output from the data lines 12 and 13 together with the output validity instruction signal 23. At the same time, the control circuit 8 instructs the selector 1 and the selector 2 to output the next input data. Decimal operation is performed by this repetition.

Secondly, when the least significant digit of both the operated data and the operated data is in the upper 4 bits, the control circuit 8 instructs the following operation by decoding the data information 20. The selector 3 outputs the output of the selector 2 as it is, and the decimal A
LU4 performs a decimal operation, decimal AUL5 does not perform a decimal operation, and becomes an operation mode in which the input carry signal is directly output as the carry signal 38, and the selector outputs the output 37 of the register 6. Then, together with the output validity instruction signal 23, a valid decimal operation result of the upper 4 bits and 1 digit is output from the data line 12. An undefined value is output from the data line 13. At the same time, the control circuit 8 instructs the selector 1 and the selector 2 to output the next input data. From the next, valid data will come from the lower 4 bits, so decimal ALU 4/5 as in the first case
Then, the selector 7 outputs the output 36 of the decimal ALU 5 as it is, so that the 2-digit decimal operation result is output from the data lines 12 and 13 together with the output valid instruction. Decimal operation is performed by this repetition.

Thirdly, when the least significant digit of the operated data is in the lower 4 bits and the least significant digit of the operated data is in the upper 4 bits, the control circuit 8 decodes the data information 20 to instruct the following operation. .. The selector 3 exchanges the upper 4 bits and the lower 4 bits of the output of the selector 2, and the lower 4 bits of the output signal 35 is replaced by the upper output signal 3 of the selector 2.
2 is output and only decimal ALU5 performs decimal operation,
Decimal ALU4 does not perform decimal arithmetic and carries carry signal 38
As a result, the carry mode 38 is output as it is, and the register 6 stores the output 37 of the decimal ALU 5. That is, the decimal operation result of the lower 4 bits 1 digit of the operation data and the upper 4 bits 1 digit of the operation data is stored in the register 6 as the lower 4 bits 1 digit. At this time, the output valid instruction signal 23 is not output and the data lines 12 and 13 are not output.
Is inactive. Then, the control circuit 8 instructs the selector 2 to output the next input data. However, since the uncalculated data remains in the upper 4 bits of the output of the selector 1, the output of the selector 1 is not changed.

Next, the control circuit 8 directs the following operation in order to perform the remaining processing. The selector 3 exchanges the upper 4 bits and the lower 4 bits of the output of the selector 2, and the lower 4 output signal 33 of the selector 2 becomes the upper 4 bit output signal 34.
Is output and decimal operation is performed only for decimal ALU4, and 1
The 0-ary ALU 5 is in an arithmetic mode in which the carry signal 38 is not output in decimal and the input carry of the decimal ALU 5 is output as it is, and the selector 7 outputs the output 37 of the register 6. Then, together with the output valid instructing signal 23, the operation result of the lower 4 bits and 1 digit stored in the register 6 last time and the operation result of the remaining upper 4 bits and 1 digit of this time are combined to obtain the data as the operation result of 8 bits and 2 digits. Lines 12 and 1
It is output from 3. At the same time, the control circuit 8 instructs the selector 1 to output the next input data. However, since the uncalculated data remains in the upper 4 bits of the output of the selector 2, the output of the selector 2 is not changed.

In the third case, the decimal operation is performed by repeating the above two operations.

Finally, when the least significant digit of the operated data is in the upper 4 bits and the least significant digit of the operated data is in the lower 4 bits, the control circuit 8 instructs the following operations by decoding the data information 20.

The selector 3 exchanges the upper 4 bits and the lower 4 bits of the output of the selector 2 and outputs the lower 4 output signal 33 of the selector 2 to the upper 4 bit output signal 34.
The decimal ALU 4 performs a decimal operation, and the decimal ALU 5 does not perform a decimal operation and the input carry signal is output as the carry signal 38 as it is, and the selector 7 outputs the output 37 of the register 6. Then, together with the output validity instruction signal 23, the valid upper 4 bits 1
The 0-ary operation result is output from the data line 12. An undefined value is output from the data line 13. Control circuit 8 at the same time
Instructs the selector 1 to output the next input data. However, since the uncalculated data remains in the upper 4 bits of the output of the selector 2, the output of the selector 2 is not changed. At this point, the digit of the operated data to be processed next is in the lower 4 bits, and the digit of the operated data is in the upper 4 bits, so that the subsequent processing is performed by repeating the same processing as in the third case.

[0016]

As described above, according to the present invention, by automatically performing the pre-digit alignment of the decimal data input in the decimal arithmetic circuit, the decimal operation, and the conversion of the operation result into 8 bits, Decimal data whose lower digit starts from the upper 4 bits of 8-bit data and 1 that starts from the lower 4 bits
This has the effects of accelerating the speed of mixed operation with 0-ary data and reducing the load on software or firmware that executes decimal operation instructions.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

 1-3 Selector 4-5 Decimal ALU 6 Register 7 Selector 8 Control circuit 10 Operated data 11 Operation data 12-13 Operation result 20 Data information 21-22 Control signal 23 Output valid instruction signal 30-37 Data line 38-39 Carry signal

Claims (1)

[Claims] 1. Decimal data starting from the upper 4 bits of 8-bit data and 1 starting from the lower 4 bits of the 8-bit data in which the least significant digit is delimited for each byte address with 4 bits as one digit.
In a decimal arithmetic unit for performing arithmetic operation by combining 0-ary data as operated data or operation data, first selecting means for outputting the operated data by dividing it into 8-bit units, and the operation data in 8-bit units Second select means for dividing and outputting to the third select means, third select means for exchanging the upper 4 bits and the lower 4 bits of the output of the second select means, decimal addition / subtraction and logical operation 8-bit decimal AL whose operation mode can be changed in 4-bit units
U, a register for holding the output of the lower 4 bits of the decimal ALU, and fourth selecting means for switching and outputting the values of the lower 4 bits of the decimal ALU and the register,
Data information indicating the number of data digits and the position of the least significant digit of the operation data and the operation data is input to control the selection means, set the operation mode of the decimal ALU, and set the upper 4 bits of the decimal ALU. A decimal arithmetic circuit comprising: a control circuit that outputs a valid instruction of the arithmetic result output from the fourth selecting means.