JPH0562360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides two memories, such as a pitch control device, which are used to change the pitch of musical notes by writing at a constant speed and reading at different speeds.
The present invention relates to a clock generation circuit used for accessing two frequencies at different timings.

FIG. 1 shows an embodiment of the present invention, which will be explained based on this and a timing chart shown in FIG.

Figure 1 shows the configuration of the write clock to RAM1.
Although this is an example of supplying the access timing to RAM1 when OSC1 and read clock OSC2 are different, both clocks may have the same frequency.

In the figure, clocks for reading, writing, and control are output from the clock generating circuit CL, and the reading and writing clocks are inputted to address counters CT1 and CT2, respectively, and output a read address and a write address. Each address is supplied to a multiplexer MPX, and its output is selectively controlled by control clocks A/B. In the cycle for writing data into RAM1, the input signal is digitally converted by A/D converter 3 and sent to RAM1 through three-state buffer 2. At this time, buffer 2 and RAM1 are enabled for writing by control signals C and R/W, and multiplexer MPX is also switched to the write address side of address counter CT1. With this write address
Data is written to RAM1.

On the other hand, in the read cycle, the multiplexer MPX switches to the read address side of the counter CT2, putting RAM1 in the read state.
Data corresponding to the read address of RAM1 is sent and latched into latch 6.

Next, the clock generation circuit CL will be explained.
OSC1 is the write clock, OSC2 is the read clock, and OSC3 uses the frequency divider DV
The frequency is divided into 1/N by . This divided output is
The frequency is more than twice that of OSC1 and OSC2.

OSC1 and OSC2 sometimes have edges at the same time as shown in Figure 2 b and c. To avoid this, the outputs of OSC1 and OSC2 are connected to D latches D1 and D.
Enter 2. If the clocks of the D latches D1 and D2 are the outputs of the frequency divider DV (Fig. 2 a), outputs with the timing of the outputs Q of the D latches D1 and D2 are obtained as shown in Fig. 2 d and e, and the edge is You can avoid them happening at the same time. Each Q output is a clock for address counters CT1 and CT2.

Next, the outputs of D latches D1 and D2 are respectively edge trigger type RS-flip-flop RS-
It is input to the set S and reset R of the FF, and its output Q is as shown in FIG. 2 f and g. This output Q,
AND the outputs of latches D1 and D2, respectively.
Input to 1 and AND2. The output of AND1 is the second
As shown in Figure h, at this time, the output Q of latch D1
The rising edge of latch D2 becomes "H" of AND1, and the rising edge of latch D2 becomes "L" of AND1. The output of this AND1 becomes a switching signal for multiplexer MPX. As a result, address counter CT1
is the write address of RAM1, and the address counter CT2 is the read address, allowing enough time to cope with the delay time of each gate.

Also, the output of AND1 is used as the write/read control signal R/W of RAM1 to latches D3, D4,
D5 and the Q output of latch D4 (second
k) and the Q output of latch D5 (Fig. 2 l).
By inputting the signal to NAND1, an R/W signal as shown in FIG. 2m is obtained as an output. In this embodiment, it is assumed that in the RAM 1, writing is performed when R/W is "L", and reading is performed when R/W is "H".

Also, by delaying the output of AND2 (n in Figure 2) using a delay circuit DL such as a latch,
If the clock is used for the latch D6 for outputting read data as shown in FIG. Furthermore, R/W and three-state buffer 2 (active when the clock is “L”, high impedance when the clock is “H”).
By setting the two clocks at the same time, writing can be performed and malfunctions can be prevented.

Furthermore, if a latch is further added to the output of latch D6 and the clock of this latch is used for the signal of OSC2, it is also possible to obtain data of a constant period.

As described above, according to the present invention, the rise timings of the two oscillators are timely shifted, and each gate circuit performs appropriate delay and waveform shaping, making it possible to cope with delay times caused by RAM, counters, etc. This can prevent malfunctions.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a timing chart of each part of FIG. 1. CL...Clock generation circuit, 1...RAM, RS
-FF...RS-flip-flop, MPX...multiplexer, CT1, CT2...address counter, DL...delay circuit.

Claims (1)

[Claims] 1. First and second oscillators (OSC1 and OSC2) that output clocks with different frequencies
, a latch circuit (D1 and D2) that latches the output of each oscillator (OSC1 and OSC2), and an edge trigger type that performs set and reset using the output of each latch circuit (D1 and D2).
RS-flip-flop (RS-FF), the output of the rat circuit (D1 and D2) and RS
- first and second AND circuits (AND1 and AND2) that take respective ANDs with the output of the flip-flop (RS-FF), and first and second AND circuits that delay the output of each AND circuit (AND1 and AND2) by a predetermined time, respectively; A clock generation circuit comprising: second delay means (D3, D4, D5 and DL).