JPH0561069A - Matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the capacity of a crossing part and to prevent the reduction of a speed at the rise time of a source signal, or a gate signal by making a wiring width in the crossing part of a gate wiring and a source wiring narrower than parts except the crossing part. CONSTITUTION:As to the matrix type liquid crystal display device provided with plural transistors, the source wiring 5 and the gate wiring 3, the width of the gate wiring 3 in the crossing part of the gate wiring 3 and the source wiring 5 is made narrower than the other parts, that means, it is made 1/N (N>1), and the length of it is made Lg times of the length of one pitch of the gate wiring 3. And also, the width of the source wiring 5 is made narrower than the other parts, that means, it is made 1/M (M>1), the length of it is made Ls times of the length of one pitch of the source wiring 5. Thus, the capacity of the crossing part becomes 1/NM. Meanwhile, the rate of increasing the resistance of the gate wiring 3 and the source wiring 5 becomes Lg(N-1) and Ls(M-1) respectively, so that the increase of the wiring resistance can be almost disregarded in comparison with the capacity of the crossing part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device, and more particularly to its wiring shape.

[0002]

2. Description of the Related Art FIG. 2 is a plan view of a conventional matrix type liquid crystal display device disclosed in, for example, Japanese Patent Laid-Open Nos. 2-44318 and 1-281434. In the figure,
1 is a transparent insulating substrate, 2 is a pixel electrode, generally ITO
Is used. Reference numeral 3 is a gate wiring, 4 is a semiconductor layer, and a gate insulating film is formed thereunder. Reference numeral 5 is a source wiring and 6 is a drain electrode. The portions indicated by reference numerals 2 to 6 are formed on the transparent insulating substrate 1.

Next, the operation will be described. When a gate signal voltage is applied to the gate wiring 3, carriers are induced in the semiconductor layer 4 and the thin film transistor is turned on.
When no voltage is applied to the gate wiring 3, the gate wiring 3 is turned off. In the ON state, the source signal voltage is directly applied to the drain electrode 6. Actually, the transistors having such a configuration are arranged in a matrix in the direction of the gate wiring 3 and the source wiring 5. Therefore, the gate voltage and the source voltage applied to each transistor rise with a time constant determined by the resistance and wiring capacitance of each wiring.

[0004]

The conventional liquid crystal display device having the inverted stagger type thin film transistor is constructed as described above, and the capacitance between the source wiring 5 and the gate wiring 3 is not considered at all. Therefore, there is a problem in that the rising speed of the source signal or the gate signal is reduced due to this capacitance and the resistance of the source wiring 5 and the resistance of the gate wiring 3, and this capacitance has a problem. There was a capacity in the part, that is, a cross capacity.

The present invention has been made in order to solve the above problems, and reduces the capacitance at the intersection of the source wiring and the gate wiring to prevent the rise rate of the source signal or the gate signal from decreasing. It is an object of the present invention to obtain a matrix type liquid crystal display device which can be manufactured.

[0006]

In the matrix type liquid crystal display device according to the present invention, the width of at least one of the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring is made narrower than the portion other than the intersection. is there.

[0007]

According to the present invention, since the width of at least one of the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring is narrower than the portion other than the intersection, the capacitance at the intersection is significantly reduced and the wiring resistance of one wiring is reduced. The amount of increase is small, and the rising speeds of the gate signal and the source signal do not decrease.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a matrix type liquid crystal display device according to this embodiment, and the portions indicated by reference numerals 1 to 6 are the same as those in the prior art. Reference numeral 7 indicates that the width of the gate wiring 3 at the intersection of the gate wiring 3 and the source wiring 5 is smaller than that of the other portions, that is, 1 / N
(N> 1), and its length is the gate wiring 3
It is L _g times the length of 1 pitch. Similarly, 8 is the source wiring 5 at the intersection of the gate wiring 3 and the source wiring 5.
Is smaller than the other portions, that is, 1 / M (M> 1), and its length is L _s times the length of one pitch of the source wiring 5.

In the above structure, at the intersection of the gate wiring 3 and the source wiring 5, the wiring width of each is 1 / th of that of the other portion.
Since it is set to N and 1 / M, the capacitance at the intersection is 1 compared to the conventional one.
/ NM, which can be significantly reduced. On the other hand, the ratio of the lengths of the thinned portions 7 and 8 to the length of one pitch of the gate wiring 3 and the source wiring 5 is L _g and L _s , respectively, and the rate of increase in resistance of the gate wiring 3 and the source wiring 5 Are L _g (N-1) and L _s (M-1), respectively.
Since L _g and L _s are usually small values of about 1/10,
The increase in wiring resistance is almost negligible compared to the capacitance at the intersection. As a result, it is possible to prevent the rising speeds of the gate signal and the source signal from decreasing.

Although the thin portions 7 and 8 are provided on both the gate wiring 3 and the source wiring 5 in the above embodiment, the same operation and effect can be obtained even if they are provided on either one.

[0011]

As described above, according to the present invention, the capacitance at the intersection can be significantly reduced, and the increase in wiring resistance can be almost ignored as compared with the reduction in the capacitance at the intersection. Alternatively, it is possible to prevent the rise rate of the source signal from decreasing.

[Brief description of drawings]

FIG. 1 is a plan view of a matrix type liquid crystal display device according to the present invention.

FIG. 2 is a plan view of a conventional matrix type liquid crystal display device.

[Explanation of symbols]

 1 Transparent Insulating Substrate 3 Gate Wiring 4 Semiconductor Layer 5 Source Wiring 6 Drain Electrode 7 Gate Wiring Narrow Width 8 Source Wiring Narrow Width

Claims (1)

[Claims] 1. In a matrix type liquid crystal display device having a plurality of transistors, a source wiring and a gate wiring, the width of at least one of the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring is made narrower than the portion other than the intersection. A matrix type liquid crystal display device characterized by the above.