JPH0561812A - Information processing system - Google Patents

Abstract

PURPOSE:To realize an interruption system which can avoid the increase of the number of signal lines and the performance deterioration of the system. CONSTITUTION:Plural processor parts 1-N inputting/outputting an interruption signal with the other processors, an interruption signal-only bus 30 for transmitting the interruption signal and a bus mediation means 400 mediating the bus 30 are provided. Thus, the number of the signal lines does not increase since the system consists of bus connection constitution. Since a data bus is not used, the performance of the system is not deteriorated even if the frequency of interruption occurrence becomes high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to a system having a large number of processor units and interrupting the processor units.

[0002]

2. Description of the Related Art Conventionally, there are roughly two types of interrupt methods in this type of information processing system. The first method is to connect the interrupt signals of each processor in a star pattern. As one example, there are three processors, and the configuration when the interrupt lines are mutually connected is shown in FIG. In this system, each processor inputs an interrupt signal from all the other processors and outputs an interrupt signal to all the other processors. Receiving the interrupt signal, each of the processors 100 to 300 temporarily holds the signal as a pulse signal in an internal flip-flop (not shown), and resets the FF when the interrupt occurs. To do.

In the second method, a plurality of data buses to which each processor is connected and a plurality of interrupt holding FFs connected to the data bus are provided, and the output of each FF is one of the interrupt terminals of one of the processors. It is a method of connecting to one. As an example thereof, FIG. 6 shows a configuration in which three processors are provided and interrupt lines are mutually connected. Each FF is selected by an address bus (not shown) attached to the data bus, and an interrupt is generated by writing "1" in the FF of the interrupt destination. The processor receiving the interrupt writes "0" in the corresponding FF via the data bus.
In the figure, one processor out of the processors 100 to 300 is provided with two FFs in order to separate interrupts from the other two processors. When using the data bus, each processor needs to send a bus use request to the bus arbitration unit 400 and receive a use permission.

The above-mentioned conventional interrupt method has the following drawbacks.

First, the first interrupt method has a drawback that the number of interrupt signal lines increases significantly as the number of processors increases, which makes it difficult to perform pattern wiring on a printed circuit board. For example, if the number of processors is N
If the number is 1, the number of interrupt signal lines is N × (N−1). In addition, there is a drawback that a pin for sending an interrupt to the processor is required, and when the processor is an LSI, there is a shortage of pins because the total number of pins is limited.

Next, in the second interrupt method, since the data bus is used to generate an interrupt, when the number of processors increases and the frequency of interrupt occurrence increases, the free time of the data bus decreases, and the data of other processors is reduced. There is a drawback in that the access to the input / output control unit and the memory unit on the bus is kept waiting and the performance of the processor and the performance of the entire processing unit are degraded.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to adopt an interrupt system which does not cause problems in wiring or performance deterioration due to increase in data bus usage time. It is to provide the information processing system.

[0008]

An information processing system according to the present invention comprises a plurality of processor units for inputting / outputting interrupt signals to / from other processors, an exclusive bus for interrupt signals for transmitting the interrupt signals, and this bus. And a bus arbitration unit that performs arbitration.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of an information processing system according to the present invention. In this system, a bus 30 dedicated to transmitting an interrupt signal is provided, and a bus arbitration unit 400 for arbitrating the bus 30 is further provided.
The feature is that is provided. That is, the interrupt signal is not transmitted using the data bus, but is transmitted using the bus 30 dedicated to the interrupt signal.

In the figure, the system of this example is configured to include processor units 1, 2, ..., N and a bus arbitration unit 400. The internal configuration of each processor unit is assumed to be the same. Each processor unit 1 to the interrupt bus 30
It is connected to the microprocessor in N. The interrupt bus arbitration unit 400 is connected to the microprocessor in each processor unit by bus use request signal lines 12-1, 12-2, ..., 12-n and bus use permission signal lines 13-1, ..., 13-n. There is. In addition to the microprocessor, each processor unit is also configured to include interrupt acceptance FFs 11, 12, and 1M (M = N-1). Each interrupt acceptance FF can be written via the interrupt bus, and the output signal line is connected to each interrupt pin of the microprocessor.

Next, the operation of the system of this example having such a configuration will be described in detail. Here, a case where the processor unit 2 interrupts the processor unit 1 will be described.

First, the microprocessor in the processor unit 2 causes the interrupt bus arbitration unit 400 to use the bus use request signal line 12
Request use of interrupt bus 30 via -2. The interrupt bus arbitration unit 400 arbitrates the bus use request sent from each microprocessor. When the microprocessor 100 in the processor unit 2 receives the use permission from the interrupt bus arbitration unit 400 via the bus use permission signal line 13-2, the interrupt acceptance FF in the processor unit 1 via the interrupt bus 3
Write “1” in 11. It is assumed that all the interrupt FFs are assigned individual addresses. here,
The interrupt accepting FFs 11 to 1M in the processor unit 1 are used by the processor units 2 to N to cause interrupts. Similarly, the interrupt accepting FFs (not shown) in the processor unit 2 are also used by the processor units other than the own processor unit to interrupt. Of course, one more interrupt reception FF
If one is provided, it is possible to cause an interrupt to the own microprocessor.

The output of the interrupt acceptance FF 11 is connected to the interrupt pin of the microprocessor 100, and accepts the interrupt if the microprocessor 11 is in the interrupt acceptable state. Interrupted microprocessor 100
The micro program of "1" writes "0" in the interrupt acceptance FF 11 via the interrupt bus 30. Of course, the bus request signal line 12-1 and the bus use permission signal line 13-1 must be operated as already described.

In the above example, the microprocessor 10
Although the interrupt acceptance FFs 11 to 1M are provided outside 0, there is no problem even if they are provided inside the microprocessor 100. Of course, the same applies to microprocessors in other processor units. Also, the above description has been made assuming that each microprocessor has a dedicated interrupt bus connection pin.

Next, a configuration example in which each microprocessor has only a data bus connection pin will be described.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the information processing system according to the present invention. The system of this example includes processor units 1 to N,
The following is a detailed description focusing on the processor unit 1. The microprocessor 100 in the processor unit 1 is connected to the data bus 40 via a bidirectional buffer 101. Similarly, microprocessor 100 is connected to interrupt bus 30 via bidirectional buffer 102. The interrupt accepting FFs 11 to 1M are directly connected to the interrupt bus 30 as in the first embodiment described above. Interrupt bus use request signal line 12-1 and interrupt bus use permission signal line 13-1
Is connected to the interrupt bus arbitration unit 400.

When the microprocessor 100 accesses an external register, memory or the like (not shown), the address decoder 103 monitors the output address, determines whether it is addressed to the data bus or the interrupt bus, and outputs a decoding result signal. It outputs to the line and selectively activates the AND circuits 105 and 106 to output the bus use request from the micro.

The switch 104 includes a signal line of a decoding result of the address decoder 103 and a data bus arbitration unit (not shown).
Data bus enable signal line returned from the interrupt bus arbitration signal line 1 returned from the interrupt bus arbitration unit 2
3-1 is connected.

The two bidirectional buffers 101 and 102 are enabled in the directions instructed by the microprocessor 100 only when the data bus use permission signal and the interrupt bus use permission signal are received, respectively. In other cases, the impedance becomes high in both directions.

Next, the operation of the system of this example having such a configuration will be described in detail.

When the microprocessor 100 writes "1" to the interrupt acceptance FF in the other processor section 2, the address decoder 103 determines that the address output from the microprocessor 100 is addressed to the interrupt bus 3. The bus use request signal output from the microprocessor 100 is transmitted to the interrupt bus use request signal line 12-1 via the integrating circuit. When the interrupt bus arbitration unit 400 sets the interrupt bus use permission signal line to “1”, the switching unit 104 receives the output signal of the address decoder 103 from the microprocessor.
Transmit bus enable signal to 100.

Thereafter, the microprocessor 100 writes "1" in the interrupt reception FF 12 in the processor section 1. Also, when the processor unit 1 writes "0" in the interrupt acceptance FF in its own processor unit, the same operation as above is performed.

Next, the processor unit 1 causes the interrupt acceptance FF
A configuration example in which an interrupt acceptance register having one control bit is provided in each processor unit instead of the above will be described. FIG. 3 is a block diagram showing the configuration of the third embodiment of the information processing system according to the present invention. In the figure, this system has the same configuration as processor units 1 to N.
However, the following description focuses on the processor unit 1. The interrupt acceptance register 14 in the processor unit 1 is connected to the interrupt bus 3, and the other bits except the control bit in the register are connected to the microprocessor 100 in the own processor unit.

Here, the interrupt acceptance register 14 has, as shown in FIG. 4, one N-bit as well as one control bit.
It is configured to include one interrupt holding bit 41 to 4 (N-1). The left side of the figure is connected to the interrupt bus 30, and the right side of the figure is connected to the microprocessor 100. As is clear from the figure, the bit for holding the control bit may not be provided.

Next, the operation of the system of the present example configured as shown in FIGS. 3 and 4 will be described in detail focusing on the part different from the first embodiment (FIG. 1) described above. In addition,
Here, the operation when the processor unit 2 interrupts the processor unit 1 will be described.

When the processor unit 2 receives permission to use the interrupt bus 30 from the interrupt bus arbitration unit 400, it outputs an address addressed to the interrupt acceptance register 14 in the processor unit 1 and outputs "1100 ... 0" as data. .. The data is held in the interrupt acceptance register 14 shown in FIG. 4 in order from the top of the drawing. In this case, since the control bit is “1”, the interrupt acceptance register 14
"1" is written only in the interrupt holding bit 41 of 1 and other bits remain unchanged.

That is, since the signal line to the control bit of the register 14 in FIG. 4 is "1" and the signal line to the interrupt holding bit 41 is "1", the output of the AND circuit 61 and the output of the OR circuit 51. Becomes "1" and interrupt hold bit 4
"1" is written in 1. At this time, the outputs of the inverters other than the inverter 71 are "1", but the AND circuit 6
Since the outputs of the AND circuits other than 1 are "0", the interrupt holding bits other than the interrupt holding bit 41 are "0".

Conversely, when the microprocessor 100 receives the interrupt, it outputs "010 ... 0" as data. In this case, "0" is written only in the interrupt holding bit 41 of the register 14, and the other bits remain unchanged.

That is, since the signal line to the control bit of the register 14 in FIG. 4 is "0" and the signal line to the interrupt holding bit 41 is "1", the outputs of the AND circuits 61 and 62 are both "0". "It becomes. Therefore, the output of the OR circuit 51 becomes "0", and "0" is written in the interrupt holding bit 41. At this time, the outputs of the inverters other than the inverter 71 are "1", but the outputs of all the AND circuits are "0".
Therefore, the interrupt holding bits other than the interrupt holding bit 41 remain "0".

The reason why the above processing is necessary is that each microprocessor uses the interrupt bus 30 twice to update the interrupt acceptance register, and there is a difference between the first time (reading) and the second time (writing). This is to prevent the microprocessor of the above from updating the same interrupt acceptance register.

Therefore, while the interrupt bus 30 is used twice, the effect is the same even if the bus is held so that another microprocessor cannot use the interrupt bus 30. In that case, after the bus arbitration unit 400 receives the bus hold signal and sends out the bus use permission signal, the interrupt arbitration unit 400 may be controlled not to perform the next bus arbitration until the bus hold signal is no longer output.

As described above, in the first to third embodiments, the bus dedicated to the interrupt signal is provided, and "1" is written in the interrupt receiving FF or the interrupt receiving register in the processor unit of the interrupt destination via this bus. Since an interrupt is generated by plugging in, the number of interrupt signal lines can be significantly reduced as compared with the conventional method described above, and the performance of the processing unit does not deteriorate because the data bus is not occupied.

[0034]

As described above, according to the present invention, by providing the dedicated bus for transmitting the interrupt signal, the number of signal lines does not increase, and the system performance does not deteriorate even if the interrupt frequency increases. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an information processing system according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an information processing system according to a third embodiment of the present invention.

4 is a block diagram showing a configuration of an interrupt acceptance register in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional information processing system.

FIG. 6 is a block diagram showing a configuration of a conventional information processing system.

[Explanation of symbols]

 1 to N processor part 30 interrupt signal dedicated bus 100 microprocessor 400 bus arbitration part

Claims (1)

[Claims] 1. A plurality of processor units for inputting / outputting an interrupt signal to / from another processor, a bus dedicated to an interrupt signal for transmitting the interrupt signal, and a bus arbitration unit for arbitrating the bus. An information processing system comprising: