JPH0561775A - Access right inspecting device - Google Patents

Abstract

PURPOSE:To easily inspect the right of access at an execution level different from the current execution level of a processor almost without changing the hardware of an address translating mechanism or the like by providing a function to inspect the right of access while switching the execution level to the arbitrary temporary execution level by a selector. CONSTITUTION:An execution level 120 to inspect the right of access extracted by decoding information to a decoder 206 concerning the access right inspection applied by a data bus 213, selection control selector 121 to select either a current execution level (PEL) 205 of the processor or the execution level 120, and selection control signal 122 to the selector 121 are added. Thus, address translation is executed by switching to the objective execution level to detect the right of access, and it is inspected whether there is a memory protect violation or not. After the right of access is inspected, the selection control signal 122 to the selector 121 is controlled so as to select the PEL 205.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory protection mechanism in virtual memory management realized by a paging or segment method, and more particularly to a method of realizing a mechanism for checking an access right to a memory area which is not actually accessed.

[0002]

2. Description of the Related Art In microprocessors and large-scale computers,
A virtual memory system is adopted which enables execution of a program even when the capacity of the memory mounted on the device is smaller than the capacity of the code of the program. In the virtual memory system, a logical address space provided by a processor, that is, an address space that can be referenced by a program is divided into unit areas called pages or segments. The program is stored in an auxiliary storage device having a sufficient capacity to store the program, and only a partial program required for execution of the processor at this time is loaded from the auxiliary storage device into the memory and executed. If the necessary partial program is not loaded in the memory, the unnecessary partial program in the memory is saved in the auxiliary storage device, and the necessary partial program is loaded from the auxiliary storage device in the memory instead.
Replacement of the partial program between the auxiliary storage device and the memory is performed in units of page or segment unit areas. Although a part of the program is loaded on the memory, the logical address (virtual address) seen from the program does not always match the actual address on the memory (real address). Which area of the memory the virtual address corresponds to is determined by the address conversion table arranged on the memory. That is, the address conversion table holds the correspondence between virtual addresses and real addresses.

In a processor employing the virtual memory system,
Since it is necessary to convert a virtual address to a real address when accessing a memory, the address conversion time from the virtual address to the real address becomes a factor that delays the instruction execution time of the processor. However, since the address translation table is arranged on the memory in the real address space, and the access of the address translation table itself is affected by the access time of the memory, high-speed address translation cannot be expected. Therefore, in a normal processor, the result of address translation is cached in the address translation buffer mechanism (hereinafter referred to as TLB) in the chip, and the virtual address to be accessed is TL.
As long as B is hit, the memory is accessed according to the real address cached in TLB, and high-speed instruction execution is realized.

The original purpose of the virtual memory system is to apparently expand a small amount of memory space to a large amount of space by the mechanism described above, but secondarily realizes a memory protection function. The memory protection is a function of storing the access information about the corresponding virtual address together with the real address of the address conversion table and suppressing the access against the access information. For example, the execution environment of the processor may be classified into an OS level and an application level so that a program operating at the application level cannot access the OS-level virtual space. This is for the purpose of protecting the OS program from being destroyed due to runaway of the application program or intentional access. In addition, each unit area of the virtual address space is classified by the attribute of executable, readable, and writable, and by detecting an access contrary to the attribute, a logical mistake of the program is notified to the program and the execution is stopped. Protection is also considered. Generally, the virtual memory system is provided by combining an address translation mechanism and a memory protection mechanism.

A processor which provides a memory protection mechanism provides a program with a function of checking an access right to an arbitrary virtual address to see whether or not the area is accessible. The present invention solves the problems of the conventional access right inspection method.

FIG. 2 is a block diagram showing an address translation mechanism and a protection mechanism in a conventional processor. Two
00 is an address translation buffer (TLB), 201 is a TL
An associative RAM (ARAM) with multiple entries in B,
202 is a data RAM (DRAM) having the same number of entries as the associative RAM in the TLB, 203 is a hit signal of the TLB associative RAM, 204 is a selection signal of the data RAM, and 205 is a register (PEL) for holding the execution level of the processor. ), 206 is a decoder (DEC), 207 is an access right checking mechanism (PROT), 208 is a register (STAT) which holds protection information as a result of address translation,
Reference numeral 209 is a control circuit (REPCONT) for reading the address conversion table on the memory into the TLB, 210 is an address bus (ABUS) communicating with the outside of the processor, 211 is a data bus (DBUS) communicating with the outside of the processor, 2
Reference numeral 12 denotes a data bus (VA bus) for transferring a virtual address for address translation to the associative RAM of the TLB, and transfer of protection information of an address translation result, and 213 denotes access information accompanying the virtual address for address translation. A transfer data bus (VT bus) 214 is a data bus (RA bus) for transferring a real address, which is the result of address conversion, to and from the TLB data RAM.

When performing address translation, a virtual address and access information (read, write, or execute) associated with the virtual address are transferred on the VA bus 212 and the VT bus 213, respectively. The virtual address transferred by the VA bus 212 is the ARAM 2 of the TLB 200.
Each entry of 01 is compared, and if any entry in the ARAM 201 is hit, the hit signal 203 becomes "1", and if there is no hit, the hit signal 203 becomes "0". When the hit signal 203 becomes “1”, the specific entry of the data RAM 202 is selected by the selection signal 204, and the real address corresponding to the virtual address is output from the DRAM 202 to the RA bus 214. When the hit signal 203 becomes “0”, REPCO
NT209 is activated, controls ABUS 210,
The contents of the address conversion table (real address and memory protection information) in the memory external to the processor are stored in DBUS 2
Read from 11 to RA bus 214. And TLB
One of the entries of the ARAM 201 of 202 and the entry of the DRAM 202 corresponding to the entry,
The virtual address transferred from the VA bus 212 and the contents of the address conversion table transferred to the RA bus 214 are stored. This mechanism ensures that the virtual address is TLB
It will hit 200 ARAM 201s.

The access right is checked by D of TLB 200.
The memory protection information stored in the entry of the RAM 202, the execution level PEL 205 of the processor, and
The access information notified through the VT bus 213 is DE
According to the result decoded by C 206, PROT
207 and the result is stored in STAT 208.

FIG. 3 is a detailed block diagram of the mechanism for checking access rights. In FIG. 3, PEL 205, DE
C 206, PROT 207, STAT 208, V
The T bus 213 is the same as that shown in FIG. 100
Is data R corresponding to the virtual address hit by TLB
One specific entry of AM (202 in FIG. 2) is shown. 101 to 107 are contents of the address conversion table stored in the entry 100, 101 is a real address (RADR), 102 is an executable level (EEL),
103 is a readable level (REL), 104 is a writable level (WEL), 105 is an execution permission (E), 10
Reference numeral 6 holds read permission (R) and 107 holds write permission (W) information. Reference numerals 108, 109, and 110 are comparators, which are the execution level PEL 205 and the execution level EEL for each attribute of execution, read, and write.
102, REL 103, and WEL 104 are compared. If the execution level (102 to 104) of each attribute and the execution level PEL 205 of the processor have a magnitude relation allowing access, the outputs of the comparators 108 to 110 are "1". If the execution levels have a magnitude relation that does not allow access, the outputs of the comparators 108 to 110 are "0". Reference numerals 111 to 113 denote AND gates, which are comparators 108 which are the results of the access right check on the execution level.
The output of 110 and the protection information 105 to 107 of the area in the entry 100 of the DRAM of the TLB are ANDed. As a result, the outputs of the AND gates 111 to 113 become the access right permission / prohibition signals related to execution, read, and write at the execution level PEL 205, respectively. DE
The C 206 decodes the access information transferred along with the virtual address through the VT bus 213, and generates a signal 114 indicating execution access, a signal 115 indicating read access, and a signal 116 indicating write access.
Each of the signals 114 to 116 becomes "1" at the target access and becomes "0" at other accesses.
Reference numerals 117 to 119 denote NAND gates, which output signals from AND gates 111 to 113 and signals 114 to indicate each access
Take the NAND of 115. If any of the outputs of the NAND gates 117 to 119 is "1" by the mechanism described above, it indicates that there is a protection violation regarding the access for which the address conversion is performed. The outputs of NAND gates 117-119 are held in register STAT 208 and read from the VA bus (212 in FIG. 2, not shown in FIG. 3).

In the above-mentioned conventional memory protection mechanism, the access right check is realized as follows. This will be described with reference to FIGS. 2 and 3. In the access right inspection request, the virtual address to be inspected is notified by the VA bus 212 in FIG. 2, and the information about the inspection is notified by the VT bus 213. The information regarding the inspection includes an execution level for performing the inspection and access information regarding execution, read, and write. The address to check is TLB 200
If it doesn't hit ARAM 201, REPCON
T209 allows ARAM 201, DRAM 2
The contents of 02 are updated. Access right inspection is PROT
207. If PROT 207 does not cause a protection violation, the inspected virtual address is accessible. However, the comparison of execution levels is DRAM
Since it is performed between 102-104 included in the entry of 202 and PEL 205 which is the execution level of the processor, it is incorrect when the execution level for checking the access right transferred by the VT bus 213 and the PEL 205 do not match. Notify the inspection result. Therefore, when the execution level to be inspected does not match the PEL 205, it is necessary to execute the access right inspection by another means such as a microprogram.

[0011]

As described above, in the access right inspection in the conventional processor, it is necessary to divide the processing depending on whether or not the execution level at which the access right should be inspected matches the current execution level of the processor. there were. If the execution level for which the access right is to be checked does not match the current execution level of the processor, the following steps are required if the processing is performed by the microprogram. (1) The real address corresponding to the virtual address and the real address of the address conversion table in which the protection information is stored are calculated. (2) The contents of the address conversion table are read into the processor by controlling the address bus and the data bus. (3) Check the access right for the execution level of execution, read, and write. (4) Inspect access rights regarding attributes of execution, read, and write. The processing of (1) and (2) is necessary even when the virtual address for checking the access right does not hit the TLB, but the processing of (1) is executed by a microprogram if it is executed only by hardware. The execution speed is faster by at least one clock or more than in the case. Also,
As for the processing of (3) and (4), it can be processed by one clock if it is performed by hardware. However, according to the microprogram, at least 6 can be obtained by repeating calculation, inspection and determination twice.
Clock time is needed. Therefore, if the microprogram performs the processing when the execution level for which the access right is to be checked does not match the current execution level of the processor, the processing time will be delayed by 6 clocks or more. Also,
In order to realize the processing equivalent to this microprogram by providing dedicated hardware other than the address translation mechanism and memory protection shown in FIGS. 2 and 3, hardware of the same scale as in FIGS. 2 and 3 is required. It is necessary and a waste of resources.

An object of the present invention is to provide a mechanism for checking access right at a high execution level different from the current execution level of a processor at a high speed, with almost no change in the hardware of the conventional address translation mechanism and memory protection mechanism. To do.

[0013]

An access right inspection apparatus of the present invention comprises an address translation buffer buffer for performing translation from a virtual address to a real address, a register for holding an execution level of a processor, a selector, and In a virtual memory management mechanism having an access right inspection mechanism for inspecting an access right to a virtual address according to the contents of an address translation buffer and the contents of a register holding the execution level of the processor, the execution level of the processor is set by the selector. , It has a function of performing access right inspection by switching to any temporary execution level.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of an access right inspection device using the present invention. Compared with the conventional access right inspection device shown in FIG. 3, the information about the access right inspection provided by the VT bus 213 is DE
Execution level 120 for inspecting the access right decoded and fetched by C 206, PEL 205 which is the current execution level of the processor, selector 121 for selecting one of the execution levels for inspecting the access right, and selection control for selector 121 Signal 122 is added. Data RAM in TLB, which is a component of FIG.
Contents 100-107, comparators 108-110, AND
Gates 111 to 113, signals 114 to 115 indicating access attributes of execution, read, and write, NAND gate 1
17-119, PEL 205, DEC 206, PR
OT 207, STAT 208, and VT 213 are shown in FIG.
Since it is the same as the constituent element of the conventional example shown in FIG.

As described above, the VT bus 213 notifies the address translation request or the access right inspection request for the address translation mechanism and the memory protection mechanism shown in FIGS. The address conversion request and the access right inspection request include information indicating which type of access is to be executed, read or write.
6 is decoded into signals of access attributes 114 to 116. If the request notified by the VT bus 213 is an access right check request, information on which execution level the access right should be checked is further included. The DEC 206 decodes the information regarding the access right check request and extracts the execution level into the signal 120. At this time, the selection control signal 122 for the selector 121 is determined by the DEC 206 to select the PEL 205 if the request is an address translation and the decoded execution level 120 if the request is an access right check. In the access check mechanism having such a configuration, the access right check temporarily changes the execution level of the current processor to the execution execution level for which the access right should be checked, performs address conversion, and violates the memory protection. Equivalent to checking for the existence. If there is no protection violation, that is, if all the outputs of the NAND gates 117 to 119 are "0", the access is possible, and if any one of the outputs of the NAND gates 117 to 119 is "1", the access is not possible. Become. After the access right is determined, the selection control signal 12 for the selector 121
2 shall be controlled to select PEL 205.

[0017]

As described above, the use of the present invention makes it possible to check the access right of the execution level different from the current execution level of the processor, and substantially change the conventional hardware for address translation and memory protection. It can be realized at high speed. If the present invention is not used, the performance will be reduced by at least 6 clocks or more, or the hardware resources for memory protection will be doubled.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an address translation mechanism and a memory protection mechanism assumed in a conventional example and an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example of the present invention.

[Explanation of symbols]

100 1 entry of data RAM in TLB 101 real address information (RADR) 102 executable level information (EEL) 103 readable level information (REL) 104 writable level information (WEL) 105 execution permission information (E) 106 read permission Information (R) 107 Write permission information (W) 108, 109, 110 Comparators 111, 112, 113 AND gate 114 Signal indicating execution access attribute 115 Signal indicating read access attribute 116 Signal indicating write access attribute 117, 118, 119 NAND gate 120 Execution level for performing access right check 121 Selector 122 Selection control signal 200 Address translation buffer (TLB) 201 Associative RAM (ARAM) 202 Data RAM (DRAM) 203 TLB hit signal 04 Data RAM Selection Signal 205 Processor Execution Level (PEL) 206 Decoder (DEC) 207 Access Right Check Mechanism (PROT) 208 Register (STAT) 209 Holding Protection Information 209 Control Circuit for Reading Address Translation Table on Memory to TLB (REPCONT) 210 Address bus (ABUS) 211 Data bus (DBUS) 212 Bus for transferring virtual address information (VA bus) 213 Bus for transferring additional information of VA bus (VT bus) 214 Bus for transferring real address information ( RA bus)

Claims (1)

[Claims] 1. An address translation buffer for performing translation from a virtual address to a real address, a register for holding an execution level of a processor, and a selector,
Normally, the access right to the virtual address is checked according to the contents of the address translation buffer and the contents of the register holding the execution level of the processor, and the execution level of the processor is set to an arbitrary temporary execution level by the selector. An access right inspection device characterized by performing access right inspection by switching.