JPH0561571A - Chattering preventing circuit for one-chip microcomputer - Google Patents

Abstract

PURPOSE:To reduce energy consumption and to miniaturize the circuit by adopting a counter by executing pull-up for fixed time in a fixed cycle and sampling a level at the time point of pull-up. CONSTITUTION:A pull-up transistor 2 is pulled up only for fixed time by a D flip-flop 4 and an AND gate 5, and the level at the time point of pull-up is counted by an up counter 8 with synchronous set/reset. Thus, chattering is removed, an interrupting signal is generated, and data are held in a D latch 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chattering prevention circuit.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, a signal REA is used to eliminate chattering of an input signal of a one-chip microcomputer.
Enable D, read input data several times,
Chattering was being removed. However, in FIG.
If the switch input is always ON, the current continues to flow from V _DD to GND, and a portable device or the like having a small battery capacity accelerates battery consumption. FIG. 6 is a modification of FIG. 5, in which data is read by enabling signal pull-up and enabling signal READ only when reading input data. As a result, even if the switch is still input, the current flows from V _DD to GND only during pull-up, and the battery consumption is reduced.

[0003]

However, in both FIGS. 5 and 6, since the program in the microcomputer has the function of removing chattering, the program in the IC becomes heavy and high-speed processing is required in a low-speed machine cycle. However, there is a drawback that it cannot respond. This invention is
In order to solve such conventional drawbacks, it is an object of the present invention to realize chattering elimination by a circuit, reduce the load of programming, and provide a compact circuit by using a counter circuit.

[0004]

In order to solve the above problems, the present invention pulls up at a fixed cycle for a fixed period and samples the level at the time of pulling up.
Low power consumption and synchronous set / reset
A compact chattering elimination circuit was realized by using an up counter.

[0005]

[Function] Sampling the switch input at a constant cycle,
Chattering of the switch input can be eliminated by counting the counter when the switch input is made at the time of sampling and resetting the counter when the switch input is not made.

[0006]

1 is a circuit diagram of a chattering elimination circuit of the present invention, and FIG. 2 is a timing chart thereof. The input terminal 20 is pulled up because the pull-up transistor 2 is ON for the period of the clock A and the period of the clock B (when the signal E of FIG. 2 is High). AND gate 3
Is V _DD -G inside the IC when it is not pulled up.
This is for preventing a through current between NDs and for resetting the counter 8 when the switch 1 is OFF during pull-up. Reset is clock C of counter 8.
It is performed in synchronization with the rising edge of the input of. While the input terminal 20 is not pulled up, the reset signal R of the counter 8 is disabled and the counter 8 shows the previous value.

If the switch 1 remains ON during pull-up, the counter 8 counts up in synchronization with the rising of the signal C, and the output signals Q1 and Q2 of the counter 8 are 1,
Further, when the positive logic input of the gate 9 is 0, the output of the gate 9 becomes 1. As a result, when the data is different from the data stored in the latch 10, the EOR gate 12 becomes 1 and the interrupt signal is enabled. By this interrupt processing, the program enables the signal READ, outputs the result of the switch input to the data bus, and reads the data. The clock input of the latch 10 receives a one-shot pulse generated from an interrupt signal, and the value of the latch 10 is updated when an interrupt occurs. Case 1 of FIG.
If the switch is inputting, in case 2, the switch is ON
-It is a time chart when it changes to OFF.

In FIG. 3, a shift register realizes a function similar to that of FIG. 1, and the number of D-flip-flops is larger than that of FIG. As described above, since it is a counter type, the larger the number of samples, the smaller the number of D-flip-flops. In FIG. 4, four sets of counters 8 shown by the chain double-dashed line in FIG. 1 are prepared.
When any one of the input terminals 21 to 24 is switched on for the period of the signal A × 3 or more, an interrupt signal is generated.
The signal READ is enabled by the interrupt processing of the program, and the switch input is read. An interrupt also occurs when the switch changes from ON to OFF, but this frequency does not become shorter than the cycle of the signal A, so the program does not have to perform this interrupt process frequently. In addition, D
B0, DB1, DB2, DB3 are signals sent to the data bus in the microcomputer.

[0009]

As described above, according to the present invention, the power consumption is reduced by pulling up at a constant period for a certain period and sampling the level at the time of pulling up, and a synchronous counter is used. This has the effect of providing a compact chattering removal circuit.

[Brief description of drawings]

FIG. 1 is a chattering removal circuit diagram of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a chattering removal circuit using the shift register of the present invention.

FIG. 4 is a configuration diagram of four sets of input terminals used in the present invention.

FIG. 5 is a conventional switch input circuit diagram.

FIG. 6 is a conventional switch input circuit diagram.

[Explanation of symbols]

 1 Switch 2 Pull-up Transistor 3 AND Gate 4 D-Flip Flop 5 AND Gate 6 D-Flip Flop 7 Inverter 8 Synchronous Set / Reset Up Counter 9 OR Gate 10 D Latch 11 Bus Driver 12 EOR Gate 13 OR Gate 14 One Shot pulse generation circuit

Claims (1)

[Claims] 1. A flip-flop and a gate circuit pull up a pull-up transistor only for a fixed period, and an up counter counts the level at the time of pull-up to eliminate chattering and generate an interrupt signal. In addition, a chattering prevention circuit characterized by holding data in a latch circuit.