JPH0557934U - PLL synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if it is driven at a low voltage, the frequency lockup time is short without reducing the specific number of LPFs.
Get the LL synthesizer. [Structure] It is composed of transistors Tr ₁ , Tr _2, etc.,
P including a charge pump 11 that outputs a phase error signal
In the LL synthesizer, the transistor Tr ₃ is Darlington-connected between the collector and the emitter of the transistor Tr ₁ .

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a PLL synthesizer used for frequency control of a high frequency signal such as a carrier wave signal or a local oscillation signal in a wireless communication device such as a cordless phone or a mobile phone.

[0002]

[Prior Art]

 FIG. 3 is a block diagram showing a first configuration example of a conventional PLL synthesizer, in which 1 is a voltage controlled oscillator (hereinafter referred to as VCO) that outputs a high frequency signal such as a carrier signal or a local oscillation signal, 2 is an output terminal for outputting a high frequency signal, 3 is a prescaler (fixed frequency divider) that divides the high frequency signal by a preset division ratio (1 / M) and outputs the divided signal, 4 is a program It is a counter (variable frequency divider), and further divides the frequency-divided signal by a frequency division ratio (1 / N) corresponding to the channel selection signal output from the channel selection circuit 5.

Reference numeral 6 is a reference frequency oscillator that uses a crystal oscillator or the like and oscillates an oscillation signal of a reference frequency. Reference numeral 7 is a phase comparator that detects the phase of the oscillation signal and the phase of the output signal of the program counter 4. When the former phase leads the latter phase, the leading signal φP is output, and when the former phase lags the latter phase, the lagging signal φR is output.

Further, 8 is a charge pump composed of an NPN type transistor Tr ₁ and a PNP type transistor Tr _2, etc., which amplifies the output current of the phase comparator 7 and, at the same time, advances the phase signal φP and delays the phase signal. φR is added in opposite phase and output as a phase error signal. Reference numeral 9 is a low-pass filter (hereinafter, referred to as LPF) that controls the oscillation frequency of the VCO 1 by its output voltage, and removes harmonic components such as the output signal of the phase comparator 7 superimposed on the pulse-shaped phase error signal. In addition to removing it, the voltage of the phase error signal is integrated.

In such a configuration, when the operator operates the tuning circuit 5 to tune to a predetermined channel, the tuning circuit 5 outputs a selection signal and the program counter 4 corresponding to the predetermined channel. Set the frequency division ratio (1 / N). As a result, the control voltage proportional to the phase error signal is output from the LPF 9 and input to the control voltage input terminal of the VCO 1, so that the frequency of the high frequency signal output from the VCO 1 is locked to the frequency corresponding to the predetermined channel. To do. The shorter the time to lock, that is, the shorter the lock-up time, the more stable the frequency of the high-frequency signal output from the VCO 2 becomes to a predetermined value.

By the way, along with the recent decrease in the voltage of electronic devices, the wireless communication devices using the PLL synthesizer described above are also decreased in voltage, and due to this decrease in voltage, the gain of the charge pump 8 and the output of the phase comparator 7 are reduced. The voltage drops. As a result, the frequency lock-up time of the PLL synthesizer becomes long, and the performance of the entire electronic device is also reduced. Therefore, in order to shorten the frequency lockup time even when the voltage is lowered, the time constant of the LPF 9 may be reduced, or the gain of the charge pump 8 or the sensitivity of the VCO 1 may be increased, as shown below.

Here, _assuming that the closed-loop natural frequency of the PLL synthesizer shown in FIG. 3 is ω _n and the step response number is M, these are expressed by the following equations 1 and 2, respectively.

[Equation 1]

[Equation 2] Where A is the gain of the charge pump 8, K is the sensitivity of the VCO 1 (Δf / ΔV), T is the frequency lockup time, and R ₁ , R ₂ and C ₁ are the values of the two resistors and one capacitor of the LPF 9, respectively. Is. As can be seen from Expressions 1 and 2, in order to shorten the frequency lockup time, the time constant of the LPF 9 may be reduced, or the gain A of the charge pump 8 or the sensitivity K of VCO 1 may be increased.

Next, FIG. 4 shows a block diagram of a second configuration example of a conventional PLL synthesizer provided with an active filter using an operational amplifier in order to shorten the frequency lockup time. In this figure, parts corresponding to those in FIG. 3 are assigned the same reference numerals and explanations thereof are omitted. In FIG. 4, an active filter 10 including an operational amplifier OP, a resistor having values R ₃ and R _4, and a capacitor having a value C ₂ is newly provided between the charge pump 8 and the LPF 9. ..

Since the operation is almost the same as that of the above-mentioned first configuration example, the description thereof will be omitted. The frequency synthesizer of the PLL synthesizer of FIG. 4 has a shorter frequency lock-up time than the PLL synthesizer of FIG. 3 because the output current of the charge pump 8 is amplified by the operational amplifier OP and supplied to the VCO 1 through the LPF 9. In other words, the driving force or control force is increased. Although the LPF 9 is not necessary because the active filter 10 is provided, the characteristics of the entire filter are better when the LPF 9 is present than when the LPF 9 is removed.

[0010]

[Problems to be solved by the device]

 In the conventional PLL synthesizer described above, first, in the case of the first configuration example, if the time constant of the LPF 9 is made small in order to shorten the frequency lockup time, it is caused by the output signal of the phase comparator 7. The harmonic components are not sufficiently removed by the LPF 9. As a result, the harmonic component remains superimposed on the high-frequency signal output from the VCO 1, and this PLL synthesizer has the drawback that it cannot satisfy the harmonic suppression ratio standard. Further, if the sensitivity K (Δf / ΔV) of the VCO 1 is increased instead of decreasing the time constant of the LPF 9, the performance of the VOC 1 itself (for example, S / N or C / N, etc.) that responds to external noise or internal noise is increased. ) Was reduced.

Further, in the case of the second configuration example, when used at a low voltage, the output voltage of the operational amplifier OP becomes low, but the noise level of the operational amplifier OP remains unchanged, so that the S / N ratio is relatively high. Getting worse. Further, the addition of the operational amplifier OP increases the noise amount of the entire circuit, so that there is a problem that the S / N and C / N of the entire circuit are deteriorated as compared with the first configuration example. The present invention has been made under such a background, and an object thereof is to provide a PLL synthesizer which can realize a low voltage without deteriorating the performance of equipment and has a short frequency lockup time. ..

[0012]

[Means for Solving the Problems]

 This invention is directed to a voltage-controlled oscillator that outputs a high-frequency signal, a frequency divider that divides the high-frequency signal and outputs a divided signal, a reference frequency oscillator that outputs an oscillation signal of a reference frequency, and an oscillation signal of the oscillation signal. The phase comparison is made up of a phase comparator that compares the phase with the phase of the frequency-divided signal and outputs a phase-advance signal or a phase-delay signal according to the result, an NPN-type transistor, a PNP-type transistor, and the like. It not only amplifies the output current of the converter but also adds the phase-advancing signal and lag-phase signal in opposite phase and outputs as a phase error signal, and removes the harmonic components from the phase error signal. In the PLL synthesizer, the phase error signal is voltage-integrated, and a low-pass filter for controlling the oscillation frequency of the voltage-controlled oscillator according to the output voltage thereof is used. It is characterized in that the at least one of the NPN transistor and the PNP-type bets transistor of Jiponpu constituted by Darlington-connected transistors.

[0013]

According to the above configuration, the collector current of the Darlington-connected transistor of the charge pump becomes a direct current amplification factor times as large as that in the case where the Darlington connection is not made. Therefore, when a delayed signal or a advanced signal is input. The gain of this charge pump is larger than that of the conventional charge pump, and the frequency lockup time is shorter than that of the conventional charge pump.

[0014]

【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PLL synthesizer according to a first embodiment of the present invention. In this figure, parts corresponding to those in FIG. To do. In the PLL synthesizer shown in this figure, instead of the charge pump 8, a charge pump 11 in which a transistor Tr ₃ is Darlington-connected between the collector and emitter of the transistor Tr ₁ is newly provided.

[0015] As described above, by Darlington-connected transistors Tr ₁ and Tr _3, the collector current I _C3 of the transistor Tr ₃ is a h _FE times the collector current I _C3 of the transistor Tr _1. As a result, the gain of the charge pump 11 when the delay signal φR is input is larger than the gain of the conventional charge pump 8. Therefore, the delay signal φR is input according to the equations 1 and 2 described above. In this case, the frequency lockup time will be shorter than before. According to the experiment, the frequency lockup time when the delay signal φR of the PLL synthesizer is input is shortened by 20 to 30% compared with the conventional case.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of a PLL synthesizer according to a second embodiment of the present invention. In this figure, parts corresponding to those in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted. In this PLL synthesizer shown in FIG., In place of the charge pump 11, a charge pump 12 which transistor Tr ₄ is Darlington-connected between the collector and the emitter of the Tran register Tr ₂ are newly provided.

With such a configuration, the gain of the charge pump 12 becomes larger than that of the conventional charge pump 8 regardless of whether the delay signal φR or the advance signal φP is input. From Equations 1 and 2 described above, the frequency lockup time when the delay signal φR and the advance signal φP are input is shorter than in the conventional case.

As described above, according to this embodiment, the frequency lockup time can be shortened without reducing the time constant of the LPF 9, so that the harmonic components from the control voltage input to the VCO 1 can be shortened. It does not sacrifice the LPF9's ability to remove the. Further, according to this embodiment, the frequency lock-up time can be shortened without increasing the sensitivity of the VCO 1, so that the performance of the VCO 1 itself (for example, S / S) corresponding to external noise or internal noise can be reduced. N, C / N, etc.) does not decrease.

[0019]

[Effect of the device]

 As described above, according to this invention, there is an effect that a low voltage can be realized without deteriorating the performance of the device. In addition, the frequency lockup time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL synthesizer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a PLL synthesizer according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a first configuration example of a conventional PLL synthesizer.

FIG. 4 is a block diagram showing a second configuration example of a conventional PLL synthesizer.

[Explanation of symbols]

1 VCO 3 Prescaler 4 Program counter 5 Tuning circuit 6 Reference frequency oscillator 7 Phase comparator 8, 11, 12 Charge pump 9 LPF 10 Active filter Tr _{1 to} Tr ₄ transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 E

Claims (1)

[Scope of utility model registration request] 1. A voltage-controlled oscillator that outputs a high-frequency signal, a frequency divider that divides the high-frequency signal and outputs a divided signal, a reference frequency oscillator that outputs an oscillation signal of a reference frequency, and the oscillation signal. Comparing the phase of and the phase of the divided signal,
A phase comparator that outputs a phase advance signal or a phase lag signal according to the result, and an NPN type transistor, a PNP type transistor, etc. Add signals in opposite phase,
A charge pump that outputs as a phase error signal, and removes harmonic components from the phase error signal,
A PLL synthesizer comprising: a low-pass filter for voltage-integrating the phase error signal and controlling an oscillation frequency of the voltage-controlled oscillator according to an output voltage thereof, wherein at least one of the NPN transistor and the PNP transistor of the charge pump is A PLL synthesizer characterized by comprising transistors connected in Darlington.