JPH0552909A - Detection of strobe timing setting error - Google Patents

Abstract

PURPOSE:To prevent the occurrence of wrong judgment caused by a programming error by providing a circuit which inputs a strobe signal, etc., to a data input circuit and outputs an error signal upon detecting a difference between the outputting order of the output data of a circuit to be tested and that of the strobe signal, etc. CONSTITUTION:The flip-flop circuits 101-104 of an error detection circuit respectively constitute counters and the circuits 101 and 102 count a strobe signal 17, with the circuits 103 and 104 counting another strobe signal 19. An AND/OR circuit 105 outputs an error signal 106 by decoding an error code from the output codes of the two counters. Therefore, the reliability is improved, because a strobe setting error can be surely detected through hardware and the occurrence of wrong judgment caused by a programming error can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI tester capable of setting a strobe for each test cycle over the next cycle, and has a circuit capable of detecting a strobe timing setting error caused by shortening a strobe interval. Regarding the LSI tester.

[0002]

2. Description of the Related Art Conventionally, as an LSI tester, there is an example as shown in FIG. In FIG. 11, the timing generator 1 sets the timing of the edges and strobes of the waveform, and the formatter 2 inputs the timing output from the timing generator 1 and the waveform data from the pattern memory 16,
The waveform is output to the circuit under test 4 via the driver 3. The output signal from the circuit under test 4 is judged by the comparator 5 to be either low level, high level or high impedance, and is input to the flip-flop circuits 6 and 7 as comparison data 23. The D-flip-flop circuits 6 and 7 respectively latch the comparison data with strobe signals 17 and 19, respectively, and the latched signals are compared with expected values 21 and 22 by exclusive ORs 8 and 9. The FIFOs 10 and 11 fetch the outputs of the exclusive ORs 8 and 9 and the latched signal by strobe signals 18 and 20 which are timed to the data. FI
The outputs of the FOs 10 and 11 are passed through the multiplexer 12 to R
It is connected to AM13. Further, 14 is a CPU, and 15 is a pattern generator.

[0003]

When an error in strobe timing setting occurs in the above-mentioned LSI tester, the flip-flop circuits 6 and 7 respectively latch the test results of the other, and the exclusive ORs 8 and 9 are used. The test result is compared with the expected value of the other test, which causes an erroneous judgment. The conventional LSI tester does not have a function of detecting the error, and the programmer has to check it during programming. At this time, if errors are overlooked, it leads to erroneous judgment, which leads to a decrease in reliability of the test due to human error. Therefore, an object of the present invention is to realize an LSI tester that reliably detects an error occurrence by hardware and prevents an erroneous determination due to a program error.

[0004]

In order to achieve such an object, the present invention connects a strobe timing setting error detection circuit to a strobe signal of a data input circuit of an LSI tester.

[0005]

When the strobe timing setting error occurs during LSI testing, the error detection circuit outputs an error signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.
In FIG. 1, reference numeral 100 denotes an error detection circuit, which is 1 to 2
Up to 3 is the same as in FIG. The structure of the error detection circuit 100 is shown in FIG. In FIG. 2, 101, 102, 10
3, 104 are D-flip-flop circuits, 105 is a logical product / logical sum gate circuit, 17 and 19 are strobe signals,
Reference numeral 24 is a clear signal, and 106 is an error signal. The flip-flop circuits 101 and 102 and 103 and 104 respectively constitute counters.
01 and 102 count the strobe signal 17, and the flip-flop circuits 103 and 104 count the strobe signal 19. The logical product / logical sum gate circuit 105 decodes an error code from the output codes of the two counters and outputs an error signal 106. 110, 120, 130, 1
40 are flip-flop circuits 101 and 102,
These are Q ₁ , Q ₂ , Q ₃ , and Q ₄ outputs of 103 and 104.

FIG. 3 is a timing chart showing the relationship between the strobe signals 17 and 19 and the comparison data 23. Although the time for generating the strobe signals 17 and 19 in FIG. 3 is set after the data is output to the circuit under test and the strobe signals are alternately operated, the apparent strobe interval can be shortened. If the order of the actual strobes is changed as in (a), the other comparison data will be latched.

The error detection operation having the above configuration will be described. In the error detection circuit of FIG. 2, the flip-flop circuits 101 to 104 have Q ₁ output 110 and Q ₂ output 12
The 0, Q ₃ output 130 and Q ₄ output 140 are set to “0” by the clear signal 24. When the strobe signals 17 and 19 are alternately input from this state, the outputs Q ₁ 110 and Q ₂ 120 of the flip-flop circuit are output in the normal operation loop indicated by the double-lined arrow in the state transition diagram shown in FIG. , Q ₃ 130,
Q ₄ 140 changes. However, when the strobe signal 17 is input twice in succession or the strobe signal 19 is input twice in succession, the normal operation is changed to the deviated state indicated by the single-line arrow. At this time, the AND / OR gate circuit 105 decodes the code in the deviated state and outputs the error signal 106. For example, in the operation example shown in the timing chart of FIG. 5, when the strobe signal 17 is continuously input as indicated by the broken line B in FIG. 5, the code is deviated from the normal state “1110” as indicated by the broken line C in FIG.
0 ", and the error signal 106 is output as indicated by the broken line D in FIG.

The error detection circuit may have the configurations shown in FIGS. 6 and 8. In FIG. 6, 25 and 26 are toggle flip-flop circuits, 28 and 29 are D-flip-flop circuits, 27 is an exclusive OR, 30 is a logical product, 17 and 19 are strobe signals, 33, 34 and 36,
37 is a flip-flop circuit 25, 26, 2 respectively
8 and 29 outputs, 35 is exclusive OR 27 output, 10
6a is an error signal.

When the strobe signals 17 and 19 are alternately input after the flip-flop circuits 25 and 26 are cleared, the output 35 of the exclusive OR 27 is "0" with respect to the input of the strobe signal 17 and the strobe signal 19 is input. However, the output 106a of the logical product 30 is always "1". However, when the strobe signal 17 is input twice in succession or the strobe signal 19 is input twice in succession, the output 106a becomes "0". An example of this operation is shown in FIG.
Is shown in the timing chart of. Also, in FIG.
Is a logical sum, and 32 is a toggle flip-flop circuit. In the circuit of FIG. 8 as well, if the strobe signals 17 and 19 are alternately input, the output 106b is always "1", and if an error occurs, the output 106b is "0". Further, as shown in FIGS. 9 and 10, the error detection circuit is provided with strobe signals 18, 20 or strobe signals 18, 20 respectively.
It is also possible to connect to an IR (Input Ready) signal synchronized with the data fetch timing of the FIFO.

[0011]

As is clear from the above description,
The present invention has the following effects. That is, by providing the error detection circuit in the LSI tester, it is possible to reliably detect an error in strobe setting by hardware. Therefore, the efficiency at the time of program debugging is improved, erroneous determination due to a program mistake can be prevented, and reliability is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an LSI tester according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of an error detection circuit according to the present invention.

FIG. 3 is a strobe signal and comparison data 23 according to the present invention.
FIG. 6 is a timing chart showing the relationship of

FIG. 4 is a state transition diagram showing an operation example of the error detection circuit of FIG. 2 according to the present invention.

5 is a timing diagram showing an operation example of the error detection circuit of FIG. 2 according to the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the error detection circuit according to the present invention.

7 is a timing diagram showing an operation example of the error detection circuit of FIG. 7 according to the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the error detection circuit according to the present invention.

FIG. 9 is a circuit diagram showing a second connection example of the error detection circuit according to the present invention.

FIG. 10 is a circuit diagram showing a third connection example of the error detection circuit according to the present invention.

FIG. 11 is a circuit diagram showing an example of a conventional LSI tester.

[Explanation of symbols]

1 Timing Generator 2 Formatter 3 Driver 4 Circuit Under Test 5 Comparator 6, 7, 25, 26, 28, 29, 32, 101, 10
2, 103, 104 flip-flop circuit 8, 9, 27 exclusive OR 10, 11 FIFO 12 multiplexer 13 RAM 14 CPU 15 pattern generator 16 pattern memory 17, 18, 19, 20 strobe signal 21, 22 expected value 23 comparison Data 24 Clear signal 30 Logical product 31 Logical sum 35 Output of exclusive OR 100 Error detection circuit 105 Logical product / OR gate circuit 106 Error signal 33, 34, 36, 37, 110, 120, 130, 1
40 flip-flop circuit output

Claims (1)

[Claims] 1. An LSI tester having a data input circuit for sequentially fetching output data of a circuit under test according to a plurality of strobe signals generated by a programmable timing generator, wherein the data input circuit has the strobe signal or a signal synchronized with the strobe signal. Is provided as an input, and an error detection circuit for detecting a difference in the output order of the strobe signal with respect to the output order of the output data of the circuit under test and outputting an error signal is provided.