JPH0550768U - Circuit board connection structure - Google Patents
Circuit board connection structureInfo
- Publication number
- JPH0550768U JPH0550768U JP9998891U JP9998891U JPH0550768U JP H0550768 U JPH0550768 U JP H0550768U JP 9998891 U JP9998891 U JP 9998891U JP 9998891 U JP9998891 U JP 9998891U JP H0550768 U JPH0550768 U JP H0550768U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- lead terminal
- terminal group
- shaped
- slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Accessory Devices And Overall Control Thereof (AREA)
- Multi-Conductor Connections (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】
【目的】コネクタあるいは電線などの接続部品を省き、
薄型小型な電子機器を提供するとともに、容易なサブア
ッセンブリを実現し低価格の電子機器を提供すること。
【構成】カードエッジ形状のリード端子群を有するメモ
リ基板2を、制御基板1のスリット状の穴に挿入し、ス
リット状の穴の端面に形成されるリード端子群5と導通
させる。
(57) [Summary] [Purpose] Omit connection parts such as connectors or electric wires.
To provide a thin and compact electronic device, and to provide a low-priced electronic device that realizes easy subassembly. [Structure] A memory board 2 having a card-edge-shaped lead terminal group is inserted into a slit-shaped hole of a control board 1 and is electrically connected to a lead terminal group 5 formed on an end face of the slit-shaped hole.
Description
【0001】[0001]
本考案はパーソナルコンピュータあるいはプリンタなどの電子機器に使用され る回路基板の接続構造に関する。 The present invention relates to a connection structure for a circuit board used in an electronic device such as a personal computer or a printer.
【0002】[0002]
従来の回路基板の接続はコネクタあるいは電線などの接続部品を用いていた。 Conventionally, connection parts such as connectors or electric wires have been used to connect circuit boards.
【0003】[0003]
しかし前述の従来技術は、コネクタあるいは電線などの接続部品が必要なため 、電子機器のサイズが大きくなるという問題点を有していた。また接続部品費が 余分にかかり、しかもそのサブアッセンブリが煩雑なため、電子機器のコストが アップするという問題点も有していた。本考案は以上に述べた課題を解決するも ので、その目的とするところは、コネクタあるいは電線などの接続部品を省き、 薄型小型な電子機器を提供するとともに、容易なサブアッセンブリを実現し低価 格の電子機器を提供することにある。 However, the above-mentioned conventional technique has a problem that the size of the electronic device is increased because a connecting component such as a connector or an electric wire is required. In addition, there is a problem in that the cost of electronic equipment increases because the cost of connecting parts is extra and the subassembly is complicated. The present invention solves the above-mentioned problems. The purpose of the present invention is to eliminate connecting parts such as connectors or electric wires, provide thin and compact electronic devices, and realize an easy sub-assembly to achieve low cost. The purpose is to provide high quality electronic devices.
【0004】[0004]
前述の課題を解決するために本考案では、カードエッジ形状のリード端子群を 有する回路基板Aと、横一列に並んだスルーホール群をスリット形状の穴で貫い て形成されるリード端子群を有する回路基板Bとからなり、前記回路基板Aのカ ードエッジ形状のリード端子群を前記回路基板Bのスリット形状の穴内に挿入し 前記回路基板Bのリード端子群と導通させている。 In order to solve the above-mentioned problems, the present invention has a circuit board A having a card edge-shaped lead terminal group and a lead terminal group formed by penetrating through-hole groups arranged in a horizontal row with slit-shaped holes. A circuit board B, and a card-edge-shaped lead terminal group of the circuit board A is inserted into a slit-shaped hole of the circuit board B so as to be electrically connected to the lead terminal group of the circuit board B.
【0005】 また別手段として、カードエッジ形状のリード端子群を有する回路基板Aと、 スリット形状のスルーホールを複数の穴で分割して形成されるリード端子群を有 する回路基板Cとからなり、前記回路基板Aのカードエッジ形状のリード端子群 を前記回路基板Cのスリット形状のスルーホール内に挿入し前記回路基板Cのリ ード端子群と導通させている。As another means, the circuit board A has a card-edge-shaped lead terminal group, and the circuit board C has a lead-terminal group formed by dividing a slit-shaped through hole into a plurality of holes. The card-edge-shaped lead terminal group of the circuit board A is inserted into the slit-shaped through hole of the circuit board C to be electrically connected to the lead terminal group of the circuit board C.
【0006】[0006]
以下、実施例に基づき本考案を詳細に説明する。 Hereinafter, the present invention will be described in detail based on embodiments.
【0007】 図1に本考案の第一の実施例の上面視図を、図2に図1の側面視図を、図3に 図1のa−a断面図を、図4に図1のb−b断面図を示す。図1から図4に於い て、1はレーザービームプリンタの制御基板であり、図示してないが印字制御を 行なうROM、CPU、ゲートアレイICなどが実装されている。また、2はメ モリ基板であり、図示してないがレーザビームプリンタの印字情報を記憶するた めの256k×16bit構成の40pinのSOJパッケージのDRAMが表 裏に2個づつ計4個実装されている。FIG. 1 is a top view of the first embodiment of the present invention, FIG. 2 is a side view of FIG. 1, FIG. 3 is a sectional view taken along line aa of FIG. 1, and FIG. The bb sectional drawing is shown. 1 to 4, reference numeral 1 is a control board of a laser beam printer, which is mounted with a ROM, a CPU, a gate array IC and the like, which are not shown, for controlling printing. Reference numeral 2 is a memory board, and although not shown, four 40-pin SOJ package DRAMs of 256 k × 16 bit structure for storing print information of the laser beam printer are mounted on the front and back sides, for a total of four. ing.
【0008】 制御基板1のメモリ基板2の挿入部には、横一列に2mmピッチで36個並ん だトラック形状のスルーホール群3を、幅が約1.6mmのスリット形状の穴4 で切断したいわゆる断スルーホール形状のリード端子群5が形成されている。ま た、メモリ基板2には、制御基板1のリード端子群5に対応するカードエッジ形 状のリード端子群6が表裏に36本づつ形成されており、リード端子部以外の部 分には表裏ともほぼ全面にレジスト7が施されている。なお、図示してないが、 リード端子群5および6には信号線が接続されている。In the insertion portion of the memory substrate 2 of the control substrate 1, 36 track-shaped through holes 3 arranged in a row horizontally at a pitch of 2 mm were cut by slit-shaped holes 4 having a width of about 1.6 mm. A so-called through-hole-shaped lead terminal group 5 is formed. In addition, the memory board 2 has 36 card-edge-shaped lead terminal groups 6 corresponding to the lead terminal groups 5 of the control board 1 formed on the front and back sides, respectively, and the portions other than the lead terminal portions have the front and back sides. In both cases, the resist 7 is applied on almost the entire surface. Although not shown, signal lines are connected to the lead terminal groups 5 and 6.
【0009】 メモリ基板2の制御基板1への半田付けは、メモリ基板2を制御基板1のプレ ス穴4に挿入した状態で、一般のディップ部品と同工程の半田ディップ槽を通す ことにより可能である。この場合、制御基板1のプレス穴4の幅を、メモリ基板 2のリード端子部の厚みよりもやや広く、レジストが施された部分の厚みよりも やや狭く設定することにより、半田付けの際のテーピングなどの固定手段は不要 となる。なお図1から図4には、半田は図示してない。The memory substrate 2 can be soldered to the control substrate 1 by inserting the memory substrate 2 into the press hole 4 of the control substrate 1 and passing it through a solder dip bath in the same process as a general dip component. Is. In this case, the width of the press hole 4 of the control board 1 is set to be slightly wider than the thickness of the lead terminal portion of the memory board 2 and slightly narrower than the thickness of the resist-coated portion, so that the width at the time of soldering is reduced. Fixing means such as taping is unnecessary. Note that solder is not shown in FIGS. 1 to 4.
【0010】 図5に本考案の第二の実施例の上面視図を、図6に図5のa−a断面図を、図 7に図6のb−b断面図を示す。図5から図7において、制御基板8には幅が約 1.6mm長さが約75mmのスリット形状のスルーホール9を37個のプレス 穴10で分割したリード端子群11が形成されている。この場合も、制御基板8 のスルホール9の幅を、メモリ基板2のリード端子部の厚みよりもやや広く、レ ジストが施された部分の厚みよりもやや狭く設定することにより、半田付けの際 のテーピングなどの固定手段は不要である。FIG. 5 is a top view of the second embodiment of the present invention, FIG. 6 is a sectional view taken along line aa of FIG. 5, and FIG. 7 is a sectional view taken along line bb of FIG. 5 to 7, the control board 8 is provided with a lead terminal group 11 in which a slit-shaped through hole 9 having a width of about 1.6 mm and a length of about 75 mm is divided by 37 press holes 10. In this case as well, the width of the through hole 9 of the control board 8 is set to be slightly wider than the thickness of the lead terminal portion of the memory board 2 and slightly smaller than the thickness of the portion where the resist is applied, so that the soldering is performed. No fixing means such as taping is required.
【0011】 第一および第二の実施例によれば、いわゆるSIMM(シングル インライン メモリモジュール)ソケットやコネクタまたはクリップリードなどの接続部品 を使用せずに、小型で大容量のメモリ基板2を制御基板に搭載可能である。制御 基板上に同容量のDRAMを搭載するためには、SOJパッケージの場合で約2 5mm×55mmの面積が、ZIPパッケージの場合で約8mm×110mmの 面積が必要であるが、本実施例の場合約3mm×75mmの面積で済み、制御基 板のサイズ制限が厳しい場合には非常に有利である。According to the first and second embodiments, a small-sized and large-capacity memory board 2 is used as a control board without using a connecting component such as a so-called SIMM (single in-line memory module) socket, connector, or clip lead. Can be installed on. In order to mount a DRAM of the same capacity on the control board, an area of about 25 mm × 55 mm is required for the SOJ package and an area of about 8 mm × 110 mm is required for the ZIP package. In this case, the area is about 3 mm × 75 mm, which is very advantageous when the size limitation of the control board is severe.
【0012】 しかも、メモリ基板2と制御基板の半田付けは、他のデイップ部品と同工程で でき、足の無いリード形状であるため、ソケットやクリップ端子付基板を実装す る場合よりも安価にサブアッセンブリできる。Moreover, the soldering of the memory board 2 and the control board can be performed in the same process as other dip parts, and since the lead shape has no legs, it is cheaper than mounting a socket or a board with clip terminals. Can be sub-assembled.
【0013】 なお、本実施例のようにメモリ基板2のリード端子を表裏に形成すると、片面 にだけリード端子が形成されている場合に比較して、2分の1の面積で実装する ことができ、半田付け強度も強くすることができる。When the lead terminals of the memory board 2 are formed on the front and back sides as in the present embodiment, it is possible to mount the lead terminals in a half area as compared with the case where the lead terminals are formed on only one side. Also, the soldering strength can be increased.
【0014】[0014]
以上実施例で詳細に説明したように、本考案によれば、コネクタあるいは電線 などの接続部品無しに回路基板を接続することができる。従って小型薄型の電子 機器を提供することができる。また接続部品費を省くことができ、サブアッセン ブリも容易にできるため、安価な電子機器を提供することができる。 As described in detail in the above embodiments, according to the present invention, a circuit board can be connected without connecting parts such as a connector or an electric wire. Therefore, a small and thin electronic device can be provided. Further, since the cost of connecting parts can be saved and the sub-assembly can be easily performed, an inexpensive electronic device can be provided.
【図1】本考案の回路基板の接続構造の実施例を示す上
面視図。FIG. 1 is a top view showing an embodiment of a circuit board connection structure of the present invention.
【図2】図1の側面視図。FIG. 2 is a side view of FIG.
【図3】図1のa−a断面図。FIG. 3 is a sectional view taken along the line aa in FIG.
【図4】図1のb−b断面図。FIG. 4 is a cross-sectional view taken along the line bb of FIG.
【図5】本考案の回路基板の接続構造の他の実施例を示
す上面視図。FIG. 5 is a top view showing another embodiment of the circuit board connection structure of the present invention.
【図6】図5のa−a断面図。6 is a sectional view taken along line aa of FIG.
【図7】図5のb−b断面図。7 is a cross-sectional view taken along the line bb of FIG.
1・・・制御基板 2・・・メモリ基板 3・・・スルーホール 4・・・プレス穴 5・・・断スルーホール形状のリード端子 6・・・カードエッジ形状のリード端子 7・・・レジスト 8・・・制御基板 9・・・スルーホール 10・・・プレス穴 11・・・リード端子 DESCRIPTION OF SYMBOLS 1 ... Control board 2 ... Memory board 3 ... Through hole 4 ... Press hole 5 ... Disconnection through hole lead terminal 6 ... Card edge lead terminal 7 ... Resist 8 ... Control board 9 ... Through hole 10 ... Press hole 11 ... Lead terminal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // G06F 1/18 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Office reference number FI technical display area // G06F 1/18
Claims (2)
る回路基板Aと、横一列に並んだスルーホール群をスリ
ット形状の穴で貫いて形成されるリード端子群を有する
回路基板Bとからなり、前記回路基板Aのカードエッジ
形状のリード端子群が前記回路基板Bのスリット形状の
穴内に挿入され前記回路基板Bのリード端子群と導通す
ることを特徴とする回路基板の接続構造。1. A circuit board A having a card edge-shaped lead terminal group, and a circuit board B having a lead terminal group formed by penetrating through holes arranged in a row in a row with slit-shaped holes. A circuit board connection structure, wherein a card-edge-shaped lead terminal group of the circuit board A is inserted into a slit-shaped hole of the circuit board B to be electrically connected to the lead terminal group of the circuit board B.
る回路基板Aと、スリット形状のスルーホールを複数の
穴で分割して形成されるリード端子群を有する回路基板
Cとからなり、前記回路基板Aのカードエッジ形状のリ
ード端子群が前記回路基板Cのスリット形状のスルーホ
ール内に挿入され前記回路基板Cのリード端子群と導通
することを特徴とする回路基板の接続構造。2. A circuit board A having a card edge-shaped lead terminal group and a circuit board C having a lead terminal group formed by dividing a slit-shaped through hole into a plurality of holes. A circuit board connection structure, wherein a card edge-shaped lead terminal group A is inserted into a slit-shaped through hole of the circuit board C and is electrically connected to the lead terminal group of the circuit board C.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9998891U JPH0550768U (en) | 1991-12-04 | 1991-12-04 | Circuit board connection structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9998891U JPH0550768U (en) | 1991-12-04 | 1991-12-04 | Circuit board connection structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0550768U true JPH0550768U (en) | 1993-07-02 |
Family
ID=14262032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9998891U Pending JPH0550768U (en) | 1991-12-04 | 1991-12-04 | Circuit board connection structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0550768U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100722498B1 (en) * | 2006-02-27 | 2007-05-28 | 주식회사 신창전기 | Structure for connecting pcb |
JP2011086664A (en) * | 2009-10-13 | 2011-04-28 | Autonetworks Technologies Ltd | Circuit structure and electric connection box |
-
1991
- 1991-12-04 JP JP9998891U patent/JPH0550768U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100722498B1 (en) * | 2006-02-27 | 2007-05-28 | 주식회사 신창전기 | Structure for connecting pcb |
JP2011086664A (en) * | 2009-10-13 | 2011-04-28 | Autonetworks Technologies Ltd | Circuit structure and electric connection box |
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