JPH054373Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generating circuit, and more particularly to a gate pulse generating circuit suitable for use in a time axis error signal generating circuit for a reproduced signal in a video signal reproducing apparatus.

A playback device that plays back video information recorded on a recording medium is provided with a time base collector circuit in order to accurately correct the time axis of a video playback signal. The first is a schematic block diagram of the time base error signal generating section in this time base collector circuit. The composite synchronization signal or color burst signal extracted and separated from the reproduced video signal is input to the gate circuit 1. The gate pulse generator 3 operates based on the reference signal from the reference signal generator 2 to generate a gate pulse, and the gate pulse generates a specific rising edge or rising edge of the reproduced horizontal synchronizing signal or color burst signal in the composite synchronizing signal. The downstream side is gated in the gate circuit 1. The phases of the gated reproduced horizontal synchronizing signal or reproduced color burst signal and the reference signal are compared in a comparator 4, and the output of this phase difference is used as time axis error information.

Since the gate pulse generator 3 shown in FIG. 1 generates the gate pulse from the reference signal, the following drawbacks occur. In other words, when the time axis error of the reproduced signal becomes large to some extent (in the case of a video disk player, for a while after the so-called spindle servo is locked), the generation timing of the reproduced horizontal synchronizing signal or the specific rising edge or The falling timing is outside the pulse width of the gate pulse, and as a result, the reproduced horizontal synchronization signal is no longer gated in the gate circuit 1, which causes the phenomenon that the time axis and error information are not output and the servo is disconnected. There is.

Therefore, an object of the present invention is to provide a gate pulse generation circuit that can generate a gate pulse that can gate a reproduced horizontal synchronizing signal even if the time axis error is large to some extent.

The gate pulse generation circuit according to the present invention includes means for generating a ramp signal having a predetermined period (for example, horizontal synchronization signal period), sample and hold means for sampling and holding the ramp signal;
means for level-shifting the sample-and-hold output by a predetermined value to generate first and second shift voltages; and generating a gate pulse when the ramp signal level is within the range of the first and second shift voltages; The invention is characterized in that it includes a means for doing so.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention.
0 is a circuit that generates a sawtooth wave (slope wave) having a constant period (for example, horizontal synchronization signal period),
A capacitor C ₁ is used to generate the slope wave, a current source I ₀ is used to charge the capacitor with a constant current, a switch S ₁ is used to control on/off of the constant current charge, and a switch S 1 is used to control the discharge of the capacitor C ₁ . It consists of a reset switch _S2 . To control the switch _S1 , a sample pulse C is applied as a control signal to the switch _S1 via an inverter _I1 , and a reset pulse B is applied to the reset switch _S2 . It is assumed that the generation timing, that is, the phase of this sample pulse C indicates a specific rising or falling timing phase of the color burst signal of the reproduced video signal, and that the existence period switch _S1 of this sample pulse C is controlled to be OFF. Constant current charging to capacitor _C1 is temporarily stopped. In addition, the charging charge of capacitor _C1 is 1H (1
It is reset by a reset pulse B having a period (horizontal scanning period).

11 is a sample and hold circuit, in which the output D of the capacitor _C1 is applied to the hold capacitor _C2 via the sampling switch _S3 ,
This switch _S3 is on/off controlled by the sample pulse C. Hold output V ₀ is buffer I ₂ and
It is input to a gate pulse generation circuit ₁₂ having a window comparator configuration via an LPF (low pass filter) F1.

The gate pulse generation circuit 12 is a level comparator _M1
and _M2 , and the slope signal D is used as the input to be compared. As a comparison voltage,
A voltage V ₀ obtained by shifting the LPF output V ₀ of the sample and hold circuit 11 in the negative direction by predetermined levels Va and Vb.
−Va, V ₀ −Vb are used. The output of this window comparator becomes the gate pulse E.

FIG. 3 is an operational waveform diagram of each part of the circuit of FIG. 2, and FIGS. B to E respectively show waveforms of signals B to E of each part of the circuit of FIG. 2, respectively. Note that A is a reference signal having a 1H period, and F is an HD (H drive) pulse waveform from which the equivalent pulse has been removed.

A reset pulse that rises in response to the rising timing of the reference signal A and has a pulse width shorter than 1/2H is obtained as shown in B, and a sample pulse that includes phase information of a reproduced video signal (not shown) is obtained as shown in C. It is assumed that this has been obtained. Therefore, the output waveform of the ramp signal generating circuit 10 is as shown in D.
Therefore, the LPF in the sample and hold circuit 11
The average level V ₀ is the level indicated by the dotted line in Figure D. This average level V ₀ is level-shifted by −Va and −Vb and is output to the window comparator 12.
Therefore, only when the level of the ramp signal D is between the two levels V ₀ -Va and V ₀ -Vb shown by the dashed line in Fig. D, a pulse as shown in Fig. E is output. will be done. Therefore, by appropriately selecting the values and polarities of the level shift voltages Va and Vb, it is possible to generate a gate pulse in an interval corresponding to a level range that is shifted by a predetermined value from the sample hold level _V0 . It becomes possible. As a result, if this gate pulse is used as a pulse to gate the reproduction horizontal synchronization signal to generate a time axis error in the reproduction video signal, as explained earlier, even if the phase of the reproduction video signal at that time is large to some extent, By selecting the generation position of this gate pulse, the reproduced horizontal synchronizing signal is gated, and the conventional problems can be solved.

Incidentally, as shown in Figure 3E, sharp pulses are output even in the steep falling portion of the sloped signal, but in a device that reproduces video information, the equivalent pulse is removed after performing the sync gate. In order to obtain the HD pulse shown in F, this HD
Even if such a sharp pulse as described above is generated in the high level portion of the pulse (greater than 1/2H), this pulse is masked by the equivalent pulse removal circuit, so there is no problem.

FIG. 4 is a circuit diagram showing an example of application of the present invention, in which the circuit shown in FIG. 2 is used together with a time axis error generation circuit for a reproduced video signal, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. has been done. A further window comparator 13 of the circuit of FIG. 2 is provided and consists of level comparators M ₃ and M ₄ . The compared input of this comparator is the slope signal D, and the comparison level is V ₀ +V ₁ , V ₀ − centered on the LPF output V ₀ of the sample-and-hold circuit 11.
A level called V ₂ is used. To generate this comparison level, a series circuit of variable resistors VR ₁ and VR ₂ is provided, and V ₀ is supplied to this series connection point.

The output E of the window comparator 13 serves as a gate signal for the diode gate 14, and serves as an on/off gate for the sample pulse C. For that purpose, the sample _pulse C
However, the output E of the window comparator 13 is also connected to the sampling switch via the diode _D2 .
It is designed to be output as the control signal F of _S3 . The other circuit configurations are the same as those shown in FIG. 2, and their explanation will be omitted.

FIG. 5 is a diagram showing operating waveforms of the circuit in FIG. 4, and A to D are equivalent waveforms to A to D in FIG. 3,
E and F are respectively second window comparators 13
and the control signal waveform of sampling switch _S3 . Now, if the sample pulse C containing the phase information of the reproduced video signal has a large phase shift as shown in the second part of FIG. Due to the shift, diode gate 14 is turned off and sample pulse C is not transmitted to sampling switch _S3 . Therefore, at this time, the sample and hold circuit 11 prohibits the sampling operation and outputs the previous sample value while holding it as it is.

In other words, if the sample value fluctuates significantly compared to the previous sample value, this is incorrect phase information due to dropouts or other noise, and the incorrect information in this case will automatically not be sampled. From, the output V ₀ of LPF F ₁ in Fig. 4
If this is used as a time axis error signal of a reproduced video signal, an error output generation circuit that is resistant to dropouts, noise, etc. can be obtained.

When a time axis error signal generation circuit consisting of such circuits 10, 11, 13 and 14 and the gate pulse generation circuit shown in FIG. 2 are provided, as shown in FIG. Since it can be shared, the circuit can be simplified. Furthermore, the gate pulse that is the output of the window comparator 12 may be used as a gate signal for generating the sample pulse C of the time axis error signal generation circuit for the reproduced video signal.

As mentioned above, according to the present invention, since the gate pulse is generated based on the sample and hold output, it is possible to always generate the gate pulse at a desired portion, thereby eliminating, for example, a time axis error in a reproduced video signal. It is preferable to use it as a gate pulse of a reproduced horizontal synchronizing signal for generation. However, it may be used as a gate pulse for extracting a color burst, or a general gate pulse for extracting only a specific portion of the signal may be used.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of a time axis error generating section of a reproduced video signal in a reproducing device, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is an operation waveform diagram of each part of the circuit of Fig. 2, FIG. 4 is a circuit diagram of an example of application of the present invention, and FIG. 5 is a waveform diagram showing the operation of each part of the circuit of FIG. Explanation of symbols of main parts, 10... Slope signal generation circuit, 11... Sample hold circuit, 12...
...window comparator.

Claims (1)

[Claims for Utility Model Registration] A gate pulse generation circuit that generates a gate pulse that triggers a gate for extracting a horizontal synchronization signal from a read composite video signal in a time axis correction circuit of a recording medium performance device, comprising: sample and hold means for sampling and holding the sloped signal at a timing corresponding to a horizontal synchronization signal included in the read composite video signal; means for generating first and second shift voltages by shifting the level by a value; and means for generating the gate pulse only while the ramped signal level is within the range of the first and second shift voltages. A gate pulse generation circuit comprising: