JPH054196U - Display control device - Google Patents

Abstract

(57) [Abstract] [Purpose] When the number of characters input per line, which is more than the number of basic display characters set in advance as a display device, is selected, the characters exceeding the basic display characters can be displayed collectively. A display controller is provided. [Structure] In addition to the basic clock that is the basis of the horizontal / vertical synchronization signals, a second clock source corresponding to the number of display characters in one line is provided, and the video system The basic clock can be selected. [Effect] With regard to the characters in the same line, all the entered characters can be displayed together, so that you can view the entered text without having to perform troublesome cursor operations during input, and obtain a device with good operability. You can

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a control device for a raster scan type CRT display.

[0002]

[Prior Art]

 FIG. 4 is a diagram showing a main part of the configuration of a conventional display control device. In the figure, 1 is a clock source 1 or 2 for supplying a basic timing of the control device, and horizontal / vertical synchronizing signals are generated based on this clock. A sync signal generation circuit, 3 is an RFM (refresh memory) for storing display data, 4 is a display timing generation circuit for generating access timing of RFM3 and control timing of display data, and 5 is read from RFM3. This is a video signal generation circuit that processes the display data and the display attributes described above according to the output timing from the display timing generation circuit 4 to generate a video signal. FIG. 5 is a diagram for explaining the operation of the conventional display control device. In the figure, 6 is a display screen a, 7 is a display screen b, and 8 is an internal structure of the RFM 3 corresponding to the above display screen. FIG. 6 is a diagram showing a sync signal and a basic clock of a video signal of a conventional display control device. In the figure, 9 is a basic clock of a synchronous signal and 10 is a basic clock of a video signal.

Next, the operation will be described. Generally, the display screen of a CRT display is displayed in a fixed format, for example, 40 characters horizontally × 25 lines vertically, but in applications such as personal computers and word processors, the number of characters for one page is 40 characters × 25 lines. I have something to overcome. Here, for convenience of description, the operation when inputting characters of 60 characters × 40 lines will be described. When the mode of 60 characters × 40 lines is selected by the operator's operation, the CPU (not shown) secures the memory area shown in 8 of FIG. 5 inside the RFM3, and the characters input from the keyboard are specified by the RFM3. Write to the address of. The display timing generation circuit 4 accesses part a of the RFM 3 and displays the display screen a6. When the cursor position exceeds 40 characters in the horizontal direction, the CPU instructs the display timing generation circuit 4 to access part b, and as a result, the display position b is shifted to the right and the display screen b is displayed. In this case, since the conventional display device has only the clock source 1 as the clock source, the basic clock 9 of the synchronizing signal and the basic clock 10 of the video signal are the same as shown in FIG.

[0004]

[Problems to be solved by the device]

 Since the conventional display control device is configured as described above, even if an attempt is made to input and display 40 or more characters per line, only 40 of those characters will be displayed. When inputting, it is necessary to move the cursor to the right or left and switch the display screen to a or b, which is not only difficult to read but also troublesome and time-consuming.

The present invention has been made to solve the above-mentioned problems, and it is not necessary to operate the cursor to switch the display screen to read back the phrase being input, and to display one line at a time 60 The purpose is to obtain a display control device capable of displaying characters.

[0006]

[Means for Solving the Problems]

 The display control device according to the present invention has a second clock source corresponding to the number of display characters in one line in addition to the basic clock which is the basis of the horizontal and vertical synchronizing signals, and one of these is supplied to the video system at the instruction of the CPU. It is configured to be selectively used as the basic clock of.

[0007]

[Action]

 The display control device according to the present invention uses the second clock for the video system to generate the timing for displaying 60 characters in one line to access the RFM and display the screen.

[0008]

【Example】

 Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a main part of the configuration of a display controller according to the present invention. In the figure, 1 is a clock source for supplying the basic timing of the controller, and 2 is a horizontal / vertical synchronizing signal based on this clock. A synchronizing signal generating circuit for generating, 3 is an RFM for storing display data and the like, 11 is a second clock source which constitutes an essential part of the present invention, 12 is a register for storing a clock selection command from a CPU, and 13 is a register 12 A clock selection circuit for selecting and outputting either the first clock source 1 or the second clock source 11 based on the instruction of, and a display timing generation circuit 14 for generating access timing of RFM3 and control timing of display data, Reference numeral 5 processes the display data and display attributes read from the RFM3 in accordance with the output timing from the display timing generation circuit 14. A video signal generation circuit for generating a Deo signal. FIG. 2 is a diagram for explaining the operation of the display control device according to the present invention. In the figure, 6 is a display screen a, 15 is a display screen c, and 8 is an internal structure of the RFM 3 corresponding to the display screen. FIG. 3 is a diagram showing the basic clocks of the synchronizing signal and the video signal of the display controller according to the present invention. In the figure, 9 is the basic clock of the synchronizing signal and 16 is the basic clock of the video signal.

Next, the operation will be described. First, when the number of characters that can be displayed on the CRT display is 40 or less, when the CPU instructs the register 12 to select the clock source 1, the clock selection circuit 13 selects the clock source 1. The display timing generation circuit 14 accesses the part a of the RFM 3 based on the selected clock and displays the display screen a 6. In this case, the basic clocks of the synchronizing signal and the video signal are 9 and 16a, respectively, which are the same.

Next, the operation when inputting characters of 60 characters × 40 lines will be described. When the mode of 60 characters × 40 lines is selected by the operator's operation, the CPU instructs the register 12 to select the second clock source 11, and the clock selection circuit 13 selects the clock source 11. The display timing generation circuit 14 accesses the c section of the RFM3 based on the selected clock and displays the display screen c15. The basic clock of the synchronizing signal in this case is 9 as described above, and the basic clock 16c of the video signal is shorter than 16a for one dot in order to display 60 characters on the display screen. That is, in the display in the horizontal 60-character mode, the width is narrower than that in the mode of 40 characters or less.

It should be noted that although the above embodiment has described the case where there are two clock sources, it is also possible to select N modes in accordance with the number of horizontal display characters. Also, although the clock sources are shown as separate ones, a clock with a higher frequency may be divided and created. Furthermore, I explained that the clock switching is triggered by the mode setting of the CPU, but when the number of characters is input and the specified number of characters is exceeded, the setting will be changed to the mode above it. It may be configured as.

[0012]

[Effect of the device]

 As described above, according to this invention, the clock corresponding to the number of displayed characters is selected and the video signal is generated based on the selected clock, so that the input text can be input without troublesome cursor operation. The whole can be displayed on the screen at the same time, and a device with good operability can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the display control device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a sync signal and a basic clock of a video signal of a display controller according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional display control device.

FIG. 5 is a diagram illustrating an operation of a conventional display control device.

FIG. 6 is a diagram showing a basic clock of a synchronizing signal and a video signal of a conventional display control device.

[Explanation of symbols]

 1 First Clock Source 11 Second Clock Source 12 Register 13 Clock Selection Circuit 14 Display Timing Generation Circuit

Claims (1)

[Claims for utility model registration] 1. A first clock source that is the basis of horizontal / vertical synchronization signals, a plurality of second clock sources that is the basis of video signals, and a clock selection instruction from the CPU. , A selection circuit for selecting the first or second clock according to the instruction of this register, and an access timing of the RFM (refresh memory) and a display timing for generating display data based on this clock. A display control device comprising a display timing generation circuit for generating.