JPH0541483A - Integrated circuit - Google Patents

Abstract

PURPOSE:To trim both of a VR circuit and detection circuit without increasing the number of pads for trimming even when different reference voltages are used for the VR and detection circuits by performing the trimming by detecting the output voltage of the VR circuit with the detection circuit. CONSTITUTION:A switch element is turned on by raising the potential of a test symbol TST to its highest level and the output voltage VRG of a VR circuit 2 is changed by changing outputs B0-B7 of a decoder circuit 52 by inputting a clock signal CLK to the circuit 52 from a clock terminal 9. Upon detecting that the output voltage VRG of the circuit 2 reaches its highest level, a detection circuit 31 terminates the changes of the outputs B0-B7 of the circuit 52 by sending a trimming terminating signal TRM to the circuit 52. The data are then stored in the circuit 52 and the voltage detected by the circuit 31 is always outputted from the circuit 52. Therefore, the chip area of this integrated circuit can be reduced, because no pad for trimming is required.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to integrated circuits, and more particularly to
The present invention relates to an integrated circuit including a power supply voltage detection circuit and a constant voltage power supply circuit.

[0002]

2. Description of the Related Art Generally, when a power supply voltage detection circuit (hereinafter referred to as a detection circuit) and a constant voltage power supply circuit (hereinafter referred to as a VR circuit) are provided on a chip of one integrated circuit, these two circuits are When the temperature characteristics of the reference voltage in each of them may be the same, the same one reference voltage can be commonly used for the two circuits. And because of this, 2
When trimming each of the two circuits, two trimmings can be performed simultaneously. The circuit configuration in such a case is shown in FIGS. 3 and 4.

Referring to FIGS. 3 and 4, a circuit block 4 including a VR circuit 2 and a detection circuit 30 and a decoder circuit 50 are provided on a chip 1 of an integrated circuit. In such a structure, when trimming is performed under the above conditions, the trimming pads R _{1 to} R
_The signal is input to ₃ and decoded by the decoder circuit 50.
Then, by inputting the outputs A _{0 to} A ₇ to the trimming circuit 60, the detection voltage BLD of the detection circuit 30 and the output voltage VRG of the VR circuit 2 are adjusted to a predetermined voltage.

In this case, the output A ₀ of the decoder circuit 50
A ₇ is commonly input to the gates of the detection circuit trimming NMOS transistors T _{1 to} T _{8 and} the gates of the VR circuit trimming NMOS transistors T _{9 to} T _{16 in} the trimming circuit 60. Then, the two output voltages V _R and V _B from the trimming circuit 60 are input to the amplifier 70 for the VR circuit and the amplifier 71 for the detection circuit, and each of them is compared with the common reference voltage V _ref . , Detection voltage BLD of detection circuit 30 and VR circuit 2
The output voltage VRG is trimmed at the same time.

On the other hand, when the detection circuit and the VR circuit use reference voltages having different temperature characteristics, FIG.
As shown in FIGS. 6A and 6B, each circuit is provided with an individual decoder circuit, and each circuit is trimmed independently.

Referring to FIGS. 5, 6A and 6B, in this case, the trimming pads R _{1 to} R _{3 are used.}
A signal is input to and is decoded by the decoder circuit 50. The outputs A _{0 to} A ₇ of the decoder circuit 50 are the NMOS transistors T1 of the detection circuit trimming circuit 61. Is input to the gate of the ~T _8. Then, the output V _B from the trimming circuit 61 is input to the amplifier 71 for the detection circuit and the reference voltage V
The detection voltage BLD of the detection circuit 30 is trimmed by being compared with _ref1 .

On the other hand, a signal for trimming is also input to the trimming pads N _{1 to} N ₃ , and the decoder circuit 51
Is decoded with. Outputs B _{0 to} B ₇ of the decoder circuit 51
Is an NMOS forming the VR circuit trimming circuit 62.
It is input to the gates of the transistors T _{9 to} T ₁₆ . The output voltage V _R from the trimming circuit 62 is input to the VR circuit amplifier 70 and compared with the reference voltage V _ref2 to trim the output voltage VRG of the VR circuit 2.

[0008]

As described above, conventionally, when reference voltages having different temperature characteristics are used in the detection circuit 30 and the VR circuit 2, a decoder circuit is provided for each circuit, Trimming is done independently. Focusing on the number of trimming pads required in this case, as shown in FIG. 5, a common reference voltage is required, which is twice as many as in the case of one reference voltage.

When the number of trimming pads increases in this way, the area of the chip as an integrated circuit increases. The description will be given below.

The trimming pad electrically serves as a portion for receiving a signal from the outside on the chip. On the other hand, when the integrated circuit is viewed as a structure, the lead of the package and the chip are connected to each other. For connecting with wires,
It is a bonding pad. Therefore, its shape
The size is generally a large rectangle with one side of about 100 to 200 μm so that bonding can be performed reliably.

On the other hand, looking at the area occupied by the decoder circuit, the trimming circuit, and the amplifier, the MOS transistor has been promoted in recent years as the speed, power consumption, and density of various integrated circuits have been increased. Since circuit elements such as resistors and resistors, wiring, and the like are extremely miniaturized, an area for one or two trimming pads is only required.

That is, generally, in this kind of integrated circuit, the area of the chip is almost determined by the number of bonding pads. Therefore, in the integrated circuit including the conventional detection circuit 30 and the VR circuit 2 shown in FIGS. 5, 6A and 6B, the chip area increases and the number of leads also increases. This is extremely inconvenient in a situation where miniaturization and high-density mounting of electronic devices are required.

The present invention has been made in view of the problems of the conventional integrated circuit as described above, and includes a detection circuit and a VR.
An object of the present invention is to provide a means capable of trimming both circuits without increasing the number of trimming pads even when different reference voltages are used for the circuits.

[0014]

According to the integrated circuit of the present invention, a voltage of a power supply is determined by a first decoder circuit for decoding an external input to a trimming pad and an output of the first decoder circuit. Power supply voltage detection circuit that is trimmed so as to generate an output when the value reaches the second value, a second decoder circuit that is decoded by a clock signal from the power supply voltage detection circuit and the output external, and a second decoder circuit. A constant voltage power supply circuit that is trimmed so that the output voltage is set to a predetermined voltage by an output of the test signal from the outside by a trimming of the power supply voltage detection circuit and the trimming of the constant voltage power supply circuit. It is characterized in that it is switched by.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, the circuit shown in FIG. 6B is used as the VR circuit 2 as in the conventional case, and the circuit shown in FIG. 2 is used as the detection circuit 31.

First, the detection circuit 31 shown in FIG. 2 will be described. Referring to FIG. 2, the detection circuit 31 includes a trimming circuit 63 used for detecting a power supply voltage.
And a trimming circuit 64 for detecting the output voltage of the VR circuit 2 are provided. Now, at the time of detecting the power supply voltage, the NMOS transistor N ₁
Is turned on and the output A _{3 of} the decoder circuit 50 (shown in FIG. 1) is trimmed with the maximum potential (hereinafter, this potential is referred to as V _DD ), the NMOS transistor N ₂ is detected when the VR circuit output voltage is detected. When turned on,
The resistance value of the trimming circuit 64 is set so that the trimming can be performed when the output A ₃ = V _DD .

Next, the operation of this embodiment will be described with reference to FIG. Referring to FIG. 1, in the present embodiment, first, the potential of the test signal TST input to the test terminal 8 is set to the minimum potential (hereinafter, this potential is referred to as V _SS ) and the switch element SW.
Turn ₁ on. Then, the trimming pad R ₁
Signal from R ₃ and output A _{0 of the} decoder circuit 50
A power supply voltage detection voltage BLD of the detection circuit 31 is set to a predetermined voltage at A ₇ . At this time, the detection circuit 31 in FIG.
, The NMOS transistor N ₁ is on.

Next, the potential of the test signal TST is set to V _DD to turn on the switch element SW ₂ , the clock signal CLK is input from the clock terminal 9 to the decoder circuit 52, and the outputs B _{0 to} B ₇ of the decoder circuit 52 are input. Is changed to change the output voltage VRG of the VR circuit 2.
Then, the detection circuit 31 detects whether or not this output voltage has reached a predetermined voltage.

The detection circuit 31 outputs the output voltage V of the VR circuit 2.
When it is detected that RG has reached a predetermined voltage, the trimming end signal TRM is sent to the decoder circuit 52 to end the change of the outputs B _{0 to} B ₇ of the decoder circuit 52. In this embodiment, the data at this time is stored in the decoder circuit 52, and the voltage detected by the detection circuit 31 is always output from the VR circuit 2.

[0020]

As described above, in the integrated circuit of the present invention, the output voltage of the VR circuit is detected by the detection circuit and trimming is performed. Therefore, according to the present invention, VR
Even when different reference voltages are used for the circuit and the detection circuit, the trimming pad for trimming the VR circuit can be omitted and the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a detection circuit in the block diagram shown in FIG.

FIG. 3 is a block diagram of an example of a conventional integrated circuit.

4 is a circuit diagram of a detection circuit and a VR circuit in the block diagram shown in FIG.

FIG. 5 is a block diagram of another example of a conventional integrated circuit.

6A is a circuit diagram of a detection circuit in the block diagram shown in FIG. FIG. 5B is a circuit diagram of the VR circuit in the block diagram shown in FIG. 1 shown in FIG.

[Explanation of symbols]

 1 chip 2 VR circuit 30, 31 detection circuit 4 circuit block 50, 51, 52 decoder circuit 60, 61, 62, 63, 64 trimming circuit 70, 71 amplifier 8 test terminal 9 clock terminal

Claims (1)

[Claims] 1. A first decoder circuit for decoding an external input to a trimming pad, and an output of the first decoder circuit to generate an output when a voltage of a power supply reaches a predetermined value. A power supply voltage detection circuit that is trimmed, a second decoder circuit that is decoded by the output of the power supply voltage detection circuit and an external clock signal, and an output voltage that is a predetermined voltage by the output of the second decoder circuit A constant voltage power supply circuit that is trimmed so that the trimming of the power supply voltage detection circuit and the trimming of the constant voltage power supply circuit are switched by a test signal from the outside. Integrated circuit.