JPH0541408A - Bonding method - Google Patents
Bonding methodInfo
- Publication number
- JPH0541408A JPH0541408A JP22100791A JP22100791A JPH0541408A JP H0541408 A JPH0541408 A JP H0541408A JP 22100791 A JP22100791 A JP 22100791A JP 22100791 A JP22100791 A JP 22100791A JP H0541408 A JPH0541408 A JP H0541408A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- curing
- circuit board
- semiconductor chip
- force
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップ等の電子
部品の実装に関し、特にその接着方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting of electronic parts such as semiconductor chips, and more particularly to a method of adhering them.
【０００２】[0002]
【従来の技術】ＳｉやＧａＡｓを材料に用いた半導体チ
ップを回路基板に実装する方法として、フリップチップ
法がある。これは、バンプ（突起電極）が形成された半
導体チップをフェイスダウン方式で、回路基板に接続す
る方法である。2. Description of the Related Art A flip chip method is known as a method for mounting a semiconductor chip using Si or GaAs as a material on a circuit board. This is a method of connecting a semiconductor chip having bumps (projection electrodes) to a circuit board by a face-down method.
【０００３】図１に、従来例を示す。同図は、回路基板
10に半導体チップ11を接続した状態の断面図である。こ
こで、12は半導体チップ11上にハンダや金などで形成さ
れたバンプ電極であり、回路基板10上のＩＴＯ（Indium
Tin Oxide）膜などで形成された配線パターン13と接続
される。14は半導体チップ11と回路基板10を固定するた
めの接着剤で、樹脂などが使用される。この樹脂14は、
通常、紫外線などで硬化する光硬化樹脂で、回路基板10
が液晶ガラスなどのように透明であるような場合に、回
路基板10の底面（紙面下方）から、例えば紫外線を照射
し、樹脂14を硬化させることによって、半導体チップ11
と回路基板10を固定するようにしている。FIG. 1 shows a conventional example. The figure shows a circuit board
FIG. 3 is a cross-sectional view showing a state in which a semiconductor chip 11 is connected to 10. Here, 12 is a bump electrode formed of solder or gold on the semiconductor chip 11, and is an ITO (Indium) on the circuit board 10.
It is connected to the wiring pattern 13 formed of a tin oxide film or the like. Reference numeral 14 denotes an adhesive for fixing the semiconductor chip 11 and the circuit board 10, and resin or the like is used. This resin 14 is
A circuit board 10 that is usually a photo-curing resin that cures with ultraviolet rays.
When the semiconductor chip 11 is transparent such as liquid crystal glass, the semiconductor chip 11 is cured by irradiating, for example, ultraviolet rays from the bottom surface of the circuit board 10 (below the paper surface) to cure the resin 14.
The circuit board 10 is fixed.
【０００４】上述の接着方法の手順は、まず回路基板10
上に光硬化樹脂14を塗布し、続いて半導体チップ11をフ
ェイスダウンで位置合わせを行ないながら配置する。紫
外線などの照射によって光硬化樹脂14を硬化させた後、
加熱により未硬化分の硬化を行なっている。The procedure of the above-mentioned bonding method is as follows.
A photo-curable resin 14 is applied on the upper surface of the semiconductor chip 11, and the semiconductor chip 11 is subsequently arranged face down. After curing the photocurable resin 14 by irradiation with ultraviolet rays,
The uncured portion is cured by heating.
【０００５】[0005]
【発明が解決しようとする課題】上述のような方法で
は、光照射と加熱の工程を有しているが、いずれの工程
も光硬化樹脂14の接着力と収縮力を同時に発生させるた
め、接着力と収縮力の発生の順序やその強度を希望する
値に制御することができなかった。本発明は、このよう
な問題を解決し、接着力と収縮力を別々に制御すること
ができる接着方法を提供することを目的とする。The method as described above has the steps of light irradiation and heating, but since both steps simultaneously generate the adhesive force and the contracting force of the photocurable resin 14, the adhesion It was not possible to control the order of generation of force and contraction force and its strength to desired values. It is an object of the present invention to solve such a problem and to provide an adhesive method capable of separately controlling the adhesive force and the contracting force.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明の接着方法は、少なくとも２物体を接着する
方法において、硬化の機能と収縮の機能を有する接着剤
を、前記２物体の間に施す工程と、しかる後、前記接着
剤を硬化させる第１の工程と、前記接着剤を収縮させる
第２の工程と、から成る。そして、前記第１の工程は加
熱または光照射の工程であり、前記第２の工程は加熱の
工程である。In order to achieve the above object, the bonding method of the present invention is a method for bonding at least two objects, wherein an adhesive having a curing function and a shrinking function is applied between the two objects. And a second step of curing the adhesive, and then a second step of shrinking the adhesive. And the said 1st process is a process of heating or light irradiation, and the said 2nd process is a process of heating.
【０００７】[0007]
【作用】このようにすると、半導体チップと回路基板の
実装の際、接着力と収縮力の制御が別々に行なえるた
め、実装の最適条件の抽出が容易になり、信頼性の向上
が図れる。In this way, since the adhesive force and the contracting force can be controlled separately when the semiconductor chip and the circuit board are mounted, the optimum mounting condition can be easily extracted and the reliability can be improved.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面を参照しつつ、
説明する。図２に、本発明を実施した実装装置及び該実
装装置の処理を示す。同図において、処理は左から右に
いくにつれて進行していく。まず、（ａ）で回路基板10
がライン上に搬入される。（ｂ）では樹脂塗布用ディス
ペンサ20により、回路基板10上の所定部分に紫外線硬化
樹脂中に熱収縮樹脂を含有した接着剤21が塗布される。
（ｃ）では半導体チップ11が回路基板10上に供給される
とともに、回路基板10と半導体チップ11の接続を考慮し
た位置合わせが行なわれる。（ｄ）では紫外線照射手段
22により紫外線の照射が行なわれ、ここで接着剤21の硬
化が開始される。（ｄ）における紫外線の照射は、完全
には行なわれず仮接着にとどめるよう、例えば、照射時
間などを制御するようにしている。これは次の収縮の工
程で接着剤21の収縮を行なう際、硬化が完了している
と、収縮により回路基板10と半導体チップ11が分離して
しまうことがあるためである。これを防ぐため、（ｄ）
の工程では、接着剤21がゲル状になった時点で、紫外線
の照射を停止するようにしている。（ｅ）では加熱連続
炉23中を、回路基板10が進み、この間に接着剤21の収縮
が行なわれる。（ｆ）では接着剤21の硬化を完了させる
ため、再度紫外線照射手段24（22と同様の手段）により
紫外線の照射が行なわれる。（ｇ）では硬化、収縮とも
に完了した、半導体チップ11が実装された回路基板10が
ラインから搬出される。但し、上述の処理で、（ｄ）と
（ｆ）のように硬化工程を分けなくても分離等の問題が
ない場合は（ｆ）は省略して（ｄ）で硬化を完了させて
もよい。また、条件によっては、（ｄ）を省略して
（ｅ）で収縮後に（ｆ）のみで硬化を行なうという工程
にしてもよい。Embodiments of the present invention will now be described with reference to the drawings.
explain. FIG. 2 shows a mounting apparatus embodying the present invention and processing of the mounting apparatus. In the figure, the process progresses from left to right. First, in (a), the circuit board 10
Are loaded onto the line. In (b), the adhesive 21 containing the heat-shrinkable resin in the ultraviolet curable resin is applied to a predetermined portion on the circuit board 10 by the resin application dispenser 20.
In (c), the semiconductor chip 11 is supplied onto the circuit board 10, and the alignment is performed in consideration of the connection between the circuit board 10 and the semiconductor chip 11. In (d), ultraviolet irradiation means
Irradiation of ultraviolet rays is performed by 22, and the curing of the adhesive 21 is started here. The irradiation of the ultraviolet rays in (d) is not completely performed, but is temporarily adhered, for example, the irradiation time is controlled. This is because when the adhesive 21 is shrunk in the next shrinking step, if the curing is completed, the circuit board 10 and the semiconductor chip 11 may be separated due to the shrinkage. To prevent this, (d)
In the step (2), the irradiation of the ultraviolet rays is stopped when the adhesive 21 becomes a gel. In (e), the circuit board 10 advances through the heating continuous furnace 23, and the adhesive 21 shrinks during this period. In (f), in order to complete the curing of the adhesive 21, the ultraviolet irradiation is again performed by the ultraviolet irradiation means 24 (means similar to 22). In (g), the circuit board 10 on which the semiconductor chip 11 is mounted, which has been cured and contracted, is unloaded from the line. However, in the above process, if there is no problem such as separation even if the curing process is not divided like (d) and (f), (f) may be omitted and curing may be completed in (d). .. In addition, depending on the conditions, (d) may be omitted and curing may be performed only in (f) after shrinking in (e).
【０００９】図３に、図２に示した接着方法を用いて、
回路基板10と半導体チップ11の接続を行なった場合の実
装構造を示す。前記接着剤21を使用する場合、まず紫外
線照射により接着剤21を硬化させることによって、回路
基板10と半導体チップ11を接着する。その後、熱収縮樹
脂が収縮する温度に加熱して収縮させることによって熱
収縮樹脂の体積収縮分だけ接着剤21が収縮し、それに伴
なう応力によって回路基板10の配線パターン13と半導体
チップ11のバンプ電極12が圧接される。その後、再度の
紫外線照射によって接着剤21の硬化を完了させている。
従って、図１と較べ、回路基板10上の配線パターン13と
半導体チップ11のバンプ電極12の接触の強度が違う。図
３に示す構造の方が圧接された状態であり、より強度が
大きく、実装の信頼性が向上する。In FIG. 3, using the bonding method shown in FIG.
1 shows a mounting structure when the circuit board 10 and the semiconductor chip 11 are connected. When the adhesive 21 is used, the circuit board 10 and the semiconductor chip 11 are first bonded by curing the adhesive 21 by irradiating ultraviolet rays. After that, the adhesive 21 is shrunk by the volume shrinkage of the heat-shrinkable resin by heating to a temperature at which the heat-shrinkable resin is shrunk, and the stress accompanying it shrinks the wiring pattern 13 of the circuit board 10 and the semiconductor chip 11. The bump electrode 12 is pressed. After that, the curing of the adhesive 21 is completed by irradiating the ultraviolet ray again.
Therefore, compared with FIG. 1, the contact strength between the wiring pattern 13 on the circuit board 10 and the bump electrode 12 of the semiconductor chip 11 is different. The structure shown in FIG. 3 is in a state of being pressure-welded, has higher strength, and improves reliability of mounting.
【００１０】図２においては、紫外線硬化樹脂に熱収縮
樹脂を含有した接着剤を使用していたので、紫外線照射
の工程が設けられているが、熱硬化樹脂に熱収縮樹脂を
含有したタイプの接着剤を使用する場合は、紫外線照射
の工程（（ｄ）及び（ｆ））を加熱工程にすればよい。
硬化、収縮いずれも加熱により行なうタイプの接着剤
は、硬化が開始する温度と収縮が開始する温度に差をつ
けることで、硬化と収縮を別々に行なうことができる。
この場合も、硬化のための加熱工程の区別化や収縮工程
との順序については、各々の樹脂の条件によって変更可
能である。In FIG. 2, since an adhesive containing a heat-shrinkable resin in the ultraviolet-curable resin is used, a step of irradiating the ultraviolet rays is provided. When an adhesive is used, the ultraviolet irradiation steps ((d) and (f)) may be heating steps.
In the case of an adhesive in which both curing and shrinkage are performed by heating, the curing and the shrinkage can be performed separately by making a difference between the temperature at which the cure starts and the temperature at which the shrinkage starts.
Also in this case, the distinction of the heating process for curing and the order of the shrinking process can be changed depending on the conditions of each resin.
【００１１】上述の接着方法は、半導体チップに限ら
ず、容量や抵抗などの電子部品の回路基板への実装にも
応用できる。The above-described bonding method is applicable not only to semiconductor chips but also to mounting electronic components such as capacitors and resistors on circuit boards.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
半導体チップと回路基板の実装の際、硬化の機能と収縮
の機能を有する接着剤を用いて接着を行なうことで、硬
化の工程と収縮の工程を別々に制御できる。これによ
り、硬化による接着力の発生タイミング及びその強度
を、また収縮力の発生タイミング及びその強度をそれぞ
れ制御できるため、接着の最適条件の抽出及び管理、変
更が容易に行なえるようになる。従って、実装の信頼性
が向上するとともに、作業性がよくなるという長所もあ
る。As described above, according to the present invention,
When mounting the semiconductor chip and the circuit board, by using an adhesive having a curing function and a shrinking function to perform the bonding, the curing process and the shrinking process can be controlled separately. This makes it possible to control the generation timing and strength of the adhesive force due to curing, and the generation timing and strength of the contraction force, respectively, so that it is possible to easily extract, manage, and change the optimum bonding condition. Therefore, there are advantages that the reliability of mounting is improved and the workability is improved.
【図１】 従来の実装構造を説明するための図。FIG. 1 is a diagram for explaining a conventional mounting structure.
【図２】 本発明を実施した接着方法を示す図。FIG. 2 is a diagram showing a bonding method embodying the present invention.
【図３】 本発明の接着方法を実施した実装構造を示す
図。FIG. 3 is a diagram showing a mounting structure in which the bonding method of the present invention is implemented.
10 回路基板 11 半導体チップ 12 バンプ電極 13 配線パターン 14 接着剤 20 樹脂塗布用ディスペンサ 21 接着剤 22 紫外線照射手段 23 加熱連続炉 24 紫外線照射手段 10 Circuit board 11 Semiconductor chip 12 Bump electrode 13 Wiring pattern 14 Adhesive 20 Resin application dispenser 21 Adhesive 22 Ultraviolet irradiation means 23 Heating continuous furnace 24 Ultraviolet irradiation means
Claims (2)
て、 硬化の機能と収縮の機能を有する接着剤を、前記２物体
の間に施す工程と、 しかる後、前記接着剤を硬化させる第１の工程と、 前記接着剤を収縮させる第２の工程と、 から成ることを特徴とする接着方法。1. A method for adhering at least two objects, a step of applying an adhesive having a curing function and a contracting function between the two objects, and a first step of subsequently curing the adhesive. And a second step of shrinking the adhesive, the bonding method comprising:
程であり、 前記第２の工程は加熱の工程であることを特徴とする請
求項１に記載の接着方法。2. The bonding method according to claim 1, wherein the first step is a heating or light irradiation step, and the second step is a heating step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22100791A JPH0541408A (en) | 1991-08-05 | 1991-08-05 | Bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22100791A JPH0541408A (en) | 1991-08-05 | 1991-08-05 | Bonding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541408A true JPH0541408A (en) | 1993-02-19 |
Family
ID=16760017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22100791A Pending JPH0541408A (en) | 1991-08-05 | 1991-08-05 | Bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541408A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07205133A (en) * | 1994-01-26 | 1995-08-08 | Toyota Kihan:Kk | Clamping and unclamping apparatus |
| US5777385A (en) * | 1997-03-03 | 1998-07-07 | International Business Machines Corporation | Ceramic ball grid array (CBGA) package structure having a heat spreader for integrated-circuit chips |
| US5783867A (en) * | 1995-11-06 | 1998-07-21 | Ford Motor Company | Repairable flip-chip undercoating assembly and method and material for same |
| US6018188A (en) * | 1997-03-28 | 2000-01-25 | Nec Corporation | Semiconductor device |
| JP2001298052A (en) * | 2000-02-09 | 2001-10-26 | Interuniv Micro Electronica Centrum Vzw | Method for flip-chip assembly of semiconductor device using adhesive |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170881A (en) * | 1988-11-02 | 1990-07-02 | Philips Gloeilampenfab:Nv | Method of bonding two objects with adhesive, and composite |
-
1991
- 1991-08-05 JP JP22100791A patent/JPH0541408A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170881A (en) * | 1988-11-02 | 1990-07-02 | Philips Gloeilampenfab:Nv | Method of bonding two objects with adhesive, and composite |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07205133A (en) * | 1994-01-26 | 1995-08-08 | Toyota Kihan:Kk | Clamping and unclamping apparatus |
| US5783867A (en) * | 1995-11-06 | 1998-07-21 | Ford Motor Company | Repairable flip-chip undercoating assembly and method and material for same |
| US5777385A (en) * | 1997-03-03 | 1998-07-07 | International Business Machines Corporation | Ceramic ball grid array (CBGA) package structure having a heat spreader for integrated-circuit chips |
| US6018188A (en) * | 1997-03-28 | 2000-01-25 | Nec Corporation | Semiconductor device |
| JP2001298052A (en) * | 2000-02-09 | 2001-10-26 | Interuniv Micro Electronica Centrum Vzw | Method for flip-chip assembly of semiconductor device using adhesive |
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