JPH0537378A - Time a/d conversion circuit - Google Patents

Abstract

PURPOSE:To precisely encode a pulse phase difference even when a delay time, that is, a time resolution fluctuates due to the fluctuation of a temperature or a power supply voltage, in a pulse phase difference encoding circuit using a gate delay. CONSTITUTION:A first pulse difference encoding circuit 108a inputs a pulse PA, and afterwards inputs a pulse PB after an arbitrary delay. On the other hand, a second pulse difference encoding circuit 108b inputs the pulse PA, and afterwards inputs a pulse PC after the lapse of a fixed time compensated by a crystal oscillator 103. At that time, the pulse phase difference encoding circuits 108a and 108b have plural gate delays which allow the pulse PA to pass, and the pulse phase difference is encoded corresponding to the PA passage position in the input timing of the pulse PB or PC. The time resolution of the circuit 108a and 108b fluctuates in the same way, and then a pulse phase difference DAB to be measured is defined as a relative ratio to a pulse phase difference DAC based on the stable pulse PC by an arithmetic circuit 109, so that an output Do can be obtained as an always stable value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time A / D conversion circuit for digitizing a minute time such as a phase difference between two pulse signals having an arbitrary phase relationship. And this time A
The D / D conversion circuit is an application of, for example, a measuring device that accurately measures a phase difference between two pulses to a physical amount such as pressure, or a laser radar that measures a distance from a reflected wave of a laser beam to an object. It is suitable for use in equipment.

[0002]

BACKGROUND ART For example, two pulses P _A, when it is desired to detect a phase difference between the P _B, by encoding a plurality of bits of digital signals the phase difference between the pulses, two pulses P _A and P _B It is possible to detect the deviation (phase difference) of the phase in both positive and negative directions. According to this method, by increasing the number of bits of the digital signal, it is possible to expand the detection range of the phase shift without lowering the detection accuracy.

However, the circuit scale is increased due to the increase in the number of bits.
It will expand significantly. Also, detection without changing the circuit scale
If you try to expand the range, the detection accuracy will decrease.
U Therefore, the present inventors have expanded the circuit scale and detected accuracy.
With the ability to expand the detection range without deterioration
Then, multiple delay elements (gate delays) are formed into a ring shape.
One pulse P connected and input at any timing
_AAnd the number of laps, and
Another pulse P input with the desired phase difference _BInput
Pulse P corresponding to imming_AThe orbiting position of the
Two pulses P depending on the specific position of P_A, P_B
First applied for a pulse phase difference encoding circuit that detects the phase difference of
Proposed in No. 2-15865.

According to this, since the final stage of the gate delay is fed back and the gate delay is used many times, the detection range can be expanded without increasing the circuit scale. ..

Further, since the detection accuracy (time resolution) of this circuit is determined only by the delay time of one stage of gate delay, the accuracy is not deteriorated even if the detection range is expanded, and the resolution is, for example, 1 ns or less. Can be realized.

[0006]

However, as a result of repeated experimental consideration by the present inventors, according to this, it is possible to realize a high resolution of 1 ns level with only a delay time of one stage of gate delay. However, it became clear that the gate delay time fluctuates due to fluctuations in temperature and power supply voltage. That is, the resolution slightly changes due to changes in temperature and power supply voltage.

The present invention has been made in view of this problem, and an object thereof is to stably quantify a minute time such as a pulse phase difference with high speed and high accuracy even if the detection accuracy (resolution) changes. A time A / D conversion circuit is provided.

[0008]

SUMMARY OF THE INVENTION A schematic configuration of the present invention which achieves the above object uses pulse phase difference encoding means (M1, M2) using a delay element proposed in Japanese Patent Application No. 2-15865. A stable reference pulse P _C that is not affected by fluctuations in temperature and power supply voltage and a signal pulse P to be measured in order to correct fluctuations in gate delay time due to fluctuations in temperature and power supply voltage.
It is characterized by performing relative comparison (ratio comparison) of _B times. Here, as the reference pulse P _C, for example, an oscillation pulse from a crystal oscillator can be used.

The basic circuit configuration of the present invention shown in FIG.
Three signal pulses P input at the timing shown in FIG.
_A description will be given based on _A , P _B , and P _C. The first pulse phase difference encoding means M1 detects the time difference T between the input pulses P _A and P _B.
The digital value D _AB corresponding to _AB is output, and the second pulse phase difference encoding means M2 similarly outputs the digital value D _AC corresponding to the time difference T _AC between the input pulses P _A and P _C. Here, in order to accurately measure the time difference T _AB between P _A and P _B ,
It is necessary to accurately correct the delay time of one stage of gate delay of the pulse phase difference encoding means. Therefore, the calculation means M3 performs the following correction calculation. Here, the pulse P _C is generated by a clock of, for example, a crystal oscillator that stably oscillates, and the time difference T _AC between the pulses P _A and P _C can always be regarded as an accurate value.

The delay time T _G per one stage of the gate delay in the second pulse phase difference encoding means M2 is

[0011]

## EQU1 ## T _G = T _AC / D _AC . Further, the time difference T _AB between the pulses P _A and P _B , which is the time to be measured, is the same as that of the above-mentioned M1 in the first pulse phase difference encoding means M1, so that the same delay time T _G is used for the following. Can be represented as.

[0012]

(2) T _AB = D _AB / T _G

[0013]

## EQU3 ## T _AB = (D _AB / D _AC ) T _AC , and the calculation means M3 calculates M1 and M2 based on the formula 3.
By comparing (dividing) the digital outputs from each, T _AB can be detected with the accuracy of, for example, a crystal oscillator.

That is, in the timing chart shown in FIG. 2, the input timing of the signal pulse P _B input with a phase difference with respect to the pulse P _A is taken as a relative ratio to the input timing of the reference pulse P _C , For example, when the time difference T _AC between the pulses P _A and P _{C is} fixed as 1000 ns as a reference time and the input timing of the pulse P _B is 500 ns after P _A (P _B1
(At input) is detected as being 50% of the pulse P _C , and 35% at 350 ns (when P _{B2 is} input).
Will be detected as.

Next, it will be explained with reference to specific numerical values that the delay time per one stage of gate delay can be corrected by this configuration when it changes due to temperature or power supply voltage fluctuation.

When there is no fluctuation, assuming that the delay time T _G per one stage of gate delay is 1 ns, when T _AC = 1000 ns, the digital output D _{AC of} the second pulse phase difference encoding means M2 Is equivalent to 1000 from the number 1. In this case, if the digital output D _AB of the first pulse phase difference encoding means M1 due to the input of the pulse P _B corresponds to 500, then T _AB (pulses P _A , P) to be measured Time difference of _B ) is number 3
Using,

[0017]

Equation 4] T _AB = (500/1000) is determined as × 1000 ns = 500 ns. Here, assuming that the input timings of the pulses P _A , P _B , and P _C are unchanged and the delay time T _G per one stage of the gate delay is fluctuated, T _G ′ = 1.25 ns. the digital output D _AC two pulse phase difference encoding means M2 becomes equivalent to 800. On the other hand, the digital output D _AB of the first pulse phase difference encoding means M1 becomes equivalent to 400. Therefore, the pulse time difference T _AB to be measured is given by

[0018]

## _EQU00005 ## It is determined that T.sub.AB = (400/800) .times.1000 ns = 500 ns, and it can be understood from Equations 4 and 5 that correct correction can always be performed even if the delay time of the delay element changes.

As described above, according to the time A / D conversion circuit of the present invention, even if the detection accuracy (time resolution) changes, the minute time such as the pulse phase difference can be digitized with high speed and high accuracy. be able to.

[0020]

The present invention will be described below with reference to the embodiments shown in the drawings. FIG. 3 shows a block circuit configuration which is an embodiment of the time A / D conversion circuit 100 when the present invention is realized for measuring the optical round trip time of a laser radar. In FIG. 3, the time A / D conversion circuit 100 inputs from the input terminal 101 an input pulse P _A which rises in response to the laser beam emission time, and also rises from the input terminal 102 in response to the laser beam reception time. Input the input pulse P _B. It also has a built-in crystal oscillator 103.

Hereinafter, referring to the time chart of FIG.
First, the configuration of this embodiment will be described. Crystal oscillator 103 is a signal
As shown in INCKC, stable oscillation at a constant frequency
Is going. Here, from the input terminal 101, laser oscillation
Corresponding signal pulse P _AIs input, the control circuit 10
4 is a signal pulse P_AThe RST signal corresponding to the counter 10
Send to 5. The counter 105 is P_AThe rising edge of
A reference pulse P that rises after a certain period of time_C
Is generated, and the timing of occurrence is the rising edge of the RST signal.
Starts counting the number of pulses of the INCKC signal in response to falling
Then, it is set by counting only a predetermined pulse.
Note that instead of the oscillation pulse of the crystal unit 103, for example,
External stable clock signal EXCK like icon clock
Even if C is input from the external clock input terminal 107, the same
Reference pulse P_CCan occur.

Here, the pulse encoding circuits 108a and 108a
b has, for example, the circuit configuration shown in FIG.
Ruth P_APulse P that is input after_B(Okay
Is P _C) Is encoded and the digital value D is encoded._AB(Ah
Ruiha D_AC) Is output.

Schematic of the pulse phase difference encoding circuit shown in FIG.
Explaining the configuration, this circuit mainly uses a large number of signal delay circuits.
Ring delay with a path (hereinafter also referred to as gate delay)
Pulse generation circuit 1, counter 2, pulse selector
3, consisting of each block of encoder 4
Then, one of the input pulses P at terminal 6_AIs given,
Pulse P from the middle of the delay pulse generation circuit 1_A
Delay time depends on the number of stages of gate delay that the
Multiple delayed pulses in the whole area are output and the pulse selection
It is input to the actor 3. On the other hand, in the pulse selector 3
Pulse P from terminal 8 _AAnother pulse P later_B(is there
I'm P_C) Is input and this pulse P_B(Or
P_C) Is input, pulse P_AThe stage that has reached
Input pulse from the delaying pulse circuit 1
-3 selects the signal corresponding to this selected input.
Input to the encoder 4. Then enter the encoder
The binary digital signal corresponding to the force is output from encoder 4.
Output from force 9. Also, ring delay pulse generator
The final end 5 of the gate delay 1 returns to the OR circuit 1a.
So that the gate delay becomes ring-shaped.
Since it is connected, the delay time for all gate delays
Along with this, the repetitive pulse P_AIs the ring delay pulse generation time
Return to the left end of the road 1, and the output of the last end 5 causes the counter 2
Is the pulse P_AHow many times the gate delay has taken
Output from output 10 as the above bit of output 9
Then, with these outputs 9 and 10, the pulse P_A, P_B(Ah
Ruiha P_C) Time difference is digital value D_AB(Or
D_AC) Is output. In addition, in FIG. 5, NAND input
By setting 7 to 0, the ring delay pulse generation circuit 1
Is reset.

That is, in FIG. 3, when the pulse P _B indicating the reception timing of the laser beam reflected wave is input from the input terminal 102 after the oscillation (the input timing of P _A ), the pulse phase difference encoding circuit 108a. As described above, the input time difference T _AB is digitally converted by the resolution by the gate delay and is output as a digital value D _AB . Here, the output timing by this one A / D fluctuation operation is such that the period until the input of the next input pulse P _B is set.

Also in the other pulse phase difference encoding circuit 108b, the reference pulse P _C rising at the above-mentioned timing is input, and the input time difference T _AC from the P _A input to the P _C input is _calculated by the gate delay. It is digitally converted by the resolution according to and output as a digital value D _AC . Here, 108a and 108b have the same structure,
They are formed on the same chip, and the delay time due to the gate delay changes in the same manner due to changes in temperature and power supply voltage.

The circuits 108a and 108b send their digital outputs D _AB and D _AC to the arithmetic circuit 109. Arithmetic circuit 1
In 09, the time difference T _AB corresponding to to the reception from the oscillation of the laser, as a relative ratio to output D _AC sent from the circuit 108b, the exact value which is set based on the pulse signal always stably by a crystal oscillator 103 Based on the arithmetic processing shown in the above-mentioned Equation 3 so as to be corrected by T _AC ,
The digital output values D _AB and D _AC from the circuits 108a and 108b are compared (divided) and D _O corresponding to stable T _AB is output. D _O indicates the round-trip time of the laser beam and corresponds to the measured distance.

Here, as described above, the circuits 108a, 1a
Since the delay time due to the gate delay of 08b similarly changes, even if the delay time (that is, time resolution) changes, the operation circuit 109 always obtains a stable output value D _O. That is, even if the time resolution fluctuates from 1 ns to 1.25 ns, if 500 ns is measured, the measurement accuracy is 500 n.
Only from s ± 0.5 ns to 500 ns ± 0.625 ns, stable measurement can always be realized.

As described above, in the present embodiment, the minute time of the laser round trip is digitized at high speed and with high accuracy by the time resolution that can be obtained for each stage of the gate delay. The resolution can also be shortened. In addition, the accuracy can be corrected by digital calculation based on the stability of the crystal oscillator, and adjustment for correction is unnecessary. Furthermore, even if the gate delay time increases due to high temperature and the detection accuracy decreases, if it is within the allowable range,
Normal operation is possible even at high temperatures (200 ° C. or higher) where digital circuits operate, and the operating temperature range of conventional analog circuits can be exceeded.

Further, the time A / D conversion circuit 100 used in the above embodiment can be applied not only to the laser radar but also to other sensors. For example, an example adopted in an acceleration sensor is shown in FIG.

In FIG. 6, reference numeral 110 denotes an intelligent sensor in which a sensing unit and a circuit unit are formed on the same substrate so as to detect acceleration and output the amount of change in acceleration as a digital value. This intelligent sensor can be formed, for example, by the manufacturing method proposed in Japanese Patent Laid-Open No. 3-49267. Also, 12
Reference numeral 0 denotes a thin-walled beam that is distorted by the displacement of the weight 130 due to acceleration, and the beam 120 is formed with a piezoresistive effect element 140 whose resistance value changes according to the strain.

On the circuit side, 150 is an oscillator,
The oscillation frequency of the piezoresistive effect element 140 changes according to the change in resistance. The oscillator 150 further has a waveform shaping circuit, and the piezoresistive element 14
The pulse signal CKG having a frequency equal to the oscillation frequency determined by the resistance change of 0 is output. Reference numeral 160 is a known counter, which calculates a pulse signal CKG output from the oscillator 150 and outputs count signals C0 to C3. Reference numeral 170 is a decoder, and the decoder 170 outputs a reset signal RST to the counter 160 when the count value of the counter 160 reaches a predetermined value (for example, 9). Also, the decoder 170
6 outputs the pulse signal P _A shown in FIG. 6B when the preset count value is 0, for example, and outputs the pulse signal P _B when the count value is 9. ..

Here, the piezoresistive effect element 140
Is the one whose resistance value changes when it receives a displacement (strain)
And the oscillator 150 responds to the change in resistance value from small to large.
Since the oscillation frequency changes from high to low,
As shown in FIG. 6 (b), the pulse signal from the oscillator 150
Pulse signal P generated by counting 10 CKGs_BIs
Loose signal P_AThe rising position is the piezo resistance
The resistance change of the effect element 140, that is, the addition of the weight 130
It changes according to the magnitude of speed change. Obey
The pulse signal to the acceleration change acting on the weight 130.
P_A, P_BTime difference T _ABCan be detected as a change in
Wear. This time difference T_ABIs the pulse signal P_BOccurs
Change in the oscillation frequency contained in each pulse signal until
Minutes are accumulated, so detection of changes in acceleration
The sensitivity is improved and the oscillation frequency
It is also possible to detect changes.

Then, the time A / D conversion circuit 100 described above is used.
Is for inputting the pulse signals P _A and P _B , digitizing the time difference T _AB representing the acceleration change, and outputting it as a digital signal D _O.

Here, the time A / D conversion circuit 100 inputs not only the pulse signals P _A and P _B but also the stable clock signal CKC as described above, and thereby corrects the fluctuation of its own time resolution. Therefore, the sensor of this structure can always output the output value D _O with stable accuracy, regardless of temperature and power supply voltage fluctuations.

The application example shown in FIG. 6 shows an acceleration sensor in which a piezoresistive element is used to give a change in resistance as a time difference between two pulse signals. It can also be applied to an acceleration sensor designed to be captured. Moreover,
By appropriately changing the sensing unit, it can be applied to, for example, a magnetic sensor.

Next, another embodiment of the present invention, time A / D
FIG. 7 shows a schematic block circuit configuration of the conversion circuit. In the above-described embodiment, two pulse phase difference encoding circuits 108a and 108b are used as shown in FIG. 3, but in the present embodiment, one pulse phase difference encoding circuit 108 is used. Is realized. In the present embodiment, the pulse signal P to be input to the pulse phase difference encoding circuit 108 is formed so as to configure one pulse phase difference encoding circuit.
_B and P _C are assigned by time division.

The circuit operation will be described below with reference to the time chart of FIG. The pulse signal P _A having the pulse waveform shown in FIG. 8 is input to the pulse phase difference encoding circuit 108. Further, one of the other pulse signals P _B and P _C input to the pulse phase difference encoding circuit 108 is selected by the select signal SEL whose state changes in synchronization with the fall of the pulse signal P _A. Is selected. That is,
In FIG. 8, when the signal SEL is at the H level, the pulse signal P _B input with an arbitrary phase difference to be detected with respect to the pulse signal P _A is selected, while when the signal SEL is at the L level, Reference pulse signal P _C that is always input with a stable phase difference T _AC with respect to pulse signal P _A
Is selected. Then, the pulse phase difference encoding circuit 108
Performs the above-mentioned digital conversion corresponding to the time difference T _AB (or T _AC ) between the input pulse signal P _A and the pulse signal P _B (or P _C ) with its time resolution to obtain a digital value D _AB (or D _AC ). Output as. Then, the arithmetic circuit 109 performs the predetermined arithmetic operation shown in the equation 3 on the basis of these digital values D _AB and D _AC input in time division,
The error contained in the digital value D _AB due to the fluctuation of the time resolution of the pulse phase difference encoding circuit 108 is corrected by the digital value D _AC based on the time difference T _AC whose accuracy can be guaranteed, and this corrected time difference The digital value corresponding to T _AB is output as D _O.

Also in the structure of this embodiment, it is possible to obtain the same effects as in the above-mentioned embodiment and to reduce the circuit area, so that it is suitable for use in various sensor circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic basic configuration of the present invention.

FIG. 2 is a time chart explaining the operation of the present invention.

FIG. 3 is a block circuit configuration diagram of a laser radar to which an embodiment of the present invention is applied.

FIG. 4 is a time chart used to explain the operation of the embodiment.

FIG. 5 is a block diagram showing a circuit configuration example of a pulse phase difference encoding circuit.

FIG. 6A is a block diagram in which one embodiment is applied to an acceleration sensor, and FIG. 6B is a time chart for explaining the detection principle.

FIG. 7 is a schematic block diagram showing another embodiment of the present invention.

FIG. 8 is a time chart used for explaining the operation of another embodiment.

[Explanation of symbols]

M1 first pulse phase difference encoding means M2 second pulse phase difference encoding means M3 calculating means 100 hours A / D converter circuit 101 P _A input terminal 102 P _B input terminal 103 crystal oscillator 106 D _O output 108 , 108a, 108b pulse phase difference encoding circuit 109 arithmetic circuit

Claims (1)

Claim: What is claimed is: 1. A first pulse signal is input, the first pulse signal is passed through a plurality of delay elements, and the first pulse signal is delayed by an arbitrary time. The second pulse signal is input and the passing positions of the plurality of delay elements of the first pulse signal at the input timing of the second pulse signal are specified, so that the arbitrary time is set to the first time. Pulse-phase-difference encoding means for encoding the pulse signal based on the number of passed delay elements, and inputting the first pulse signal, the first pulse signal being the first pulse position. The first pulse signal is passed through a plurality of delay elements having the same configuration as the phase difference encoding means, and at the input timing of the reference pulse signal input with a constant time difference with respect to the first pulse signal. of The second pulse phase difference encoding means for identifying the passage position in a plurality of delay elements and encoding the constant time difference based on the number of the delay elements through which the first pulse signal has passed; Computing means for outputting the arbitrary time coded by the pulse phase difference coding means as a relative ratio to the constant time difference coded by the second pulse phase difference coding means. And time A / D conversion circuit.