JPH0537544A - Header error check device and atm cell monitor - Google Patents

Abstract

PURPOSE:To realize the compact device which receives an STM signal S including a header part comprising 1st to Pth header blocks and a header error check block to check a header error of the header part. CONSTITUTION:The device is provided with single error check sections 33, 35, 37 which check a header error when a control signal points out an n-th (n is a variable natural number between 1-N) ATM cell header unit and an n-th ATM cell HRC unit in a p-th (p is a variable natural number between 1-P) header block with respect to the n-th ATM cell header unit and the n-th ATM cell HRC unit in the p-th header block. A control signal generating section 15 generates a control signal pointing out continuously the 1st to N-th ATM cell header units of the 1st to Pth header blocks and then the lst to the N-th ATM cell HEC units continuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to STM (synchronous
transfer mode: AT used for synchronous transfer mode signal
M (asynchronous transfer mode)
The present invention relates to an ATM cell monitoring device for monitoring cells, and a header error checking device for checking header errors in ATM cells.

[0002]

2. Description of the Related Art ATM cells are transmitted as STM signals in STM (synchronous transfer mode). STM (synchronous transfer mode) is used at various levels. The STM signal is called an STM-M signal when transmitted at a level M (M is a predetermined natural number). The STM-1 signal is transmitted at a bit rate of 155.52 Mbit / s and contains 2,016 telephone channels. STM-4 signal is 662.08Mb
It is sent at a bit rate of it / s and contains 8,064 telephone channels. The STM-16 signal is transmitted at a bit rate of 2,488.32 Mbit / s and contains 32,256 telephone channels.

As will be described in detail later, various header error checking devices are already known. Such a header error checking device has a data input terminal for receiving an STM signal having a header part. The header error checking device checks a header error in the header part. Header parts are 1st to Pth
(P is a first predetermined natural number) and a header error check block. Each of the header blocks is a first to Nth (N is a second predetermined natural number) AT
The header error check block has M cell header units, and the first to Nth ATM cell header error check units. The first ATM cell header unit of the first to Pth header blocks and the first ATM cell header error check unit constitute a header of the first ATM cell. Similarly, the Nth ATM cell header unit of the first to Pth header blocks and the Nth AT cell
The M cell header error checking unit is the Nth ATM
Configure the cell header. Each of the first to Nth ATM cell header units and the first to Nth ATM cell header error check units has a third bit interval at a predetermined bit interval.
Has a predetermined natural number of bits.

The header error checking device includes a control signal generator connected to the data input terminal and generating a control signal. The control signal generating unit is, for example, an SDH (synchronous
digital hierachy) This is the end part. The conventional header error checking device includes first to Nth control signals. The nth control signal is the nth ATM of each header block.
The bits of the cell header unit and the nth ATM cell header error check unit are successively indicated. Here, n is variable between 1 and N inclusive.

In one of the conventional header error checking devices, the nth serial / parallel converter is controlled by the nth control signal, and the nth ATM cell header unit and the nth ATM cell header unit of the first to Pth header blocks are controlled. n ATM
Each of the cell header error checking units is converted into an nth bit parallel signal. The nth cyclic redundancy check (CRC) circuit performs a cyclic redundancy check on the nth bit parallel signal to determine the nth AT of the header block.
Check for header error in M cell header unit.

In another conventional header error checking device, an nth cyclic redundancy check (CRC) circuit is controlled by the nth control signal to cycle through each of the nth ATM cell header units of the STM signal. A redundancy check is performed to check for header errors in the nth ATM cell header unit of the header block.

[0007]

Here, since n is variable between 1 and N, such a conventional header error checking device includes first to Nth cyclic redundancy check circuits. Would be obvious. Therefore, the conventional header error checking device becomes large and expensive.

The conventional header error checking device is the first
Through the Nth ATM cell header unit
By checking the header error in the header part of the signal, it is possible to check the header error in the header of the first to Nth ATM cells.
It can be understood that the header error checking device is a device for monitoring the ATM cell. However, the conventional header error checking device has the ATM header together with the ATM cell header.
Information errors in the information fields of the ATM cells that make up the cell cannot be checked.

Therefore, an object of the present invention is to provide a compact and inexpensive header error checking device.

Another object of the present invention is to provide an ATM cell monitoring apparatus capable of checking not only a header error in an ATM cell header but also an information error in an ATM cell information field.

[0011]

According to one aspect of the present invention, there is provided a header error checking device having a data input terminal for receiving an STM signal having a header part and checking a header error in the header part.
The header part includes first to Pth header blocks (P is a first predetermined natural number) and header error check blocks, and each of the header blocks is a first to Nth header block.
(N is a second predetermined natural number) ATM cell header units, and the header error check block has first to Nth ATM cell header error check units and is connected to the data input terminal. To the first to Nth ATMs of the Pth header block
In the header error check device, including a control signal generation unit for continuously indicating a cell header unit and subsequently generating a control signal for continuously indicating the first to Nth ATM cell header error check units, Connected to a data input terminal and the control signal generator,
The control signal is the nth (n is a natural number that is variable between 1 and N) nth header block of the pth (p is a natural number that is variable between 1 and P) and the nth. When the ATM cell header error check unit is designated, the nth ATM of the pth header block
A header error checking apparatus is provided which has a single error checking unit for checking the header error with respect to a cell header unit and the nth ATM cell header error checking unit.

According to another aspect of the present invention, there is provided an ATM cell monitoring device used in combination with an ATM cell transmission system having a system input terminal for receiving a system input ATM cell and a system output terminal. , The ATM cell transmission system is the system input ATM
An ATM cell for directly transmitting a cell to the system output terminal and outputting the system input ATM cell as a system output ATM cell, monitoring the ATM cell transmission system, and checking an error in the system output ATM cell. The monitoring device receives an original ATM cell composed of a predetermined number of bytes, and converts the original ATM cell into a first converted ATM cell composed of the predetermined number of bytes and one empty byte added to it. A first format converter; connected to the first format converter, checking a first error in the predetermined number of bytes in the first converted ATM cell, and outputting a first error correction code; A first error check circuit for outputting; and the system input terminal of the ATM cell transmission system Connected to the first format converter and the first error check circuit, inserting the first error correction code into the empty byte of the first converted ATM cell to fill it. An ATM cell, and a coupler for sending the filled full ATM cell as the system input ATM cell to the system input terminal; and a coupler connected to the system output terminal of the ATM cell transmission system, A second error check circuit for checking a second error in a predetermined number of bytes and outputting a second error correction code; and a system output terminal of the ATM cell transmission system and the second error check circuit. The first error correction code which is connected and is included in the system output ATM cell is converted into the second error correction code. ATM cell monitoring device is obtained which is characterized by having; compared to the code, a comparator for outputting a comparison result.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

First, referring to FIG. 6, a conventional header error checking device will be described for better understanding of the present invention. This header error checking device includes a data input terminal 12 for receiving the above-described STM signal S of level M,
The first to Nth result output terminals 13 (1), 13 (2),
, And 13 (N). The result output terminal is
When viewed as a whole, the subscript is omitted and designated by reference numeral 13. When attention is paid to one of the result output terminals 13, the result output terminal 13 is called the nth result output terminal and is designated by the reference numeral 13 (n). This also applies to other reference signs used herein.

Referring to FIG. 7, the STM signal S includes a known section overhead SOH and a virtual container VC, as shown in the first line of FIG. The virtual container VC includes a known path overhead POH,
A header part HP and a payload with an information part IP. The path overhead POH follows the section overhead SOH in the STM signal S. The header part HP follows the path overhead POH in the STM signal S. Following the header part HP, the information part IP has first to Jth (J is a predetermined positive integer) information blocks (not shown), and each of the information blocks is first to Nth. ATM information unit (not shown). The header error check device is for checking a header error in the header part HP.

As shown in the second line of FIG. 7, the header part HP includes the first to Pth parts (P is a first predetermined natural number).
Header block and a header error check (HEC) block. Each of the header blocks includes a first to Nth (N is a second predetermined natural number) ATM cell header unit (these are "first to Nth header units").
Is abbreviated. ) Has. The header error check (HEC) block includes first to Nth ATM cell header error check units (these are abbreviated as “first to Nth HEC units”).
Have. Each of the first to Nth ATM cell header units and the first to Nth ATM cell header error check units has a third predetermined natural number Q of bits at predetermined bit intervals.

It is now assumed that the first predetermined natural number P is equal to 4 and the second predetermined natural number N has no special value. In general, the third predetermined natural number Q is typically equal to 8. That is, each of the ATM cell header unit and the ATM cell header error check unit has a 1-byte length, that is, an 8-bit length. Specifically, the bits of the first ATM cell header unit of the first header block are designated A (1), ..., And A (8). Second
The bits of the first ATM cell header unit of the header block of A are denoted by A (9), ..., And A (16).
Similarly, the bits of the second ATM cell header unit of the first header block are designated B (1), ..., And B (8).

Assuming now that the second predetermined natural number N is equal to 4, the Nth ATM of the Pth header block.
The bits of the cell header unit are indicated by N (25), ..., And N (32). The bits of the first ATM cell header error check unit are AH (1), ..., And A
It is indicated by H (8). The bits of the second ATM cell header error check unit are BH (1), ..., And BH
It is shown by (8). The bits of the Nth ATM cell header error check unit end with NH (8). In this way, the second predetermined natural number N indicates the multiplicity.

Referring to FIG. 8, first to Nth ATMs
One of the cells has 53 bytes. The illustrated ATM cell is called the nth ATM cell. Here, n is a natural number that is variable between 1 and N, as described above. First
The 5th to 5th bytes are called the header of the nth ATM cell, and the 6th to 53rd (that is, 48th) bytes are the nth ATM cell.
Called the information field of the ATM cell. In the information field shown, the previously defined positive integer J equals 48.

Referring to FIG. 7 in addition to FIG. 8, the first to fourth bytes represent the nth ATM cell header unit of the first to fourth (Pth) header blocks. In other words, the nth ATM cell header unit is shown as the pth byte, where p is variable between 1 and N inclusive. In detail, the p-th header block includes the first to N-th ATs.
The p-th byte of the M cell is composed of the first to Nth ATM cell header units. The fifth byte in FIG. 8 is the nth A
This is a TM cell header error check unit. As described above, the header part HP of the STM signal S includes the headers of the first to Nth ATM cells. Similarly, the STM signal S
Information part IP includes information fields of the first to Nth ATM cells.

In FIG. 7, paying attention to the nth ATM cell header unit of the first to Pth header blocks, the nth ATM cell header unit of the first to Pth header blocks is designated as (1, n). , (2, n), ..., And (P, n) ATM cell headers. In the pth header block of the first to Pth header blocks, the nth ATM cell header unit is called the (p, n) th ATM cell header.

Returning to FIG. 6 with reference to FIG. 7, the present header error checking device has an SDH (synchronous digital hierachy) terminal section 15 connected to the data input terminal 12.
Have. The SDH terminal unit 15 is responsive to the section overhead SOH and the path overhead POH to respond to the first to Nth bit and unit control signals C (1), C (C).
(2), ..., And C (N) are generated. As is apparent from the first and second bit and unit control signals C (1) and C (2) shown in the third and fourth lines of FIG.
The nth bit and unit control signal C (n) indicates a bit of the nth ATM cell header unit and a bit of the nth ATM cell header error check unit of the first to Pth header blocks.

First to Nth serial / parallel (S /
P) Converters 17 (1), 17 (2), and 17 (N)
Is connected to the data input terminal 12 and is connected to the SDH termination unit 15
From the first to Nth bits and a unit control signal C (subscript omitted). 1st to Nth
The n-th serial-parallel converter 17 (n) of the serial-parallel converter 17 (subscript omitted) converts the header part HP of the STM signal S into the n-th bit parallel signal.
As the first bit parallel signal is shown as (17) in the fifth line of FIG. 7, bit A (1) of the first ATM cell header unit of the first to Pth (fourth) header blocks. ~ A (32) and bits AH (1) to AH of the first ATM cell header error check unit
(8) appears at the end of the first bit and unit control signal C (1).

The first through Nth cyclic redundancy checks (CR
C) Circuits 19 (1), 19 (2), ..., 19 (N)
Receives the first to Nth bit-parallel signals from the first to Nth serial-parallel converters 17 (subscripts omitted).
The nth cyclic redundancy check circuit 19 (n) of the first to Nth cyclic redundancy check circuits 19 (subscript omitted) performs cyclic redundancy check on the nth bit parallel signal, and is high when a header error is detected. At the level, when no header error is detected, at the low level, the nth check result signal representing the nth check result is output. 6th of FIG.
The nth check result signal indicates that no header error is detected in the nth ATM cell header unit of the first to Pth header blocks, as indicated by the first check result signal as (19) in the line. When you have a low level. In this way, the first to Nth cyclic redundancy check circuits 19 output the first to Nth check result signals to the first to Nth result output terminals 13.

Next, another conventional header error checking device will be described with reference to FIGS. 9 and 10. In this header error checking device, the same parts as those described above are designated by the same reference numerals. The data input terminal 12 receives the header part HP of the STM signal S.
Although not shown in FIG. 9, the SDH termination unit 15 (FIG. 6)
Generate the first to Nth bits and the unit control signal C. The SDH terminal unit 15 further includes the first to Nth ATs.
M cell header error check unit signal T (1), T
(2), ..., And T (N) are selectively generated. Here, the first to Nth ATM cell header error check unit signals T (subscripts omitted) are referred to as first to Nth selection signals. The first to Nth bits and the unit control signal C are simply referred to as the first to Nth control signals. The first to N-th control signals C are supplied to the first to N-th control input terminals 21 (1), 21 (2), ... And 21 (N), that is, 21. The selection signal T of the first
To Nth selection input terminals 23 (1), 23 (2), ...
And 23 (N), that is, 23.

In FIG. 10, the header part HP of the STM signal S is shown in the first line, which is the same as described with reference to FIGS. 6 and 7. As is apparent from the first and second bit and unit control signals C (1) and C (2) shown in the second and third lines of FIG. 10, the nth bit and unit control signal C (n ) Indicates the bits of the nth ATM cell header unit and the bits of the nth ATM cell header error check unit of the first to Pth header blocks, similar to those described with reference to FIGS. 6 and 7. To do. As is apparent from the first selection signal T (1) shown as (T (1)) in the fourth line of FIG. 10, the nth selection signal T (n) is the nth ATM cell header error check. Selectively direct units.

The first to Nth cyclic redundancy checks (CR
C) The circuit 19 is directly connected to the data input terminal 12 without the serial-parallel converter 17 as shown in FIG. The nth cyclic redundancy check circuit 19 is further connected to the nth control input terminal 21 (n), and the nth control signal C
(N) is supplied to the nth control input terminal 21 (n).
The nth cyclic redundancy check circuit 19 detects the nth control signal C
A cyclic redundancy check is performed on the nth ATM cell header error check unit of the first to Pth header blocks selected from the STM signal S by (n).
An nth result signal representing the nth result is output. Specifically, the first to N-th cyclic redundancy check circuits 19 (1)-
19 (N) represents the first to Nth results and the first to Nth results
The result signals of are output respectively. The nth result signal is
It does not have a high or low level as in the case of FIGS. 6 and 7 and represents an nth update ATM cell header error check unit consisting of a number of update check bits equal to a third predetermined natural number Q. The update check bit of the nth update ATM cell header error check unit is typically the nth of the first to Pth header blocks.
The remainder obtained by dividing the ATM cell header unit of 1 by the generator polynomial is represented as an error correction code.

As is apparent from the first result signal shown as (19 (1)) in the fifth line of FIG. 10, the nth updated ATM cell header error check unit has update bits Ah (1) to Ah. It consists of (8). On the other hand, the ATM included in the STM signal received at the data input terminal 12
The cell header error check unit is called an original ATM cell header error check unit, and the bits of the original ATM cell header error check unit are called original bits.

First to Nth selectors or switches 2
5 (1), 25 (1), ..., and 25 (N), the first selector 25 (1) is connected to the data input terminal 12,
Moreover, the Nth selector 25 (N) is connected to the data output terminal 27.
Connected in a cascaded manner. The n-th selector 25 (n) includes the n-th cyclic redundancy check circuit 19
Receive the nth result signal from (n). Nth selector 2
5 (n) is controlled by the n-th selection signal received from the n-th selection input terminal 23 (n) to update the n-th update ATM.
The cell header error check unit is inserted in place of the original ATM cell header error check unit included in the STM signal supplied from the data input terminal 12. Nth
Therefore, the selector 25 (N) of the above supplies the STM signal in which the header error check block is rebuilt into the updated header error check block to the data output terminal 27 as a data output signal.

Referring back to FIGS. 6 to 10, in the conventional header error checking device, when the second predetermined natural number (ie, multiplicity) N increases, a large number of cyclic redundancy check circuits 1 are provided.
9 is needed. In addition, the conventional header error checking device of FIG.
, And the conventional header error checking device of FIG. 9 additionally requires a large number of selectors 25. As a result, conventional devices are large and expensive.

Next, a header error checking device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.
In FIG. 1, the same parts as those described above are designated by the same reference numerals. Similar to FIGS. 6 and 9, the data input terminal 12
Receives the original STM signal S. This header error checking device has a single data output terminal 31. SDH
The terminal unit 15 receives the original ST received from the data input terminal 12.
It receives the path overhead and section overhead carried by the M signal S and generates a bit control signal C (a) and a unit control signal C (b).

As shown in the first line of FIG. 2, the original STM
The signal S is the same as that described with reference to FIGS. 6 to 10. As shown in the second line of FIG. 2, the bit control signal C (a) is a bit of the first to Nth ATM cell header units of the first to Pth header blocks and a first to Nth ATM cell header error check. Indicates a bit in the unit. The unit control signal C (b) continuously indicates the first to Nth ATM cell header units of the first to Pth header blocks, as indicated by the pulse in the third line of FIG. The first to Nth ATM cell header error check units are continuously indicated.

Serial-parallel (S / P) converter 33
Are controlled by the bit control signal C (a) and the unit control signal C (b) received from the SDH terminal unit 15 and the original STM signal S received from the data input terminal 12. The serial-parallel converter 33 outputs the bit control signal when the unit control signal C (b) indicates the (p, n) th ATM cell header unit (that is, the nth ATM cell header unit of the pth header block). C
It is controlled by (a) to generate a 0th bit parallel signal. The 0th bit parallel signal is the (p, n) th ATM cell header unit and then the nth ATM cell header error when the unit control signal C (b) indicates the nth ATM cell header error check unit. This is a signal representing the check unit in bit parallel.

The first to Pth delay circuits 35 (1), 35
(2) and 35 (P) are serial-parallel converters 3.
3 connected in cascade. The first to P-th delay circuits 35 (subscripts omitted) generate the first to N-th bit parallel signals in a state where each delay circuit is supplied with the unit control signal C (b) from the SDH terminating unit 15. . In this way,
Delay circuit 35 (p) delays the p-th bit parallel signal by delaying the (p-1) -th bit parallel signal by a number NQ of bit intervals equal to N times the third predetermined natural number Q. To occur. When p is equal to 1, the (p-
The bit parallel signal 1) is the 0th bit parallel signal.

The unit control signal C (b) is the nth ATM
When instructing the cell header error check unit, the first
The to Pth bit parallel signals represent the nth ATM cell header units of the first to Pth header blocks in bit parallel. At this point, the 0th bit parallel signal represents the nth ATM cell header error unit in bit parallel.

Assuming that the first predetermined natural number P is equal to 4 in FIGS. 1 and 2, the delay circuit 35 is continuously referenced by the reference numerals 35 (1), 35 (2), 35 (3). ,
And 35 (4). As indicated by (35 (4)) in the fourth line of FIG. 2, the unit control signal C (b) is the first A in the fourth bit parallel signal.
At the time point after indicating the TM cell header error check unit, bits A (1) to A (8) of the first ATM cell header unit of the first header block are shown, and the line (35 (3 )), The third bit parallel signal, at this point in time, is the bit A of the first ATM cell header unit of the second header block.
(9) to A (16) are represented. Similarly, the second and first bit parallel signals represent bits A (17) to A (32) of the first ATM cell header unit of the third and fourth header blocks at the above point in time. As indicated by (33) in the sixth line of FIG. 2, the 0th bit parallel signal is the first A of the first header block at this point.
Bits AH (1) to AH of TM cell header unit
It represents (8). Here, in general, when the unit control signal C (b) indicates the nth ATM cell header error check unit, the pth bit parallel signal is (P-
(P-1)) represents the bits of the nth ATM cell header unit of the header block.

In FIG. 1, a single cyclic redundancy check (C
The RC) circuit 37 receives the 0th to Pth bit parallel signals from the serial-parallel converter 33 and the first to Pth delay circuits 35. The cyclic redundancy check circuit 37 performs a cyclic redundancy check on the 0th to Pth bit parallel signals relating to the nth ATM cell header unit and the nth ATM cell header error check unit of the first to Pth header blocks, and An nth check result signal representing the nth check result among the 1st to Nth check results is output. The first to Nth check results are the first when the unit control signal C (b) continuously indicates the first to Nth ATM cell header error check units.
To the Nth check result signal are continuously expressed.

As indicated by (37) in the seventh line of FIG. 2, the first check result signal has high and low levels as described with reference to FIGS. 6 and 7. When no header error is detected in the nth ATM cell header unit of the first to Pth header blocks,
The nth check result signal has a low level. Specifically, the cyclic redundancy check circuit 37 divides the combination of the nth ATM cell header unit and the nth ATM cell header error check unit of the first to Pth header blocks by the generating polynomial, and the remainder is left. If there is no remainder, that is, if the remainder is 0, the nth check result signal having a low level is output, and if there is a remainder, the nth check result signal having a high level is output.

Next, a header error checking device according to the second embodiment of the present invention will be described with reference to FIGS. 3 and 4. In FIG. 3, the same parts as those described above are designated by the same reference numerals. The data input terminal 12 receives the original STM signal S. This header error checking device supplies a rebuilt STM signal of the type described with reference to FIGS. 9 and 10 to the data output terminal 27 as a data output signal.

In FIG. 3, the SDH terminating unit 15 (FIGS. 6 and 1) receives the original STM signal S from the data input terminal 12, is controlled by the section overhead and the path overhead, and outputs the bit control signal C and the unit selection signal. Generate T. The bit control signal C is the same as that described with reference to FIGS. The unit selection signal T will be described below.

As shown in the first line of FIG. 4, the original ST
The M signal S is the same as above. As shown in the second line, the bit control signal C indicates the bits of the first to Nth ATM cell header units and the bits of the first to Nth ATM cell header units of the first to Pth header blocks. . As shown in the third line of FIG. 4 as (T) for only the first ATM cell header error check unit, the unit selection signal selectively indicates the first to Nth ATM cell header error check units at the logic 0 level. To do.

In the illustrated header error checking device, the clock counter 41 receives the bit control signal C from the SDH terminal unit 15, counts the bit designated by the bit control signal C, and the bit is a third predetermined natural number. Each time Q is counted, the clock count is incremented one by one from the initial value of zero. (N-1)
When the clock count of is reached, the clock count is reset. Thereby, the clock counter 41
, Such clock counts as (0, 1) through (0, N), (1, 1) through (1, N), ..., (p, 1) through (p, , And a count signal represented as the (P, 1) to (P, N) th clock counts. Each of the (p, n) th clock counts is represented in bit parallel by a count signal equivalent to the unit control signal C (b) described with reference to FIGS.

The clock counter 41 further outputs a write pulse train of negative write pulses instructing writing. In the write pulse train, the write pulses are numbered (0, 1) to (0, N), ..., (p, 1) to (p, N), ... And (P, 1) to (P, N) write time points. Each write pulse is output when the count signal indicates a correspondingly numbered clock count.

As indicated by (41-1) in the fourth line of FIG. 4, the count signals range from 0 to (N-1).
Are repeatedly expressed as the (p, 1) to (p, N) th clock counts. At this time, p indicating consecutive header blocks is incremented one by one in each repetition. The write pulse train is (41
-2).

In FIG. 3, a single cyclic redundancy check (C
The RC) circuit 43 directly receives the original STM signal from the data input terminal 12 and the bit control signal C from the SDH terminal unit 15. As described below, the cyclic redundancy check circuit 43 further receives the (p, n) th previous result signal. The (p, n) th previous result signal represents the previous result at the current time defined at the (p, n) th write time. That is, this previous result was obtained at the previous time point defined at the (p-1, n) write time point N times the third predetermined natural number before the (p, n) write time point. It is one. The cyclic redundancy check circuit 43 uses the result signal of the previous time to calculate the (p, n) th signal from the original STM signal S.
The ATM cell header unit is selected, the cyclic redundancy check is performed on the (p, n) th ATM cell header unit, and the (p, n) th result signal of the type described with reference to FIGS. 9 and 10 is output. Specifically, the (p, n) th result signal is output in bit parallel as the (p, n) th result and represents the (p, n) th updated ATM cell header error check unit. It serves as the intermediate result signal of n).

The AND gate 45 receives the (p, n) th intermediate result signal from the cyclic redundancy check circuit 43. The AND gate 45 further receives the unit selection signal T from the SDH terminal unit 15, and as long as the unit selection signal T is given the high level shown in the third line of FIG. ) Is passed as the (p, n) th output result signal.

Random access memory (RAM) 47
Are supplied with the (p, n) th output result signal from the AND gate 45, and are represented by the count signal supplied from the clock counter 41.
N) first to Nth accessible by the clock count
Memory cells 49 (1), 49 (2), ...
Have (N). A count signal, supplied from the clock counter 41, representing the (p, n) th clock count for accessing the nth memory cell 49 (n), and a corresponding numbering, supplied from the clock counter 41. The (p, n) th output result signal is stored in the second memory cell 49 (n) as the (p, n) th stored result signal in response to the write pulse train indicating the write time point. To be done. When only the count signal representing the (p, n) th clock count is supplied,
The random access memory 47 includes the nth memory cell 49.
From (n), the (p-1, n) th stored result signal is output as the (p, n) th previous result signal.

In the meantime, the count signal shows the (P, n-1) th clock count followed by the (P, n) th clock count. At this point, the (P, n) th output result signal is the nth memory cell 4
9 (n) is stored as the nth final result signal. When the count signal indicates the (P, n) th clock count,
The random access memory 47 outputs the (P, n) th output result signal as the nth result signal representing the nth result of the type described in FIGS. 9 and 10.

As described above, in FIG. 3, the AND gate 45 and the random access memory 47 are connected to the cyclic redundancy check circuit 43 and are controlled by the write pulse train acting as a unit control signal to function as a memory section. When the unit control signal continuously indicates the (p, n) th ATM cell header unit, the memo part (45,
47) stores the (p, n) th intermediate result signal as the (p, n) th stored result signal, and the cyclic redundancy check circuit 43 stores the (p-1, n) th stored result signal. Is supplied as the (p, n) previous result signal, and the unit control signal indicates the nth ATM cell header error check unit, the (P, n) stored result signal is
It is output as the nth result representing the above-mentioned error correction code (that is, the above-mentioned remainder) in the (p, n) th ATM cell header unit.

Further, in FIG. 3, the cyclic redundancy check circuit 43 is connected to the data input terminal 12 and the SDH terminal unit 15, and the unit control signal indicates the nth ATM cell header unit of the first to Pth header blocks. (P,
(n) when continuously designated as the ATM cell header unit, the cyclic redundancy check is performed on the (p, n) th ATM cell header unit and the (p, n) previous result signal, and the result of the cyclic redundancy check is Each of the (p, n) intermediate result signals is output in a state where each of the (p, n) intermediate result signals is output in bit parallel according to the bit control signal C.

Further, in FIG. 3, the SDH terminating unit 15 and the clock counter 41 function as a control signal generating unit connected to the data input terminal 12. The control signal generators (15 and 41) generate the bit control signal C and the unit control signal as control signals.

In FIG. 1 and FIG. 3, the header error checking device has a data input terminal 1 for receiving the STM signal S.
2 and has the SDH terminating unit 15 or the SDH terminating unit 15
And a clock counter 41 are included as a control signal generation unit that generates a control signal. A combination of the serial / parallel converter 33, the delay circuit 35, and the cyclic redundancy check circuit 37, or the cyclic redundancy check circuit 43.
And the combination of memory parts (45, 47) acts as a single error checking part. Single error check section (3
3, 35, 37 or 43, 45, 47) are connected to the data input terminal 12 and the control signal generator (15 or 15, 41), and the control signal is between the p-th (p is 1 or more and P or less). Variable nth header block nth (n is 1 or more)
When the number of the ATM cell header unit and the nth ATM cell header error check unit which are variable between N or less) is indicated, the header regarding the nth ATM cell header unit and the nth ATM cell header error check unit of the pth header block Check for errors.

Referring to FIG. 3 and FIG. 4, this header error checking device has an AT whose count signal is the (P, n) th.
SDH terminator 1 when showing M cell header unit
Bit control signal C from 5 to random access memory 4
It has a parallel-serial (P / S) converter 51 for receiving the 7th to nth final result signals. The parallel-serial converter 51 is controlled by the bit control signal C and converts the nth final result signal into the nth update ATM cell header error check unit of the first to Nth update ATM cell header error check units. The first update AT, shown as (51) in line 6 of FIG.
The M cell header error check unit includes first to Nth
(8th) update bits Ah (1), Ah (2), ..., And Ah (8).

The single selector or switch 53 is connected to the data input terminal 12, the SDH terminal section 15, the data output terminal 27, and the parallel-serial converter 51. The selector 53 is controlled by the unit selection signal T indicating the nth ATM cell header error check unit, and inserts the nth updated ATM cell header error check unit instead of the nth original ATM cell header error check unit. As a result, the selector 53
Reconstructed ST in which the 1st to Nth original ATM cell header error check units are selectively changed to the 1st to Nth updated ATM cell header error check units
The M signal is output to the data output terminal 27. The reconstructed STM signal is shown as (27) in line 7 of FIG.

The unit selection signal T has a low level to indicate the nth ATM cell header error check unit. In this case, the AND gate 45 is connected to the (p,
A 0 signal is output instead of the output result signal of n).

Next, an ATM cell monitoring device according to the third embodiment of the present invention will be described with reference to FIG. This ATM
The cell monitoring device is used in combination with an ATM cell transmission system 60 having a system input terminal 61 for receiving a system input ATM cell and a system output terminal 62. The ATM cell transmission system 60 has a system input A
The TM cell is directly transmitted to the system output terminal 62, and the system input ATM cell is output as the system output ATM cell. The ATM cell transmission system 60 is
For example, it is a known cross connection network.

The present ATM cell monitoring device is for monitoring the ATM cell transmission system 60 and checking for errors in the system output ATM cells. The present ATM cell monitoring device includes a first format converter 71 that receives an original ATM cell consisting of a predetermined number of bytes (typically 53 bytes described with reference to FIG. 8).

The original ATM cell is a virtual container VC-4 (NC) carried by another STM signal.
include. The virtual container VC-4 (NC) is
It includes a path overhead POH and a series of ATM cells following the path overhead POH in the STM signal. When attention is paid to one of the series of ATM cells, the ATM cell is called an original ATM cell. The original ATM cell is supplied to the first format converter 71 under the control of an SDH terminal unit similar to the SDH terminal unit 15 of FIG.

The first format converter 71 uses the original AT
Convert the M cells into a first converted ATM cell consisting of a predetermined number of bytes and one free byte added to it. One free byte is shown in phantom in FIG.

The first error checking circuit 72 is connected to the first format converter 71, checks the first error in the predetermined number of bytes in the first converted ATM cell, and checks the first error. Output the correction code. The first error check circuit is typically a first cyclic redundancy error check (CRC) circuit. In this case, the first error correction code is the remainder obtained by dividing the predetermined number of bytes of the original ATM cell contained in the first converted ATM cell by the generator polynomial.

The combiner 73 is an ATM cell transmission system 6
0 system input terminal 61, first format converter 71, and first error check circuit 72. The combiner 73 applies the first error correction code to the first error correction code.
Insert into the empty byte of the converted ATM cell of
A filled ATM cell is set, and the filled full ATM cell is set as a system input ATM cell.
Send to 1.

The second error check circuit 74 is an ATM
It is connected to the system output terminal 62 of the cell transmission system 60, checks the second error in the predetermined number of bytes of the original ATM cell included in the system output ATM cell, and outputs the second error correction code. The second error check circuit is typically a second cyclic redundancy error check (CRC) circuit. In this case, the second error correction code is the remainder obtained by dividing the predetermined number of bytes in the system output ATM cell by the generator polynomial.

The comparator 75 is the ATM cell transmission system 6
0 is connected to the system output terminal 62 and the second error check circuit 74, and the first error correction code included in the system output ATM cell is compared with the second error correction code and the comparison result is output. . In detail, the comparator 75 is
A match / mismatch signal indicating a match / mismatch between the first error correction code and the second error correction code is output as a comparison result.

The second format converter 76 is an ATM
The system output ATM cell, which is connected to the system output terminal 62 of the cell transmission system 60 and is composed of the predetermined number of bytes and the first error correction code added thereto, is converted into the second system conversion ATM cell of the predetermined number of bytes. Converted to ATM cells. When the match signal is output by the comparator 75, the original ATM cell is correctly transmitted by the ATM cell transmission system 60 as the second converted ATM cell, and when the mismatch signal is output by the comparator 75, the original ATM cell is transmitted. Are erroneously transmitted by the ATM cell transmission system 60 as second converted ATM cells.

Thus, this ATM cell monitoring device
An error can be checked in the header of the ATM cell and in the information field following the header in the ATM cell.

[0066]

As described above, according to the present invention,
A compact and inexpensive header error checking device can be obtained. Furthermore, according to the invention, an ATM can be checked for errors in the header of an ATM cell and in the information field following the header in that ATM cell.
A cell monitor is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a header error check device according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the device in FIG.

FIG. 3 is a block diagram of a header error check device according to a second embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the device of FIG.

FIG. 5 is a block diagram of an ATM cell monitoring device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional header error checking device.

FIG. 7 is a time chart for explaining the operation of the apparatus of FIG.

FIG. 8 is a diagram for explaining the structure of an ATM cell.

FIG. 9 is a block diagram of another conventional header error checking device.

FIG. 10 is a time chart for explaining the operation of the device in FIG.

[Explanation of symbols]

SSTM signal C (a) bit control signal C (b) Unit control signal 12 data input terminals 15 SDH termination 33 Serial-parallel (S / P) converter 35 Delay circuit 37 Cyclic Redundancy Check (CRC) Circuit C bit control signal T unit selection signal 41 clock counter 43 Cyclic Redundancy Check (CRC) Circuit 45 AND GATE 47 Random access memory 51 Parallel-serial (P / S) converter 53 selector 60 ATM cell transmission system 61 System input terminal 62 System output terminal 71 First Format Converter 72 First error check circuit 73 Combiner 74 Second error check circuit 75 Comparator 76 Second format converter

Claims (9)

[Claims] 1. A header error checking device having a data input terminal for receiving an STM signal having a header part and checking a header error in the header part, wherein the header part is a first to a P-th part (P is a first part). 1
Predetermined header numbers and header error check blocks, each of the header blocks having a first to Nth (N is a second predetermined natural number) ATM cell header unit. The check block has first to Nth ATM cell header error check units, is connected to the data input terminal, and continuously connects the first to Nth ATM cell header units of the first to Pth header blocks. In the header error check device, which includes a control signal generation unit for sequentially instructing the first to Nth ATM cell header error check units and continuously generating a control signal. A natural number that is connected to the control signal generation unit and in which the control signal is a p-th variable (p is between 1 and P inclusive). ) Header block of nth (n is 1 to N)
A natural number which is variable between the following) and an nth ATM cell header error check unit are indicated, the nth Ath of the pth header block
A header error check device having a single error check unit for checking the header error with respect to the TM cell header unit and the nth ATM cell header error check unit. 2. Each of the first to Nth ATM cell header units and the first to Nth ATM cell header error check units has a third predetermined natural number of bits at a predetermined bit interval. The control signal generation unit generates a bit control signal and a unit control signal as the control signal, and the bit control signal is the first to the Pth header blocks of the first block.
To bit of the Nth ATM cell header unit and bits of the first to Nth ATM cell header error check units, and the unit control signal of the first to Pth header blocks. 2. The header error checking device according to claim 1, wherein the first to Nth ATM cell header units and the first to Nth ATM cell header error checking units are instructed. Is connected to the data input terminal and controlled by the bit control signal and the unit control signal, and each of the first to Nth ATM cell header units of the first to Pth header blocks; The first to the Nth ATM cell header error check units are connected to the 0th A serial-parallel converter for converting into a parallel-parallel signal; cascade-connected to the serial-parallel converter, controlled by the unit control signal, and converted into a (p-1) -th bit parallel signal by N times the third predetermined natural number. First to P-th delay circuits for outputting first to P-th bit parallel signals by applying delays of a number of bit intervals equal to 1 to P; and the serial-parallel converter and the first to P-th delay circuits. An error check circuit for checking the header error in response to the 0th to Pth bit parallel signals, and the pth bit parallel signal is -(P
-1)) includes the bit of the nth ATM cell header unit of the header block, and the 0th bit parallel signal includes the bit of the nth ATM cell header error check unit at the time point. Header error checking device. 3. The header error check according to claim 2, wherein the time point is a time point when the unit control signal indicates the Nth ATM cell header unit of each of the first to Pth ATM cell header units. apparatus. 4. The error check circuit is connected to the serial / parallel converter and the first to Pth delay circuits, and performs a cyclic redundancy check on the 0th to Pth bit parallel signals, 3. The header error check device according to claim 2, which is a cyclic redundancy check circuit for checking a header error. 5. The ATM cell header unit and the ATM cell header error check unit each have a third predetermined natural number of bits at predetermined bit intervals,
The control signal generation unit generates a bit control signal and a unit control signal as the control signals, and the bit control signal is the first to Nth header blocks of the first to Pth header blocks. The bit of the ATM cell header unit and the bit of the first to Nth ATM cell header error check units are designated, and the unit control signal is the first to the first of the Pth header blocks. 2. The Nth ATM cell header unit and the first to Nth ATM cell header error check units are designated.
In the header error checking device, the single error checking unit is connected to the data input terminal and the control signal generating unit, and the unit control signal is the nth ATM of the first to Pth header blocks. When the cell header unit is continuously designated as the (p, n) th ATM cell header unit, the (p, n) th ATM cell header unit and the (p, n)
n) the previous result signal is subjected to a cyclic redundancy check,
The result of the cyclic redundancy check is output as a (p, n) th intermediate result signal in a state where each of the (p, n) th intermediate result signals is output in bit parallel according to the bit control signal. One cyclic redundancy check circuit; connected to the cyclic redundancy check circuit, controlled by the unit control signal, wherein the unit control signal is the (p,
n) the ATM cell header unit is continuously instructed, the (p, n) th intermediate result signal is stored as the (p, n) th stored result signal, and the unit control signal is stored in the nth. Of the ATM cell header error check unit of (1), and a memory unit for outputting the (P, n) th stored result signal as the nth result. . 6. The header error check device according to claim 5, wherein the control signal generator further generates a unit selection signal for selectively instructing the first to Nth ATM cell header error check units. When the unit selection signal is connected to the data input terminal, the control signal generation unit, and the memory unit and the unit selection signal indicates the nth ATM cell header error check unit, the nth result is returned to the nth result. Insert in place of the ATM cell header error check unit, and
A single M signal to a reconstructed STM signal, wherein the first to Nth ATM cell header error checking units are selectively converted to the first to Nth results output by the memory unit. A header error checking device further comprising: a selector unit. 7. An ATM cell monitoring device used in combination with an ATM cell transmission system having a system input terminal for receiving a system input ATM cell and a system output terminal, wherein the ATM cell transmission system comprises: The system input ATM cell is directly transmitted to the system output terminal, and the system input ATM cell is output as a system output ATM cell.
In the ATM cell monitoring device for monitoring a cell transmission system and checking an error in the system output ATM cell, an original ATM cell consisting of a predetermined number of bytes is received and the original AT is
A first format converter for converting M cells into a first converted ATM cell consisting of the predetermined number of bytes and one free byte added thereto; and connected to the first format converter , The first converted AT
A first error checking code in the predetermined number of bytes in the M cell and outputting a first error correction code;
An error check circuit of: connected to the system input terminal of the ATM cell transmission system, the first format converter, and the first error check circuit,
The first error correction code is converted into the first converted AT.
ATM filled with the empty byte of M cell
A combiner for transmitting the filled full ATM cell as the system input ATM cell to the system input terminal as a cell; the predetermined number in the system output ATM cell connected to the system output terminal of the ATM cell transmission system; A second error check circuit for checking a second error in several bytes and outputting a second error correction code; connected to the system output terminal of the ATM cell transmission system and the second error check circuit And a comparator for comparing the first error correction code contained in the system output ATM cell with the second error correction code and outputting a comparison result; apparatus. 8. The system output ATM cell connected to the system output terminal of the ATM cell transmission system, the system output ATM cell including the predetermined number of bytes and the first error correction code added to the predetermined number of bytes, 8. A second format converter for converting into a second converted ATM cell consisting of bytes.
ATM cell monitoring device. 9. The first error check circuit is connected to the first format converter to check for a first error in the predetermined number of bytes in the first converted ATM cell, A first cyclic redundancy error check circuit for outputting a first error correction code, wherein the second error check circuit is connected to the system output terminal of the ATM cell transmission system, 8. The ATM cell monitoring device according to claim 7, wherein the ATM cell monitoring device is a second cyclic redundancy error check circuit that checks a second error in a predetermined number of bytes and outputs the second error correction code.