JPH0535379A - Data input control method and data processor - Google Patents

Abstract

PURPOSE:To prevent the unexpected defect of fetching data by re-outputting the data whose output is previously interrupted, when a low power consumption mode is reset to a normal operating mode, and the data from a data inputting device can be inputted. CONSTITUTION:This device is equipped with a D-type flip flop 6 being an output inhibiting means, and a buffer 7 which operates the wired OR of an output control signal (b) outputted by a keyboard controller 4, with an output inhibiting signal (e) outputted by the D-type flip flop 6. Then, when the keyboard controller 4 resets from the low power consumption mode to the normal operating mode by a data input start from a keyboard 2, a keyboard microcomputer 8 is allowed to re-output the initial data. Therefore, when the absence of the data output from the keyboard microcomputer 8 in a prescribed time is detected, or when the data are not outputted by the keyboard microcomputer 8 by a command through an interface signal (a) from a main CPU 3 or the like, the keyboard controller 4 can be in the low power consumption mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low power consumption of a data processing device, and more particularly to a low power consumption device suitable for a battery-operated personal computer or word processor for inputting data from a keyboard or a mouse. Regarding power consumption.

[0002]

2. Description of the Related Art As an example of a conventional data processing device, there is a personal computer (hereinafter referred to as a personal computer) that receives data input from a keyboard which is a data input device. The personal computer described on pages 345 to 366 of the AX Technical Reference Guide 1989 (July 1989) issued by the AX Council will be described below with reference to the block diagram of FIG.

In the figure, 14 is a conventional personal computer, 2
Is a keyboard, 3 is a main operation unit of the personal computer 1 (hereinafter referred to as main CPU), 4 is a keyboard controller using a microprocessor unit (MPU), 5 is an oscillation circuit of the operating clock of the keyboard controller 4, and 8 is an MPU. The keyboard microcomputer, 9 is a key matrix, and 10a to 10d and 11a to 11d are half the number between the keyboard controller 4 and the keyboard microcomputer 8.
Buffers for performing two-way communication, 12a, 12b,
13a and 13b are pull-up resistors.

The keyboard microcomputer 8 is 10 ms to 2
The key matrix 9 is checked at a cycle of about 0 ms, and the data corresponding to the key input is output to the keyboard controller 4. The keyboard controller 4 receives this data and receives the main CP via the interface signal a.
Transfer to U3.

Further, the keyboard controller 4 sets the output control signal b to the "L" level so that the buffer 1
The clock c can be forcibly set to the “L” level via 0a. As a result, the keyboard microcomputer 8 can be prohibited from outputting data.

FIG. 3 shows the timing of data output from the keyboard microcomputer 8 to the keyboard controller 4. The keyboard microcomputer 8 determines that the data output is permitted when the clock c and the data d are at the “H” level, and outputs the data from the lower bit together with the clock of the cycle of about 70 μs. Keyboard controller 4
Captures this data by detecting the falling edge of the clock c and checking the data d. Further, as shown in FIG. 4, while the keyboard microcomputer 8 is outputting data, the keyboard controller 4 sets the output control signal b to the “L” level and the clock b is supplied via the buffer 10a.
When the data output to the keyboard microcomputer 8 is prohibited by setting the "L" level to "L" level, the keyboard microcomputer 8 recognizes the data output prohibition and outputs the data when the data output prohibition time exceeds about 100 μs. To cancel. After that, when the clock c and the data d are returned to the "H" level and the data output is permitted, the keyboard microcomputer 8 re-outputs the data whose output is stopped from the first bit.

[0007]

In the conventional device, no consideration was given to the low power consumption of the personal computer 1 including the keyboard controller 4.

Generally, in the MPU, the oscillation circuit of the clock is stopped, or the clock from the oscillation circuit is masked by an AND gate (not shown) inside the MPU to reduce the power consumption in the normal operation mode. 1/100 of
Some have a low power consumption mode in which the normal operation mode is restored by an external interrupt while suppressing the power consumption to 1/1000. Conventionally, it is known that the low power consumption mode is adopted for the main CPU, but this mode is also adopted for the keyboard controller 4 to further improve the personal computer 1.
It is possible to reduce the power consumption. Reducing power consumption is an important issue for battery-powered small portable personal computers.

Specifically, when an MPU having a low power consumption mode is used as the keyboard controller 4 and the keyboard controller 4 detects that no data is output from the keyboard microcomputer 8 for a predetermined time, or the interface signal a It is conceivable that at least the keyboard controller 4 is set to the low power consumption mode while data is not output from the keyboard microcomputer 8 by a command from the main CPU 3 via the. The subsequent return to the normal operation mode can be performed by interrupting the keyboard controller 4 by the data output from the keyboard microcomputer 8 and returning to the normal operation mode. However, the above-mentioned conventional personal computer 14 has the following problems.

When returning from the low power consumption mode to the normal operation mode, the MPU considers the stabilization time until the clock of the oscillation circuit 5 stabilizes, and after a predetermined time has elapsed from the interruption, the normal operation mode is set. It is supposed to return to. Therefore, during this period, the keyboard controller 4 cannot normally take in the data from the keyboard microcomputer 8. The predetermined time is, for example, about 500 μs, although it varies depending on the MPU. On the other hand, the data from the keyboard microcomputer 8 is output together with the clock of about 70 μs cycle, as shown in FIG. Therefore, in the keyboard controller 4, data is missed and the key input is lost. Also, 1
When each key input is converted into a plurality of data, for example, the first data is missed by the keyboard controller 4, but the rest of the data can be normally input, so that the key is garbled. There was a problem.

Further, when a mouse having a data output timing similar to the data output timing shown in FIGS. 3 and 4 is connected to the keyboard controller 4, from the mouse, for example, in accordance with the movement amount and the switch state, Flag data indicating the movement direction and the state of the switch, X data indicating the movement amount in the X direction, and Y data indicating the movement amount in the Y direction are output. In this case, if the keyboard controller 4 is set to the low power consumption mode and an interrupt is generated by the data output from the mouse to return to the normal operation mode, for example, the keyboard controller 4 drops the flag data, Main C
The PU 3 transfers the X data as flag data and the Y data as X data, which causes a problem of malfunction.

An object of the present invention is to prevent data loss when returning from the low power consumption mode to the normal operation mode, so that the input controller can be kept in the low power consumption mode during the period when no data is input. In view of this, it is an object of the present invention to provide a data processing device capable of reducing power consumption.

[0013]

In order to achieve the above object, a data input control method according to the present invention uses a data input device having a low power consumption mode to input data from a data input device. A data input control method, wherein when there is no data input for a predetermined time, the input controller is set to a low power consumption mode by allowing the data input, and then when the data input is restarted, The input controller is returned from the low power consumption mode to the normal operation mode, and data input is prohibited at least for a period that can be recognized by the data input device before the completion of the first data transfer after the restart, and thereafter, the input enable state is set. By returning the data, the data interrupted by the prohibition of the data input is transferred to the data input device. It is obtained so as to be retransmitted.

The data processing device of the present invention is a data processing device that receives data input from a data input device, receives data serially transferred from the data input device, and enters a low power consumption mode when there is no input for a predetermined time. An input controller for entering, a return means for returning the input controller from the low power consumption mode to the normal operation mode at the start of re-input from the data input device after the input controller enters the low power consumption mode, and the data input At the start of re-input from the device, a prohibition means for forcibly prohibiting serial transfer of the data input device, and a prohibition cancellation means for canceling the prohibition after a predetermined time has elapsed from the prohibition of data transfer by the means. Be prepared.

[0015]

When the data processing device does not input data for a predetermined time, the data processing device enters the low power consumption mode while permitting data input from the input device. After that, when the input of data from the data input device is restarted, the input controller returns from the low power consumption mode to the normal operation mode by the returning means. Specifically, when the input controller is interrupted, it returns to the normal operation mode. At the same time as the interrupt
The prohibiting means forcibly interrupts data input from the data input device. This interruption is performed by forcibly grounding the signal line from the data input device to the input controller. When the data input device detects the forced grounding of the signal line, it recognizes that the input of the data being transferred is interrupted, and interrupts the data transfer.

When the data processing device is returned from the low power consumption mode to the normal operation mode by the interrupt and data can be input from the data input device, the prohibition is released and the data input device is allowed to output data. To be done.
As a result, the data input device re-outputs the data whose output was previously interrupted.

In this way, it is possible to prevent the loss of data when returning from the low power consumption mode to the normal operation mode. Therefore, while the data input device is not outputting data, at least the input controller is set to the low power consumption mode, which is 1/100 to 1 of the normal operation mode.
/ 1000 power consumption can be reduced,
The power consumption of the data processing device can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, an example in which the data input device is mainly applied to a keyboard and the data processing device is applied to a personal computer will be described in detail below.

First, the first embodiment will be described with reference to the block diagram of FIG.

In the figure, 1 is a personal computer using the present invention, 6 is a D-type flip-flop which is an output inhibiting means, 7
Is an output control signal b output from the keyboard controller 4.
And a buffer for wired-ORing the output inhibition signal e output from the D flip-flop 6. Below, FIG.
Constituent elements that are the same as those shown in FIG. When the operation control signal f is at "H" level, the D-type flip-flop 6 outputs "H" level to the output prohibiting signal e regardless of the clock c, and the operation control signal f is at "L" level. At this time, the buffer 7 operates at the falling edge of the clock c to output the “L” level to the output inhibit signal e, and
By setting the clock c to the “L” level via
Data output is prohibited to the keyboard microcomputer 8. Further, by inputting the clock c into the interrupt input terminal of the keyboard controller 4 via the buffer 10b, the interrupt is applied at the falling edge of the clock c. For simplification of the drawing, in FIG. 1, the connection of the personal computer 1 and the keyboard 2 is shown as four lines of clock c, data d, ground, and power source, but other lines may be connected. Of course.

FIG. 5 shows an example of the operation timing when the keyboard controller 4 in the personal computer 1 returns from the low power consumption mode to the normal operation mode by the data output from the keyboard microcomputer 8 in the keyboard 2.

The keyboard controller 4 shifts from the normal operation mode to the low power consumption mode when it detects that there is no data input from the keyboard microcomputer 8 for a predetermined time or by an instruction from the main CPU 3 through the interface signal a. At this time, by setting the output control signal b to "H" level and the operation control signal f to "L" level,
The clock c is set to "H" level (t1). As a result, the keyboard microcomputer 8 is allowed to output data, and the D-type flip-flop 6 is allowed to operate at the falling edge of the clock c to enter the low power consumption mode. The detection of the absence of data input for a predetermined time can be realized by a known method using a combination of a hardware timer and a program built in the keyboard controller 4.

After that, when the keyboard microcomputer 8 detects the key input by checking the key matrix 9, it judges that the data output is permitted because the clock c and the data d are at the "H" level. Data corresponding to key input is sent to the keyboard controller 4
Output to. As a result, the data d goes to the "L" level (corresponding to the start bit) via the buffer 11c, and then the clock c goes to the "L" level via the buffer 11a (t2).

The D-type flip-flop 6 operates at the falling edge of the clock c in this operation, and the output inhibit signal e
Goes to "L" level and clock c
Becomes "L" level, data output to the keyboard microcomputer 8 is prohibited, and the keyboard controller 4 is interrupted (t2). The keyboard controller 4 returns to the normal operation mode about 500 μs after the interruption. During this period, the clock c is at "L" level, so the keyboard microcomputer 8 detects that the data output is prohibited, and stops the output of this data. When the keyboard controller 4 returns to the normal operation mode and data can be input, the operation of the D-type flip-flop 6 is prohibited (forcibly cleared) by setting the operation control signal f to the “H” level ( t3). As a result, the output prohibiting signal e is released and becomes "H" level.
As a result, the clock c which has been set to the “L” level via the buffer 7 is returned to the “H” level. This allows the keyboard microcomputer 8 to output data.

The keyboard microcomputer 8 determines that the data output is permitted because the clock c and the data d have become "H" level. Therefore, in order to re-output the data whose output has been stopped earlier, the data d is set to the “L” level via the buffer 11c, and then the clock c is set to the “L” level via the buffer 11a (t4).
Data is output from the lower bit with a clock of about 70 μs cycle. On the other hand, the keyboard controller 4
Data is input by detecting the falling edge of the clock c and checking the data d via the buffers 10b and 10d.

According to the present embodiment, when the keyboard controller 4 returns from the low power consumption mode to the normal operation mode by starting the data input from the keyboard 2, the keyboard microcomputer 8 re-outputs the first data, and It is possible to prevent the loss of data when returning from the power consumption mode to the normal operation mode. Therefore, when it is detected that no data is output from the keyboard microcomputer 8 for a predetermined time, or when the keyboard microcomputer 8 does not output data due to an instruction from the main CPU 3 via the interface signal a, the keyboard controller 4 consumes less power. The power mode can be set, and thus the power consumption of the personal computer 1 can be reduced. Specifically, in the low power consumption mode, the power consumption can be suppressed to 1/100 to 1/1000 of that in the normal operation mode.

The main CPU 3 together with the keyboard controller 4 are set to the low power consumption mode, and after the keyboard controller 4 returns from the low power consumption mode to the normal operation mode, the main CPU 3 is set to the low power consumption mode via the interface signal a. Then, by returning to the normal operation mode, it is possible to further reduce the power consumption of the personal computer 1.

In the present embodiment, the output control signal b and the output inhibition signal e are wired-ORed by using the buffer 7 and the buffer 10a. However, as shown in FIG.
Of course, a negative logic OR15 of the output control signal b and the output prohibition signal e may be used.

Further, in this embodiment, D is generated by the clock c.
The flip-flop 6 is operated to interrupt the keyboard controller 4, but as shown in FIG. 3, the keyboard microcomputer 8 always sets the data d to the “L” level when outputting the data. As in the second embodiment shown in FIG. 7, the D-type flip-flop 6 may be operated by the data d and the keyboard controller 4 may be interrupted. Alternatively, FIG.
It is also possible to operate the D-type flip-flop 6 by the clock c and interrupt the keyboard controller 4 by the data d, as in the third embodiment shown in FIG.

Next, a fourth embodiment of the present invention will be described with reference to FIG. As mentioned above, the keyboard microcomputer 8
Has a function of re-outputting this data when data transfer is prohibited during serial transfer of 1 byte. Further, as described in FIG. 2, it takes about 500 μs from the interruption of the keyboard controller 4 in the low power consumption mode to the return to the normal operation mode. On the other hand, as shown in FIG. 3, since the data length from the keyboard microcomputer 8 is 11 bits (start bit 1 bit, data 8 bits, parity 1 bit, stop bit 1 bit), the keyboard microcomputer 8 stores 1 byte of data. It takes about 700 μs to output. From these facts, before the keyboard microcomputer 8 finishes sending the 1-byte data, the keyboard controller 4 returns to the normal operation mode to set the output control signal b to the “L” level and the buffer 10
It can be seen that the clock c can be set to the “L” level via a. This means that the keyboard microcomputer 8 can be used without using the D-type flip-flop 6 shown in FIG.
Means that data output can be prohibited. Note that, here, a case where a mouse that outputs the same data as the keyboard microcomputer 8 described in FIG. 1 is used as the data input device will be described. Also in this embodiment,
Of course, like the previous embodiment, a keyboard can be adopted as the data input device.

In FIG. 9, 16 is a key matrix 9
The key is arranged at the intersection point of, and includes a key contact 17 and a diode 18. To simplify the explanation, the SCAN line and SENS of the key matrix 9 are
There are two E lines each. 19 is a negative logic OR, 20a
Further, 20b is a pull-up resistor, 21 is a mouse, 22 is a mouse microcomputer using an MPU, 23 is a sensor for detecting the moving direction and moving amount of the mouse, and 24 is a switch. In this embodiment, the personal computer 1 is provided with a key matrix 9, and the keyboard controller 4 is, for example, SCAN0.
Is set to "L" level, SCAN1 is set to high impedance, and the state of the SENSE line is checked to check the key contact 17, and the key contact 1 that is turned on is checked.
When 7 is detected, the corresponding data is transferred to the main CPU 3 via the interface signal a. Further, the mouse microcomputer 22 sets the data regarding the moving direction detected by the switch 24 and the sensor 23 as flag data, and the data regarding the moving amount detected by the sensor 23 as X data.
The data and the Y data are output to the keyboard controller 4 at the same output timing as the keyboard microcomputer 8 in FIG. The key detection signal g, which is the output of the negative logic OR 19, is supplied to the interrupt 1 of the keyboard controller 4.
Data d is input to the interrupt 2 via the buffer 10d.

FIG. 10 shows the operation timing when the keyboard controller 4 returns from the low power consumption mode to the normal operation mode by the data output from the mouse microcomputer 22.

Low consumption when the keyboard controller 4 detects that there is no key input from the key matrix 9 and no data output from the mouse microcomputer 22 for a predetermined time, or due to a command of the main CPU 3 via the interface signal a. When entering the power mode, the keyboard controller 4 sets SCAN0 and SCAN1 to the "L" level, sets the output control signal b to the "H" level, and sets the clock c to the "H" level via the buffer 10a. 22 is permitted to output data.

After this, the sensor 23 or the switch 24
Accordingly, when the mouse microcomputer 22 detects the movement of the mouse 21 or the switch input, the clock c and the data d are at the “H” level, so it is determined that the data output is permitted, and as shown in FIG. Then, the output of data is started with the clock of about 70 μs cycle (t1
0). Since the data length is 11 bits, it takes about 700 μs to output the data.

The keyboard controller 4 is interrupted by the fall of the data d, returns from the low power consumption mode to the normal operation mode, sets the output control signal b to the "L" level, and outputs the clock c via the buffer 10a. It is set to "L" level to prohibit data output to the mouse microcomputer 22 (t11). As described with reference to FIG. 2, the keyboard controller 4 takes about 500 μs from the interruption to prohibiting the data output to the mouse microcomputer 22, but the mouse microcomputer 22 needs about 700 μs to output 1-byte data. It is detected that the data output is prohibited during the output of this data, and the output of this data is stopped.

The keyboard controller 4 sets the output control signal b to the "H" level after the data output inhibition time required for the mouse microcomputer 22 to reliably stop the data output, for example, 100 μs has elapsed.
The clock c is set to the "H" level via the buffer 10a to permit the mouse microcomputer 22 to output data (t12). As a result, the mouse microcomputer 22 detects that the clock c and the data d have reached the "H" level, determines that the data output has been permitted, and re-outputs the data that was previously stopped.

FIG. 11 shows the operation timing when the keyboard controller 4 returns from the low power consumption mode to the normal operation mode by the key input from the key matrix 9. When the keyboard controller 4 detects that there is no key input from the key matrix 9 and no data output from the mouse microcomputer 22 for a predetermined time, or by a command of the main CPU 3 via the interface signal a, etc., the low power consumption mode , The keyboard controller 4 sets SCAN0 and SCAN1 to "L".
At the same time, the output control signal b is set to "H" level and the clock c is set to "H" level via the buffer 10a to permit the mouse microcomputer 22 to output data.

After that, when a key input is made from the key matrix 9, the corresponding key contact 17 is turned on, the corresponding SENSE line becomes "L" level, and the negative logic OR1.
The key detection signal g falls through 9 and the keyboard controller 4 is interrupted (t20). This allows
The keyboard controller 4 returns from the low power consumption mode to the normal operation mode, sets the output control signal b to "L" level, sets the clock c to "L" level via the buffer 10a, and transfers the data to the mouse microcomputer 22. The output is prohibited (t21). The keyboard controller 4 sets the output control signal b to the “H” level after the data output inhibition time required for the mouse microcomputer 22 to reliably stop the output of data, for example, 100 μs has elapsed.
The clock c is set to the "H" level via the buffer 10a to permit the mouse microcomputer 22 to output data (t22).

If the mouse microcomputer 22 detects the input of the switch 24 or the movement of the mouse 21 by the sensor 23 before the keyboard controller 4 returns to the normal operation mode, the mouse microcomputer 22 determines that the clock c and the data d are "H". It waits until the output level is reached and data output is permitted, and then the data is output.

According to this embodiment, the data d is stored in the buffer 1
By connecting to the interrupt input terminal of the keyboard controller 4 via 0d, that is, without increasing the cost,
Data loss when the keyboard controller 4 returns from the low power consumption mode to the normal operation mode can be prevented by re-outputting the data from the mouse microcomputer 22. Therefore, when it is detected that there is no key input from the key matrix 9 and no data output from the mouse microcomputer 22 for a predetermined time, or by an instruction from the main CPU 3 via the interface signal a, the key from the key matrix is The power consumption of the personal computer 1 can be reduced by keeping the keyboard controller 4 in the low power consumption mode while the input and the mouse microcomputer 22 do not output the data.

The main CPU 3 together with the keyboard controller 4 are set to the low power consumption mode, and after the keyboard controller 4 returns from the low power consumption mode to the normal operation mode, the main CPU 3 is set to the low power consumption mode via the interface signal a. Then, by returning to the normal operation mode, it is possible to further reduce the power consumption of the personal computer 1.

In this embodiment, the case where the re-output is performed in the unit of 11-bit data shown in FIG. 2 has been described, but it is obvious that the present invention can be easily applied to the case where the re-output is performed in the unit of a plurality of data. is there.

[0043]

According to the present invention, in a data processing device using an input controller having a low power consumption mode, it is possible to effectively prevent data loss when returning from the low power consumption mode to the normal operation mode. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is an explanatory diagram of output timing of data output from the data input device.

FIG. 4 is an explanatory diagram of data re-output timing of the data input device.

FIG. 5 is an explanatory diagram of an operation timing example of the first embodiment.

FIG. 6 is an explanatory diagram of a modification of the first embodiment.

FIG. 7 is a block diagram of a second embodiment of the present invention.

FIG. 8 is a block diagram of a third embodiment of the present invention.

FIG. 9 is a block diagram of a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram of an operation timing example of the fourth embodiment.

FIG. 11 is an explanatory diagram of another operation timing example of the fourth embodiment.

[Explanation of symbols]

1 ... PC, 2 ... Keyboard, 3 ... Main CPU, 4
... keyboard controller, 5 ... oscillation circuit, 6 ... D flip-flop, 7 ... buffer, 8 ... keyboard microcomputer, 9 ... key matrix, 21 ... mouse, 22 ... mouse microcomputer, 23 ... sensor, 24 ... switch, b ... output Control signal, c ... Clock, d ... Data, e ... Output inhibit signal, f ... Operation control signal.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshiaki Nomura             Chiba Prefecture Narashino City Higashi Narashino 7-1-1             Hitachi Ltd. office system design             In the development center

Claims (9)

[Claims] 1. A data input control method for a data processing device that receives data input from a data input device using an input controller having a low power consumption mode, wherein no data is input for a predetermined time. When the data input is restarted, the input controller is returned to the normal operation mode from the low power consumption mode by the data input when the data input is restarted. Data is prohibited at least for a period that can be recognized by the data input device before the completion of the data transfer of the data, and then the data input device is returned to the input enable state to transfer the data interrupted by the data input device to the data input device. A method for controlling data input, characterized in that the data is retransmitted to the device. 2. The data input control method according to claim 1, wherein the data input prohibited state is realized by forcibly grounding a signal line connected from the data input device to the input controller. 3. The data input device detects the data input prohibited state while transferring data to the input controller, interrupts the data transfer, and automatically resends the data when the prohibited state is released. The data input control method according to claim 1 or 2, further comprising a function of: 4. The data input according to claim 1, wherein the input controller is returned from the low power consumption mode to the normal operation mode by interrupting the input controller with a signal received from the data input device. Control method. 5. A data processing device for receiving data input from a data input device, the input controller receiving data serially transferred from the data input device and entering a low power consumption mode when there is no input for a predetermined time, After the input controller enters the low power consumption mode, at the time of starting the re-input from the data input device, a return means for returning the input controller from the low power consumption mode to the normal operation mode, and the re-input start from the data input device. At the same time, a prohibition unit forcibly prohibiting serial transfer of the data input device, and a prohibition cancellation unit for canceling the prohibition after a predetermined time has elapsed from the prohibition of data transfer by the device are provided. And data processing device. 6. The data processing device according to claim 5, wherein the data input device has a function of retransmitting the data when the prohibition is released when the serial transfer of the data is prohibited. 7. The data processing according to claim 5, wherein the prohibiting means prohibits data transfer by forcibly grounding a signal line connected from the data input device to the input controller. apparatus. 8. The inhibiting means comprises a flip-flop whose output value changes according to a signal change of a signal line from the data input device to the input controller, and a means for grounding the signal line by an output of the flip-flop. 8. The data processing device according to claim 7, wherein the prohibition canceling unit is realized by the input controller resetting the flip-flop. 9. The input controller returns to a normal operation mode and outputs a control signal for a predetermined period before the data input device completes the transfer of one data at the start of re-input, and in response to the control signal. 8. The data processing device according to claim 7, wherein the prohibition unit and the prohibition cancellation unit are realized by forcibly grounding a signal line from the data input device to the input controller during the period.