JPH0535527A - Data access stop system - Google Patents

Abstract

PURPOSE:To provide a data access stop system where the desired data addresses to be stopped can be set for each task and only the execution of the corresponding task can be stopped in an address match state. CONSTITUTION:An optional trap data address is set at an initial processing point of time to a TDA information group 140 included in a TSS 10 which controls the operating history working in a multi-task state and a task switch debug interruption is generated with a T bit 130. When a program starts, the TDD is switched with relation secured to a BLP 110 for each transition of a task. Then the task switch interruption processing 510 is started when the bit 130 is turned on in a new TSS, and a DAR 30 is rewritten in the group 140. Thereafter a CPU compares a generated address with the DAR 30 for each memory access. When the matching is secured in this comparison, the address match debug interruption processing 520 is started. Then the operation of only the corresponding task can be stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access stop method for temporarily stopping the execution of a program when a CPU accesses a specified data address, and particularly for a task required for debugging software operating in multitasking. The present invention relates to a data access stop method that can suspend only program execution.

[0002]

2. Description of the Related Art A conventional data access stop method is CP
A function that sets the data address of the entire system in advance in the debug address register supported by the U hardware architecture and stops the system when the CPU accesses this data address during execution of the program. Therefore, generally, debugging of programs was performed by using this function.

[0003]

In the above conventional data access stop method, the data address set in the debug address register is not managed for each task even if the system is operating in a multitasking environment. However, when the CPU accesses the set data address, the entire system operating in multitasking must be stopped.

Further, the number of data address values to be stopped for debugging is limited by the number of entries in the debug address register. Therefore, at the time of debugging, there is a data address to be set separately for each task constituting the multitask. However, the number of debug target tasks had to be limited within the limit of the number of entries in the debug address register.

Furthermore, even if an unexpected task that does not need to be stopped is operating, if the data address set in the debug address register coincides with the memory address generated by the CPU, a data address match interrupt will occur. However, there is also a drawback in that in order to prevent the generation of this unnecessary interrupt, it is necessary to incorporate a process for ignoring this interrupt by software.

An object of the present invention is to set a data address to be stopped for each task, and to temporarily stop only execution of a program of a necessary task when the CPU accesses a specified data address. It is to provide an access suspension method.

[0007]

According to the data access stop method of the present invention, a task switching debug interrupt is issued to a CPU at the time of task switching in a task state segment storing operation history information of each task operating in a multitasking environment. It has a task trap bit for generating and a trap data address information group in which a trap data address for generating a data address matching debug interrupt is registered during the operation of the task, and is generated each time the CPU accesses the memory. Includes a debug address register that stores a trap data address that generates an address match debug interrupt when compared with an address, and an identification bit that identifies the cause of the task switch debug interrupt and the address match debug interrupt Debug stay And Surejisuta, CP at the time of task switching
A task switching debug interrupt unit that is activated when U detects the task trap bit, rewrites the debug address register with the trap data address information group of the task state segment, and ends the interrupt process, and generates a CPU data access address. Address match debug interrupt means that is activated when the contents of the debug address register are matched, identifies the cause of occurrence from the debug status register, and stops only the task currently occupying the CPU and operating in that state Is configured.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a configuration diagram of a main part for explaining an embodiment of the present invention.

The operation history (contents of each register, pointer to the starting task, etc.) of each debug target program operating in multitask is managed by TSS (task state segment) 10 provided for each task. Has been done. In the TSS 10, a BLP (back link pointer) 110 that points to the TSS of the task from which this task is activated, and a CP when the task is activated next time.
A register copy area 120 that stores a value to be restored in each register in U and a T bit (defining whether or not a task switching debug interrupt is generated in the CPU when control is passed to this task again) Task trap bit) 1
30 and a TDA information group (trap data address information group) 140 storing trap data addresses whose execution is stopped during the operation of this task are stored.

In this embodiment, since there are four types of trap data addresses that can be set at once for each task, the TDA information group 140 includes TDAR0 to TDAR3.
It is composed of four. It is sufficient that the TSS 10 has at least an area for storing the control data described above, but of course, in addition to this, it may include information necessary for the CPU to control the operation of the multitask system.

The TSS for debug interrupt processing which is activated when a debug interrupt occurs is the TSS for interrupt processing.
20, but the structure is exactly the same as TSS10. However, in general, the TD for the interrupt processing TSS 20 is
It does not have the A information group 140.

On the other hand, the trap data address that is compared with the memory address generated by the CPU (excluding instruction fetch) and generates an address match debug interrupt when the addresses match is a DAR (debug) which is one of the hardware registers of the CPU. Address register) 30. In this embodiment, since there are four types of trap data addresses that can be set at one time, the DAR 30 is the DAR.
It is composed of four pieces of 0 to DAR3.

When a debug interrupt occurs, its type is identified by a DSR (debug status register) 40. The DSR 40 has a task switch interrupt display bit 410 indicated by BT that displays a task switch debug interrupt.
And the address match debug interrupt display bit 420 indicated by Bn (n is 0 to 3) for displaying the address match debug interrupt. As described above, in this embodiment, D is used.
Since the AR 30 is composed of 4 entries, the address match debug interrupt indication bit 420 has 4 bits B0 to B3. For example, if the B2 bit is on when a debug interrupt occurs, the address match debug interrupt by DAR2 is determined to be the cause of the interrupt.

The interrupt processing program 50, which is started when a debug interrupt is generated, identifies the interrupt factor from the above-mentioned DSR 40, and (1) is a task switching debug interrupt processing 510 which is started at the time of a task switching debug interrupt. (2) Address match debug interrupt processing 520 which is activated at the time of address match debug interrupt.

Next, the operation of the data access stop system of this embodiment will be described.

First, each debug target task operating in multitask sets an arbitrary trap data address to be stopped at the time of access to the TDA information group 140 in each TSS 10 at the time of initial processing before being activated. Since this operation is generally impossible in the program to be debugged, it is necessary to use the help of the OS or language processing system tools (linker and loader), but the details are omitted because it is not the essence of the present invention. In this embodiment, four TDAR0 to TDAR3 are prepared. Each TDAR
The trap data addresses set in 0 to TDAR3 may be the task specific space or the system common space. The T bit 130 is set in the TSS 10 of the task in which a valid trap data address is stored in the TDA information group 140 so that a debug interrupt will continue to occur at the time of task switching.

The interrupt processing program 50 which operates when a debug interrupt occurs is loaded into the memory together with the corresponding interrupt processing TSS 20.

After the above preparations are completed, when the program of the multitasking structure to be debugged starts to operate, the TSS1 of the old task is generated each time a task transition occurs between the tasks.
Switching from 0 to the new task TSS 10 while being associated with the BLP 110. At this time, if the T bit 130 in the new TSS 10 is on, the CPU generates a debug interrupt, turns on the task switch interrupt display bit 410 in the DSR 40, and activates the task switch debug interrupt process 510.

The task switching debug interrupt processing 510
TSS10 of the debug target task (new task) currently operating using the BLP210 in the TSS20 for interrupt processing
C, and the TDA information group 140 in the
The DAR 30 which is the hardware register of the PU is rewritten. After that, the CPU compares the generated address with the DAR 30 for each data access to the memory, and enters a mode in which an address match debug interrupt is generated when the addresses match. The task switching debug interrupt process 510 immediately exits the interrupt process when the above processes are completed.

After that, the operation of the debug target task (new task) in operation continues, but when an address match debug interrupt actually occurs, the CPU determines that the address match in the address match debug interrupt display bit 420 in the DSR 40 is the same. The Bn bit corresponding to the generated DARn (n is 0 to 3) is turned on, and then the address match debug interrupt process 520 is started.

Address match debug interrupt process 520
DSR indicates which of the trap data addresses set up to 4 generated the address match debug interrupt.
Judging from the Bn bit in 40, the contents of the memory of the own task space and the common space immediately after the data access and the contents of the hardware register are stored in the register copy area 120 of the TSS 10 and the operation of the task is suspended. To do.

In other words, at the time of task-specific data access, the intended debugging work can be started in advance while referring to the contents of the memory and the hardware register in the immediately following state. When the desired debugging work is completed, address match debug interrupt processing 520
After that, the CPU execution right is returned to the debug target multitask program.

[0024]

As described above, according to the data access stopping method of the present invention, a group of trap data address information unique to each task is stored in each task state segment, and the CPU execution right is assigned to the target task. When given, a task switching debug interrupt is generated, and by using this as an opportunity to rewrite the debug address register with a task-specific trap data address, it is possible to set a trap data address that exceeds the limit of the number of entries in the debug address register. is there.

Further, the trap data address is managed for each task, and the debug address register is updated with the intended trap data address only when the task has the execution right of the CPU. There is no need for software to ignore the generation of unnecessary address match debug interrupts.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part for explaining an embodiment of the present invention.

[Explanation of symbols]

10 TSS (task status segment) 20 TSS for interrupt processing 30 DAR (debug address register) 40 DSR (debug status register) 50 interrupt processing program 110, 210 BLP (back link pointer) 120 register copy area 130 T bit (task trap bit) ) 140 TDA information group (trap data address information group) 410 Task switching interrupt display bit (BT) 420 Address match debug interrupt display bit (B
n) 510 task switching debug interrupt processing 520 address match debug interrupt processing

Claims (1)

Claims: 1. A task status segment that stores operation history information of each task that operates in a multitask environment,
It has a task trap bit for causing the CPU to generate a task switching debug interrupt at the time of task switching, and a trap data address information group in which a trap data address for generating a data address matching debug interrupt is registered during operation of the task. , A debug address register that stores a trap data address that generates an address match debug interrupt when the CPU compares the generated address each time the memory is accessed, and causes the task switching debug interrupt and the address match debug interrupt Debug status register that stores the identification bit to identify the
When the PU detects the task trap bit, the task switching debug interrupt means that is started when the PU detects the task trap bit and rewrites the debug address register with the trap data address information group of the task state segment, and the CPU data access generation address Address match debug interrupt means that is activated when the contents of the debug address register are matched, identifies the cause of occurrence from the debug status register, and stops only the task currently occupying the CPU and operating in that state Data access stop method characterized by