JPH05347645A - Receiver - Google Patents

Abstract

PURPOSE:To detect a frequency offset of a signal subject to phase modulation accurately by detecting a peak of data of a histogram generated by a histogram generating means and outputting a frequency error component corresponding to the peak. CONSTITUTION:A differential phase discrimination error DELTAomegasTs obtained by a subtractor 3 is fed to a histogram generating circuit 11, in which a probability distribution of the differential phase discrimination error is plotted as a graph. The generated histogram data are fed to a maximum value detection circuit 12 and an area conversion circuit 13. The circuit 12 detects a maximum frequency (m) and it is fed to the circuit 13. The circuit 13 implements histogram data area conversion from the circuit 11 and converts the data into values within a range of m-(pi/4) to m+(pi/4) around the maximum frequency (m) from the circuit 12. The histogram subject to range conversion are sent to an averaging circuit 5, from which a frequency offset DELTAomega is obtained by averaging and DELTAomegais fed to an output terminal 6. Thus, the obtained frequency offset An is an accurate value in which the averaging processing in the circuit 5 is correctly implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for receiving a phase-modulated signal such as a DQPSK modulated signal.

[0002]

2. Description of the Related Art Proposed is a communication system such as a mobile telephone system which performs communication by transmitting phase-modulated digital data such as π / 4 shift DQPSK modulation (π / 4 shift / Differential / QPSK modulation). Has been done.

In the π / 4 shift DQPSK modulation, the differentiated two series of data are used as phase information by complex operation, and the phase information is combined to form a modulated signal. That is, for example, as shown in FIG. 5, two series of data (X _k , Y _k ) is converted into phase data θ _k by a four-value phase converter and transmitted. Such a π / 4 shift D
Performing QPSK modulation enables efficient transmission of digital data.

When receiving such a π / 4 shift DQPSK modulated wave, it is necessary to detect a frequency offset from the detection signal of the π / 4 shift DQPSK modulated wave and correct the received frequency by the offset. is there. An example of a conventional frequency offset detection circuit is shown in FIG. 6, in which a π / 4 shift DQPSK-modulated received signal (intermediate frequency signal) obtained at an input terminal 1 is supplied to a delay detection circuit 2 and this delay detection circuit is provided. Delay detection is performed to detect the differential phase by taking the difference from the signal delayed by the circuit 2. In this case, the differential detection processing is performed in synchronization with the symbol clock of the received signal supplied from the clock generation circuit (not shown) to the differential detection circuit 2.

Then, the detection output of the differential detection circuit 2 is
The signal is supplied to the reception signal processing circuit (not shown) in the subsequent stage for demodulation.
It is also used in the circuit for frequency offset detection.
To pay. That is, the detection output of the differential detection circuit 2 is supplied to the subtractor 3.
It is supplied to the differential phase determination circuit 4. And this differential
Differential phase supplied from the differential detection circuit 2 in the phase determination circuit 4
Is determined and the differential phase determination value (estimated value) Δθ_k′
obtain. Then, the determination value Δθ of this differential phase_k′ Is a subtractor
3 to the differential output from the detection output of the differential detection circuit 2.
Judgment value Δθ_k′ Is subtracted. This subtraction gives the differential phase
Constant error Δω_sT _s[Rad] is obtained.

FIG. 7 shows the detection state of the differential phase determination error Δω _s T _s . The difference between the differential phase Δθ _k detected by the differential detection circuit 2 and the differential phase determination value Δθ _k ′. Is the differential phase determination error Δω _s T _s . Then, the differential phase determination error Δω _s T _s is supplied to the averaging circuit 5. Then, the averaging circuit 5 averages the differential phase determination error Δω _s T _s to obtain the frequency offset value Δω. Then, the frequency offset value Δω is fed back to a reception frequency setting circuit (not shown), whereby the offset amount of the reception frequency is corrected.

[0007]

In this conventional frequency offset detection circuit, the detected frequency offset value Δ
ω may deviate from the exact frequency offset value. That is, the averaging circuit 5 averages the differential phase determination error because the differential phase determination error has variance due to noise or the like, but the differential phase determination error is phase data. The value range is limited to -π / 4 to π / 4. Here, if averaging is performed in the range of −π / 4 to π / 4, a value deviated from the accurate frequency offset value may be detected as an average value. If the frequency offset value is not detected correctly, the correction of the offset of the reception frequency cannot be performed correctly, and there is a possibility that good reception cannot be performed. For example, when a phase modulation signal transmitted in the 800 MHz band is received, a frequency offset of about ± 1.6 kHz may occur.
If the frequency offset of about kHz cannot be corrected well, the reception state deteriorates and the error rate of the reception data deteriorates.

In view of the above points, the present invention has a π / 4 shift D
An object of the present invention is to make it possible to accurately detect the frequency offset value of a phase-modulated signal such as a QPSK modulated wave.

[0009]

According to the present invention, for example, as shown in FIG. 1, a differential detection means 2 for differentially detecting a phase-modulated input signal, and a differential phase determination based on the output of the differential detection means 2. Determination means 4 for performing the above, a phase difference detection means 3 between the output of the delay detection means 2 and the determination phase of the determination means 4, a histogram generation means 11 for the phase difference detected by this phase difference detection means 3, and this histogram generation. The peak detecting means 12 for detecting the detection of the peak of the histogram data generated by the means 11 is provided, and the frequency error component corresponding to the peak detected by the peak detecting means 12 is output.

Further, in this case, the histogram generating means 1
The histogram data generated in 1 is range-converted into a value around the peak by the range conversion circuit 13, the average value of the converted values is obtained by the averaging circuit 5, and the frequency error component is output. It is a thing.

Further, according to the present invention, for example, as shown in FIG.
The output of the local oscillator 23 that determines the reception frequency is mixed with the reception signal to obtain an intermediate frequency signal, the intermediate frequency signal is subjected to delay detection by the delay detection means 2, and the differential phase is determined from the output of the delay detection means 2. Then, the phase difference between the differential detection output and the judgment phase of the differential phase is detected, the histogram data of the detected phase difference is obtained, the peak of the histogram data is detected, and the frequency corresponding to this detected peak is detected. An error component is obtained, and the oscillation frequency of the local oscillator 23 is corrected by this frequency error component.

[0012]

According to the present invention, the frequency error component (frequency offset value) can be accurately detected based on the histogram. In this case, it is possible to detect more accurately by converting the range into a value centering on the peak.

Further, according to the present invention, the oscillation frequency of the local oscillator that determines the reception frequency is corrected by the frequency error component accurately detected based on the histogram, so that the reception frequency can be set accurately.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4, parts corresponding to those in FIGS. 5 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, π / 4 shift DQPSK
This circuit is applied to a frequency offset detection circuit of a transceiver as a terminal of a wireless telephone system that receives and transmits modulated data, and its circuit configuration is shown in FIG.
In this example, the reception signal (intermediate frequency signal) obtained at the input terminal 1 is subjected to delay detection by the delay detection circuit 2 and then the detection output is supplied to the subtractor 3 and the differential phase determination circuit 4 for differential phase detection. The determination circuit 4 determines the differential phase supplied from the differential detection circuit 2, and supplies the differential phase determination value Δθ _k ′ to the subtractor 3. Then, the subtractor 3 subtracts the determination value of the differential phase from the detection output of the differential detection circuit 2. By this subtraction, the differential phase determination error Δω _s T _s [rad] is obtained. Up to this point, the circuit is the same as the circuit shown in FIG. 6 as a conventional example.

In this example, the differential phase determination error Δω _s T _s is supplied to the histogram creating circuit 11. The histogram creation circuit 11 performs a process of graphing the probability distribution (frequency distribution) of the differential phase determination error. For example, a histogram is created as shown in FIG. In this case, the data is a phase error, so −π
A histogram is created in the range of / 4 to π / 4.

Then, the created histogram data is supplied to the maximum value detection circuit 12 and the range conversion circuit 13.
The maximum value detection circuit 12 detects a value m having the maximum frequency from the supplied histogram data, and sets the detected maximum value m as a frequency error component ΔωT _s (see FIG. 3). Then, the data of the detected maximum value m is supplied to the range conversion circuit 13. The range conversion circuit 13 performs range conversion of the histogram data supplied from the histogram creation circuit 11. At this time, the maximum value detection circuit 1
Centering on the maximum value m supplied from 2, m- (π /
4) to m + (π / 4) are converted. For example, the histogram shown in FIG. 3 is range-converted into the histogram shown in FIG. Then, the range-converted histogram data is supplied to the averaging circuit 5, the frequency offset value Δω is obtained by averaging in the averaging circuit 5, and the result is supplied to the output terminal 6. In the following description, the circuit from the output section of the differential detection circuit 2 to the averaging circuit 5 will be referred to as the frequency offset detection circuit 10.

The frequency offset value Δ thus obtained
ω is an accurate value for which the averaging circuit 5 has performed averaging correctly. That is, in the conventional circuit shown in FIG. 6, since the differential phase determination error is averaged as it is, the average value is the maximum value m due to the influence of the data in the vicinity of −π / 4 shown in the range x in the histogram of FIG. However, the accurate frequency offset value Δω could not be detected. On the other hand, in the configuration of this example, m-
Since the histogram of FIG. 4 is centered around the maximum value m of (π / 4) to m + (π / 4), values in the vicinity of the maximum value m in the averaging by the averaging circuit 5 are average values (that is, The frequency offset value Δω) is obtained, and the accurate frequency offset value Δω can be detected.

Although the value averaged by the averaging circuit 5 is set as the frequency offset value Δω here, the maximum value detecting circuit 12 can be seen from the histogram of FIG.
Since the maximum value m detected in step 2 is almost the same as the frequency offset value Δω, if the detection accuracy of the maximum value detection circuit 12 is good, the detection output of the maximum value detection circuit 12 is set to the frequency offset value Δω. Thus, the range conversion circuit and the averaging circuit may be omitted.

Next, FIG. 2 shows a configuration in which the transmission / reception frequency is corrected by the frequency offset value Δω detected in this way. The terminal of this example receives the signal (π / 4 shift) from the antenna 21. DQPSK modulated wave) mixer 22
And the mixer 22 mixes the reception channel selection frequency signal supplied from the local oscillator 23 with the reception signal to form the reception signal as an intermediate frequency signal. In this case, the reception frequency is determined by the oscillation frequency of the local oscillator 23, and this oscillation frequency is controlled by the control data supplied from the transmission / reception frequency control circuit 29 described later.

Then, the intermediate frequency signal output from the mixer 22 is supplied to the delay detection circuit 2, and the signal delay-detected by the delay detection circuit 2 is received via the reception data input terminal 24 to the reception signal processing circuit in the subsequent stage. (Not shown).

Further, the transmission signal obtained at the transmission data output terminal 25 is supplied to the modulation circuit 26, and the π / 4 shift DQP is supplied.
This is a SK modulated wave, and this π / 4 shift DQPSK modulated wave is supplied to the mixer 27. Then, the frequency signal for transmission channel selection output from the local oscillator 27 is supplied to the mixer 27 to be a transmission signal modulated into a predetermined transmission channel, and this transmission signal is wirelessly transmitted from the antenna 21.
In this case, the oscillation frequency of the local oscillator 27 is controlled by the control data supplied from the transmission / reception frequency control circuit 29 described later. The reception frequency and the transmission frequency may be the same (that is, the oscillation frequency of the local oscillator 23 and the oscillation frequency of the local oscillator 27 may be the same).

In this example, the signal detected by the delay detection circuit 2 is detected by the frequency offset detection circuit 10.
Supply to. The frequency offset detection circuit 10 has the configuration shown in FIG. 1 described above, and supplies the frequency offset value Δω detected by the frequency offset detection circuit 10 to the transmission / reception frequency control circuit 29. The transmission / reception frequency control circuit 29 outputs control data for shifting the oscillation frequencies of the local oscillators 23 and 27 by the amount corresponding to the supplied frequency offset value Δω, and outputs the local oscillator 2
The oscillation frequencies at 3 and 27 are shifted to correct the reception frequency and the transmission frequency.

By correcting the reception frequency and the transmission frequency in this way, the reception frequency becomes an accurate frequency, and it becomes possible to accurately receive the signal transmitted by being π / 4 shift DQPSK modulated. .. Further, since the offset amount of the transmission frequency is the same as the offset amount of the normal reception frequency, the transmission frequency can be accurately adjusted to the specified frequency by simultaneously performing the correction of the transmission frequency as in the above embodiment. , Good transmission is possible.

In the above embodiment, the present invention is applied to a receiver for receiving π / 4 shift DQPSK modulated digital data, but it is also applicable to a circuit for receiving other phase modulated data and detecting a frequency offset. Applicable.

[0026]

According to the present invention, the frequency offset value of the received signal can be detected accurately based on the histogram, and the received frequency can be set accurately. In this case, the frequency offset value can be detected more accurately by performing the range conversion to a value centered on the peak and then the frequency offset value can be detected more accurately, thereby enabling more accurate reception control.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a terminal device to which the circuit of the embodiment is applied.

FIG. 3 is a waveform chart provided for explaining one embodiment.

FIG. 4 is a waveform chart provided for explaining one embodiment.

FIG. 5 is an explanatory diagram showing π / 4 shift DQPSK modulation.

FIG. 6 is a configuration diagram showing an example of a conventional frequency offset detection circuit.

FIG. 7 is an explanatory diagram showing a differential phase detection state.

[Explanation of symbols]

 2 Delay detection circuit 4 Differential phase determination circuit 5 Averaging circuit 10 Frequency offset detection circuit 11 Histogram creation circuit 12 Maximum value detection circuit 13 Range conversion circuit

Claims (3)

[Claims] 1. A differential detection means for differentially detecting a phase-modulated input signal, a determination means for determining a differential phase from an output of the differential detection means, an output of the differential detection means and a determination of the determination means. And a phase difference detecting means for detecting a phase difference, a histogram generating means for detecting the phase difference detected by the phase difference detecting means, and a peak detecting means for detecting a peak of the histogram data generated by the histogram generating means. A receiving device configured to output a frequency error component corresponding to a peak detected by a peak detecting means. 2. The receiving apparatus according to claim 1, wherein the histogram data is subjected to range conversion into a value centered on the peak, an average value of the converted values is obtained, and a frequency error component is output. 3. An intermediate frequency signal is obtained by mixing an output of a local oscillator for determining a reception frequency with a reception signal, the intermediate frequency signal is subjected to delay detection by delay detection means, and a differential phase signal is output from the output of the delay detection means. Judgment is performed, the phase difference between the differential detection output and the judgment phase of the differential phase is detected, the histogram data of the detected phase difference is obtained, the peak of the histogram data is detected, and the detected peak is detected. A receiving device adapted to obtain a frequency error component corresponding to and correct the oscillation frequency of the local oscillator by the frequency error component.