JPH05347545A - Output buffer for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the noises occurring on a power line included in a semiconductor integrated circuit of a buffer which is driven by a large current. CONSTITUTION:A P-channel MOS transistor TR P11 set at the final stage of an output buffer is connected in parallel with an auxiliary P-channel MOS TR P12. Meanwhile, an N-channel MOS TR N11 is connected in parallel with an auxiliary N-channel MOS TR N12. An auxiliary control circuits G12 and G13 consist of the delay circuits which control those auxiliary MOS TRs and NAND or NOR gates. In such a constitution, an error is produced between the driving periods of the TR P11 and N11 or TR P12 or N12. So that, the output terminal voltage slowly rises or falls and then, the potential fluctuation of a power line caused in a semiconductor integrated circuit by the charging/ discharging current of the load capacity can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer of a semiconductor integrated circuit, and more particularly to an output buffer for driving a load capacitance in a signal output section of a semiconductor integrated circuit which operates with a large current.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional output buffer. The output buffer of FIG. 4 receives an input signal I41 via a drive circuit G41 composed of an inverter 401,
A P-channel MOS transistor P41 connected between the first power supply (hereinafter referred to as VDD) and the output terminal O41.
And an N-channel MOS transistor N4 connected between the second power source (hereinafter referred to as GND) and the output terminal G41.
1 is complementarily switched to drive the load. The geometrical dimensions of the final-stage MOS transistor and the MOS transistor forming the drive circuit G41 depend on the delay time until the level of the output terminal O41 reaches a predetermined value and the current drivability according to the change of the input signal I41. It is determined.

FIG. 5 is a circuit diagram showing a conventional output buffer used in a bidirectional input circuit such as a data bus. In FIG. 5, the inverter 501, the NAN
A drive circuit G51 including a D gate 502 and a NOR gate 503 and controlled by an output control input signal E51.
Through a P-channel MOS transistor P51 connected between the first power supply VDD and the output terminal O51, and a N-channel MOS transistor N51 connected between the second power supply GND and the output terminal O51 in a complementary manner. It is the one that is switching and driving the load. The difference between the output buffer of FIG. 5 and the output buffer of FIG. 4 is that the output buffer has an output control input signal E51, and the output terminal O
51 can be switched between a drive state in which one of the P-channel MOS transistor P51 and the N-channel MOS transistor N51 is in a conductive state and a high impedance state in which both are in a non-conductive state. The difference in the circuit configuration is that the NAND gate 50 in the drive circuit G51 is
2 and the NOR gate 503 are used to realize the state switching of the output terminal O51.

[0004]

In the power supply line in the semiconductor integrated circuit, the potential due to the resistance components R1 and R2 and the inductance components L1 and L2 of the power supply line due to the charging / discharging current of the load capacitance when the output signal changes. Fluctuations occur,
Noise is generated. In the output buffer that drives a large current, the MOS transistor that configures the final stage and the drive circuit has a small source-drain resistance when conducting, so in a semiconductor integrated circuit equipped with an output buffer, There is a problem in that a malfunction occurs due to noise generated in the power supply line in the circuit.

[0005]

An output buffer according to the present invention comprises a first P-channel MOS transistor having a source and a drain connected between a first power supply VDD and an output terminal, and a second power supply GND. A first N-channel M having a source and a drain connected between the output terminal and the output terminal, respectively.
An OS transistor, and the first P-channel MO
In the output buffer of the semiconductor integrated circuit, in which the S transistor and the first N-channel MOS transistor are complementarily controlled to be conductive in accordance with the level of the input signal to drive the load connected to the output terminal, P channel MO
A second P-channel MOS transistor having a source and a drain connected in parallel with the S-transistor between a first power supply VDD and an output terminal, and the first N-channel M.
A second N having a source and a drain respectively connected between the second power supply GND and the output terminal in parallel with the OS transistor.
A channel MOS transistor and a gate of the second P-channel MOS transistor, which are connected to the first P-channel MOS transistor when the rising edge of the input signal changes.
Delay circuit and NAN, which determines the conduction period of the transistor
A first auxiliary control circuit composed of a D gate;
Second N-channel MOS transistor connected to the gate of the first N-channel MOS transistor and different from the conduction period of the first N-channel MOS transistor when the input signal falls.
A delay circuit and a second auxiliary control circuit composed of a NOR gate for determining the conduction period of the channel MOS transistor are provided.

[0006]

1 is a circuit diagram of an output buffer according to a first embodiment of the present invention, and FIG. 2 is an operation waveform diagram thereof. A first P-channel MOS transistor P11 having an output conduction resistance set between the first power supply VDD and the output terminal O11 so that the output terminal voltage gradually rises when the load capacitance is charged.
(Hereinafter referred to as P11) are connected, GND and output terminal O
A first N-channel MOS transistor N11 (hereinafter referred to as N11) whose output conduction resistance is set so that the output terminal voltage falls gently when the load capacitance is discharged is connected between the nodes 11. The drive circuit G1 in which the input signal I11 is composed of the inverter 101 is applied to the gates of P11 and N11.
1 (hereinafter referred to as G11). A second P-channel MOS transistor P12 (hereinafter referred to as P12) whose output conduction resistance is set so that a large current can be driven when the output terminal is at a high level is connected in parallel with P11 between VDD and the output O11. .. The gate of P12 has a first auxiliary control circuit G12 (hereinafter referred to as G12) that generates a delay signal when the rising edge of the input signal I11 changes.
Output is being supplied. G12 is a delay circuit D11 that delays the input signal I11, and its output and input signal I11.
It is composed of a NAND gate 102 for inputting. A second N-channel MOS transistor N12 (hereinafter referred to as N12) whose output conduction resistance is set so that it can drive a large current when the output terminal is at low level is connected to GND and the output terminal O1.
1 is connected in parallel with N11. The output of a second auxiliary control circuit G13 (hereinafter referred to as G13) that generates a delay signal when the input signal I11 falls is supplied to the gate of N12. G13 is an input signal I11
Delay circuit D12 for delaying, and its output and input signal I
It is composed of a NOR gate 103 for inputting 11.

In the operation of the output buffer of the present invention, when the input signal I11 changes from the low level to the high level, the gates of P11 and N11 change from the high level to the low level via G11. Is on, N
11 is turned off. The gate of N12 via G13 changes from a high level to a low level when the input signal I11 rises, and N12 is turned off. The gate of P12 changes from the high level to the low level via G12 with a delay from the rise of the input signal I11, and P12 is turned on with a delay from P11. Therefore P
11 and P12 are in the conduction period, and the output terminal O11
Rises slowly. On the other hand, the input signal I11 is high
When the level changes to the low level, the gates of P11 and N11 change from the low level to the high level via G11, so that P11 is turned off and N11 is turned on. The gate of P12 via G12 changes from the low level to the high level when the input signal I11 falls, and P12 is turned off. The gate of N12 changes from the low level to the high level via G13 later than when the falling edge of the input signal I11 changes.
It turns on later than 11. Therefore, a gap occurs between the conduction periods of N11 and N12, and the output terminal O11 falls gently. As a result, it is possible to reduce the potential fluctuation that the charge / discharge current of the load capacitance gives to the power supply line in the semiconductor integrated circuit.

FIG. 3 is a circuit diagram of an output buffer according to the second embodiment of the present invention. The basic configuration is the same as that of the circuit of the first embodiment, but the drive circuit G31 for driving the first P-channel MOS transistor P31 inputs the input signal I31 and the output control input signal E31 to the NAND gate 303.
And includes a first N-channel MOS transistor N
The drive circuit G32 for driving 31 is composed of an input signal I31 and a NOR gate 304 to which a signal from the output control input signal E31 via the inverter 301 is input.
The first auxiliary control circuit G33 for driving the second P-channel MOS transistor P32 includes a delay circuit D31 for delaying the input signal I31, a 3-input NAND to which the output signal, the input signal I31 and the output control input signal E31 are input. It is composed of a gate 302. Second N channel MO
The second auxiliary control circuit G34 that drives the S transistor includes a delay circuit D32 that delays the input signal I31, its output signal and input signal I31, and an output control input signal E3.
It is composed of a 3-input NOR gate 305 to which a signal from 1 is input via the inverter 301. The operation of this embodiment is similar to that of the first embodiment when the control signal E31 is at high level, and P31 and P3 when it is at low level.
2, N31 and N32 are turned off.

[0009]

As described above, according to the present invention,
A second MOS transistor is connected in parallel with the first MOS transistor, and the gate of the second MOS transistor has a delay circuit and a NAND gate or N gate depending on the input signal.
By connecting through an auxiliary control circuit composed of an OR gate and determining the driving period of the second MOS transistor different from the driving period of the first MOS transistor, a charging / discharging current of the load capacitance is generated in the power supply line. The potential fluctuation can be reduced.

[Brief description of drawings]

FIG. 1 is an output buffer circuit diagram of a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the first embodiment of the present invention.

FIG. 3 is an output buffer circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a conventional output buffer circuit diagram.

FIG. 5 is a conventional output buffer circuit diagram for a bidirectional input / output circuit.

[Explanation of symbols]

101, 301, 401, 501 Inverter 102, 302, 303, 502 NAND gate 103, 304, 305, 503 NOR gate P11, P12, P31, P32, P41, P51
P-channel MOS transistors N11, N12, N31, N32, N41, N51
N-channel MOS transistor I11, I31, I41, I51 Input signal E31, E51 Output control input signal O11, O31, O41, O51 Output terminal D11, D12, D31, D32 Delay circuit G11, G31, G32, G41, G51 Driving circuit G12 , G33 First auxiliary control circuit G13, G34 Second auxiliary control circuit VDD First power supply GND Second power supply R1, R2 Parasitic resistance component of power supply line L1, L2 Parasitic inductance component of power supply line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (1)

[Claims] 1. A first P-channel MOS transistor having a source and a drain connected between a first power supply and an output terminal respectively, and a source and a drain respectively connected between a second power supply and an output terminal. A first N-channel MOS transistor, wherein the first P-channel MOS transistor and the first N-channel MOS transistor are complementarily conductively controlled according to the level of an input signal and connected to an output terminal. In a semiconductor integrated circuit output buffer for driving a load, a second P-channel MOS transistor connected between a first power source and an output terminal in parallel with the first P-channel MOS transistor, and the first P-channel MOS transistor. N
A second N-channel MOS transistor connected in parallel between the second power supply and the output terminal in parallel with the channel MOS transistor, and a gate of the second P-channel MOS transistor are connected to each other when the rising edge of the input signal changes. And a first auxiliary control circuit composed of a delay circuit and a NAND gate for determining a conduction period of a second P-channel MOS transistor different from the conduction period of the first P-channel MOS transistor, and the second N-channel. A delay circuit and a NOR gate connected to the gate of a MOS transistor to determine a conduction period of a second N-channel MOS transistor which is different from the conduction period of the first N-channel MOS transistor when the input signal falls. And a second auxiliary control circuit configured by Output buffer of the road.