JPH0533245U - Division arithmetic circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Divide that evaluates the input data of the dividend and divisor, changes the load position of the dividend based on the result, reduces the number of operation clocks, and can execute the division operation at high speed. It is to realize an arithmetic circuit. [Structure] A zero count circuit A11 counts 0's in the upper bits of the dividend data, a zero count circuit B12 counts the number of 0's in the upper bits of the divisor data, and the load data generation circuit 13 determines the partial remainder register based on this. 2 to generate data to be loaded into the dividend register 3 and the dividend register 3,
A data load position signal is sent to the operation control circuit 1 to recognize the number of operation clocks for completing the operation. The partial remainder data control circuit 14 loads the load data generation circuit 1 at the time of loading.
The data of No. 3 is sent to the partial remainder register 2 as the partial remainder data of the arithmetic circuit 12 at the time of calculation. The arithmetic circuit 4 performs a division operation on the dividend data and the divisor data.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a division operation circuit in a microprocessor, and more particularly to a division operation circuit that can realize a division operation at high speed by evaluating the value of input data.

[0002]

[Prior Art]

 As shown in FIG. 3, a division operation circuit using a conventional shift register has an operation control circuit 1 for controlling the operation of a division operation, a partial remainder register 2 for holding a partial remainder, and a dividend by one bit from the upper bit. A dividend shift register 3 to be sent to an arithmetic circuit, an arithmetic circuit 4 for obtaining a partial remainder or a remainder and a 1-bit quotient, and a commercial shift register 5 for holding quotient data obtained by the arithmetic circuit 4 from the upper bits one by one. It was composed.

Here, the input data A that is the dividend is input to the shift register 3 for the dividend, and the input data B that is the divisor is input to the arithmetic circuit 4. Here, the operation of the conventional division operation circuit will be described by dividing the operation using an actual number. When the activation signal is input to the operation control circuit 1, the operation control circuit 1 outputs a load signal, clears the partial remainder register 2, and loads the dividend data shift register 3 with the input data A. Then, after a predetermined number of clocks, the calculation results of the quotient and the remainder are output as output data Q and output data R, respectively.

It is assumed that the input data A is “1101” and the input data B is “0101”. It is assumed that the output data of the partial remainder register 2 is a, the output data of the dividend shift register 3 is b, and the input data B is c. Since the partial remainder register 2 is cleared, its data is "0000" and a is the output "000" which is shifted to the left. “B” is a high-order bit stored in the dividend shift register 3 and “1” is output and combined in the arithmetic circuit 4 to be “0001”. Since this is compared with "0101" of the data c and a <c, "0" of the signal f is stored in the commercial shift register 5, "0001" is output as the output data d, and feedback to the partial remainder register 1 is performed. To be done.

At the next clock, the partial remainder register 2 shifts the fed back data “0001” to the left and outputs “001” as a, and the dividend shift register 3 shifts the leftmost bit to “1”. Is combined with "to produce" 0011 ". This is compared with the c data "0101", and since a <c, "0" is stored in the commercial shift register 5 and "0011" is fed back to the partial remainder register 2.

In this way, in the next clock, in the arithmetic circuit 4, since a ≧ c, the subtraction between “01 10” and “0101” is performed, and the d data becomes “0001” and the partial remainder is obtained. The value is fed back to the commercial register 2 and “1” is stored in the commercial shift register 5. Similarly, the fourth operation is performed, "0010" is stored in the commercial shift register 5, and the remainder "0011" is output from the arithmetic circuit 4. The operation is ended by recognizing that the operation has been performed a prescribed number of times by four operations, and the quotient “0010” is output as the output data Q and the remainder “0011” is output as the output data R.

[0007]

[Problems to be solved by the device]

 By the way, in the above-mentioned conventional division arithmetic circuit, regardless of the dividend and the divisor, the arithmetic time of the predetermined number of clocks is always required, and the unnecessary arithmetic operation is performed for the dividend with many 0s.

The present invention has been made in view of the above points, and an object thereof is to evaluate input data of a dividend and a divisor, and change a load position of the dividend based on the result to reduce the number of operations and perform division. It is to realize a division operation circuit that can execute an operation at high speed.

[0009]

Means for Solving the Problems The present invention, which solves the above-mentioned problems, includes an arithmetic circuit for calculating input dividend data and divisor data and outputting partial remainder data including a quotient 1 bit and remainder data. , A commercial shift register that holds each 1-bit quotient output from the arithmetic circuit and outputs the quotient at the end of the operation, and loads the input dividend data and shifts the arithmetic circuit by 1 bit from the high-order bit at each operation. In the division arithmetic circuit having a shift register for dividend and a register for partial remainder holding the partial remainder data of the operation result, the values of the input dividend data and divisor data are evaluated at the time of loading, Based on the evaluation result, the constituent bits of the input data are appropriately divided and loaded, and the data load position signal indicating the position of the data load is output and the operation is performed. Includes a data control circuit for feeding back an output obtained by feeding back the partial remainder data output of the arithmetic circuit bit by bit to the partial remainder register, a shift register for the dividend by the activation signal input, and the data control circuit. An operation control circuit that sends a load signal to the data control circuit, receives a data load position signal from the data control circuit, counts the number of clocks until completion of the operation, and outputs an operation completion signal. Is.

[0010]

[Action]

 When the activation signal is input, the operation control circuit outputs a load signal to load the dividend shift register and the data control circuit with data. At the time of loading, the data control circuit evaluates the dividend data and the divisor data, divides the dividend into the partial remainder register and the dividend shift register, loads them, and sends a data load position signal to the operation control circuit. The arithmetic circuit synthesizes the output signals of the partial remainder register and the dividend register to obtain dividend data, calculates the difference from the divisor data, and outputs a 1-bit quotient and partial remainder data. The partial remainder data is fed back to the partial remainder register via the data control circuit, and the operation is continued at the next clock. The operation control circuit grasps the required number of operation clocks by the data load position signal and outputs an operation completion signal when the operation is completed.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a division operation circuit according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals. In the figure, 11 is a zero count circuit A that counts the number of 0s to the first 1 of 8-bit input data A that is a dividend, and 12 is the first 1 of 8-bit input data B that is a divisor. It is a zero count circuit B that counts the number of 0s up to.

The number of 0s obtained by the zero count circuit A 11 (j) and the number of 0s obtained by the zero count circuit B 12 (i) are input to 13 and the following equation is calculated. . p = j + (8-i-1) ……………… (1) Input the input data A separately input from this operation result to the partial remainder register 2 and dividend shift register 3 and load it. The load data generating circuit sends a data load position signal to the operation control circuit 1 to generate a data load position signal for notifying the load position of the input data A.

Reference numeral 14 denotes a partial remainder data control circuit that sends the data sent from the load data generation circuit 13 to the partial remainder register 2 at the time of data loading, and sends the partial remainder data output of the arithmetic circuit 4 to the partial remainder register 2 at the time of calculation. Is.

Reference numeral 15 is a data control circuit for controlling the data to which the input data A and the input data B are input and which is sent to the partial remainder register 2 and the dividend shift register 3. The data control circuit 15 includes a zero count circuit A11 and a zero count circuit B12. , A load data generation circuit 13 and a partial remainder data control circuit 14.

Next, the operation of the embodiment configured as described above will be described with reference to the time chart of FIG. Before going into the explanation here, FIG. 2 will be explained. (A) is a clock waveform that is input from a CPU (not shown) and serves as a reference for the operation of the circuit, (b) is the input data A of the dividend consisting of 8 bits, and (c) is also the 8-bit divisor. This is the input data B.

(D) is a start signal waveform input from an external control circuit (not shown) based on the clock. (E) is the data stored in the partial remainder register 2, (f) is the data stored in the dividend shift register 3, and the (e) and (f) data make up the 16-bit dividend. .

(G) is the quotient data that is input to the commercial shift register 5 by the arithmetic circuit 4 while shifting the quotient of the arithmetic result by 1 bit, and appears as output data Q. (H) is the remainder data stored in the partial remainder register 2 as a partial remainder each time one bit is calculated, and appears as output data R. (I) is the operation completion signal sent to the external control circuit at the end of the operation.

The input data A is “00110101” as shown in FIG. 2B, and the input data B is “00001010” as shown in FIG. The input data A is input to the zero count circuit A11 at the rising edge of the clock by the input of the start signal (d), and the zero count circuit A11 counts the number "0" of 0 until the first 1 appears. Further, the input data B is input to the zero count circuit B12, and the zero count circuit B12 counts the number "0" of 0 until the first 1 appears. This data is input to the load data generation circuit 13, and the operation of the equation (1) is performed to obtain the shift number p = 5.

On the other hand, the input data A is also directly input to the load data generation circuit 13. The load data generation circuit 13 shifts "00110101" of the input data A to the left by 5 bits based on the shift number p = 5 and stores it in the partial remainder register 2 through the partial remainder data control circuit 14. At this time, in order to make the input data 8 bits, three 0s are added to the upper order and stored as "00000110" ((e) in FIG. 2). In the dividend register 3, the remaining "101" of the input data is stored as "10100000" by adding 5 bits of 0 to the lower order to make it 8 bits. F)).

Subsequent operations are performed as described with reference to FIG. 3, and the first operation compares the dividend “00001101” with the divisor “00001010” in the arithmetic circuit 4 and outputs the quotient “1”. Is input, and the remainder “00000011” is fed back to the partial remainder data control circuit 14. The partial remainder data control circuit 14 outputs the residual data from the arithmetic circuit 4 to the partial remainder register 2 since it is in operation (a ₂ ). This is combined with the data of the register 3 for the dividend (data b _{2 obtained} by shifting the data b ₁ to the left by 1 bit) to become “00 000110”, and compared with the divisor ((c)), the quotient becomes “0”. Become. Similarly, in the third calculation, the quotient “00000101” shown in c ₃ of (g) and the remainder “0000 0011” shown in d _{3 of} (h) are output.

The calculation clock number v is obtained by the following equation from the shift number p obtained by the equation (1). v = 8-p (2) The operation control circuit 1 recognizes the number of operation clocks from the input data load position signal by the equation (2), and when the number of operation clocks is reached, Then, the calculation completion signal of (i) in FIG. 2 is output to complete the calculation.

As described above, according to the present embodiment, a data control circuit is added to the conventional division arithmetic circuit, the number of zeros in the upper bits is counted by the zero count circuit, and the dividend data is calculated according to the value of the number of zeros. By changing the load position of, unnecessary operations can be omitted and division operations can be performed at high speed.

Now, assuming that the number of bits is n, the number of high-order 0s in the divisor is i, and the number of high-order 0s in the dividend is j, calculation is performed faster than the conventional division circuit by the number of clocks m represented by the following equation. can do.

From the equation (1), when m = n-1-i + j i ≧ j, when m = n-1 i <j (When the divisor is large, the calculation only needs to be performed once.)

[0025]

[Effect of the device]

 As described in detail above, according to the present invention, the input data of the dividend and the divisor are evaluated, and the load position of the dividend is changed based on the result, so that unnecessary calculation can be omitted and high-speed calculation can be performed. It becomes possible, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of calculation by the circuit of the embodiment.

FIG. 3 is a block diagram of a conventional division arithmetic circuit.

[Explanation of symbols]

 1 Operation Control Circuit 2 Partial Remainder Register 3 Dividend Shift Register 4 Arithmetic Circuit 15 Data Control Circuit

Claims (1)

[Scope of utility model registration request] 1. An arithmetic circuit (4) for arithmetically operating inputted dividend data and divisor data to output partial remainder data including a quotient 1 bit and remainder data, and a quotient output from the arithmetic circuit (4). A commercial shift register (5) that holds each 1 bit and outputs a quotient at the end of the operation, and the input dividend data is loaded and the data shifted by 1 bit from the upper bit is sent to the operation circuit (4) each time the operation is performed. In a division arithmetic circuit having a dividend shift register (3) and a partial remainder register (2) for holding the partial remainder data of the operation result, the values of the input dividend data and divisor data are evaluated at the time of loading, The constituent bits of the input data are appropriately divided and loaded based on the evaluation result, and a data load position signal indicating the position of the data load is output. It is partial remainder data output feedback of the road (4) 1
A data control circuit (15) for sending an output shifted bit by bit to the partial remainder register (2); and a shift register (3) for the dividend upon activation signal input.
And a load signal to the data control circuit (14),
An operation control circuit (1) which receives a data load position signal from the data control circuit (15) and counts the number of clocks until the completion of operation and outputs an operation completion signal. .