JPH053316A - Mis type transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a MIS type transistor and its manufacturing method which is suitable for a process for making a contact with self-alignment, for which a conductive material can be used for the first gate side wall, which has a resistance to a hot electron degradation and in which a parasitic capacitance of a wiring running on a gate and of a gate electrode is small. CONSTITUTION:As for a MOS transistor, when a gate electrode 3 is applied with a voltage, an electric current flows between a source and a drain of an n-type high concentrated diffused layer 9, and at that time, first gate side wall 5 made of a polysilicon which is a high inductor material covers an n-type low concentrated diffused layer 8 so as to overlap the n-type high concentrated diffused layer 9, resulting in mitigated horizontal electric field near the drain for suppressed degradation of a hot electron. If the gate electron 3 is applied with no voltage, an electric current does not flow between the source and the drain of the n-type high concentrated diffused layer 9, thus functioning as a switch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS transistor in the field of ultra-high density LSI technology and a method for manufacturing the same.

[0002]

2. Description of the Related Art In ultra-integrated circuit devices, so-called VLSIs, hot electron deterioration and parasitic capacitance of devices due to high electric fields have become important problems with miniaturization of MIS transistors. Further, it is necessary to manufacture in a self-aligned manner for miniaturization. Therefore, various structures have been proposed to solve this problem. An example of a conventional MIS type transistor device is, for example, IEEE ELECTRONDEVIC.
There is a MOS transistor described in E LETTERS, VOL.11, NO.2, 1990, p.78-81.

FIG. 2 is a sectional view of this MOS transistor. In FIG. 2, 21 is a P-type semiconductor substrate. Two
2 is a gate oxide film on the P-type semiconductor substrate 21, 23 is an N-type polysilicon gate electrode formed on the gate oxide film 22, and 24 is an N-type polysilicon gate electrode 23 in the element region.
Is a thin oxide film that is formed to cover the thin oxide film 25 is a thin oxide film 2
4, a polysilicon gate side wall formed on 4, a N type low concentration diffusion layer formed on the P type semiconductor substrate 21, and 27 an N type high concentration diffusion layer formed on the P type semiconductor substrate 21. Further, 28 is a passivation film on the device, and 29 is a wiring running on the passivation film 28.

The reported M configured as described above
In the OS transistor device, when a voltage is applied to the N-type polysilicon gate electrode 23, the N-type high concentration diffusion layer 27
A current flows between the source and drain of the device, and at that time, the high electric field near the drain is relaxed by the polysilicon gate sidewall 25 having a high dielectric constant (having a dielectric constant about three times that of a silicon oxide film which is a normal gate sidewall). Suppresses hot electron deterioration. If no voltage is applied to the N-type polysilicon gate electrode 23, no current flows between the source and drain of the N-type high-concentration diffusion layer 27, and the N-type polysilicon gate electrode 23 operates as a switch.

[0005]

However, in the above structure, since the polysilicon gate side wall 25 of the conductor is used, when the contact is made in self-alignment, the polysilicon gate side wall 25 runs on the wiring. Short with 29. Therefore, after forming the polysilicon gate side wall 25, a passivation film 28 is deposited on the side wall 25, and then a contact hole is formed by mask alignment to make contact between the N-type high concentration diffusion layer 27 and the wiring 29. Will be needed.

Further, a step (for example, an element isolation end) is formed in the element region.
If there is, the polysilicon gate side wall 25 of the conductor remains as an etching residue in that portion, which causes miswiring. Further, in order to prevent the erroneous wiring and the short circuit, as shown in FIG. 2, it is necessary to cover the passivation film 28 thereon, which is not suitable for miniaturization. On the other hand, since the high dielectric polysilicon gate side wall 25 is used, the parasitic capacitance C between the wiring 29 running on the gate and the N-type polysilicon gate electrode 23 is increased, which causes a problem that the switching speed of the MOS transistor is delayed. Was there.

In view of the above point, the present invention is suitable for the step of making a contact for self-alignment, moreover, a conductive type material can be used for the first side wall of the gate, is resistant to hot electron deterioration, and further runs on the gate. It is an object of the present invention to provide a MIS transistor having a small parasitic capacitance between a wiring and a gate electrode and a manufacturing method thereof.

[0008]

According to the present invention, there is provided a gate insulating film and a gate electrode selectively formed on a first conductivity type semiconductor substrate, and an insulation provided on the gate electrode side portion and the semiconductor substrate. A first gate sidewall layer having a higher dielectric constant than the insulating film and lower than the height of the gate electrode, and an insulating film covering the first gate sidewall. A MIS transistor having a second gate sidewall layer.

The present invention also provides a step of forming a gate insulating film on one main surface of the first conductivity type semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and the gate electrode and the semiconductor substrate. A step of depositing a first insulating film, a step of depositing a first gate sidewall layer having a higher dielectric constant than the first insulating film, and an etching method having a strong anisotropy in the vertical direction, Selectively etching the first gate sidewall layer to allow the first gate sidewall layer to remain below the gate electrode height in a self-aligned manner on the side portion of the gate electrode; A MIS-type transistor including a step of depositing a second insulating film and a step of leaving the second insulating film so as to cover the first gate sidewall by an etching method having a strong anisotropic in the vertical direction. Manufacturing of It is the law.

[0010]

According to the present invention, the high electric field in the vicinity of the drain is relaxed by the first gate side wall layer having a high dielectric constant having the above-described structure, is resistant to hot electron deterioration, and is protected by the second gate side wall layer made of an insulating film. It is possible to separate the high-concentration diffusion layer and make a contact for self-alignment, and it is possible to reduce the parasitic capacitance of the wiring running on the gate and the gate electrode.

[0011]

(Embodiment 1) FIG. 1 is a sectional view of a MIS transistor according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 is a P-type silicon substrate. 2 is a gate oxide film on the P-type silicon substrate 1, 3 is a polysilicon gate electrode on the gate oxide film 2, 4 is a thin oxide film formed on the side surface of the gate electrode 3 and the silicon substrate 1, and 5 is a thin oxide film. A first gate side wall (eg, polysilicon) formed on 4 is an insulating film (eg, HTO film) 6 formed on the gate electrode 3, and 7 is formed so as to cover the first gate side wall 5. Second gate sidewall oxide film (eg HT
O film), 8 is an N-type low concentration diffusion layer formed on the P-type semiconductor substrate 1, 9 is an N-type high concentration diffusion layer formed on the P-type semiconductor substrate 1, and 10 is an Al wiring.

The feature of the structure of this embodiment is that the side wall of the gate electrode 3 is composed of two layers, that is, a first gate side wall made of a high dielectric material and a second gate side wall. is there. Further, the first gate sidewall made of a high dielectric material covers the low concentration diffusion layer. With these configurations, hot electron deterioration of the transistor can be prevented.

The MO of this embodiment configured as described above
In the S-transistor, when a voltage is applied to the gate electrode 3, a current flows between the source and drain of the N-type high-concentration diffusion layer 9, and at that time, the first gate sidewall 5 made of polysilicon as the high-dielectric material is formed. , N-type low-concentration diffusion layer 8 is covered with N
Since it overlaps with the high-concentration diffusion layer 9, the horizontal electric field in the vicinity of the drain is relaxed and hot electron deterioration is suppressed. If no voltage is applied to the gate electrode 3, no current flows between the source and drain of the N-type high-concentration diffusion layer 9 to operate as a switch.

According to this embodiment, the contact between the source / drain of the N-type high-concentration diffusion layer 9 and the wiring 10 is photomasked by the second gate sidewall oxide film 7 (for example, HTO film) as shown in FIG. It is possible to achieve good self-alignment without steps.

Further, it is possible to reduce the inter-wiring parasitic capacitance between the wiring 10 running on the gate electrode 3 and the gate electrode 3 as compared with the conventional example.

The reduction of parasitic capacitance will be briefly described using a parallel plate capacitance model as shown in FIGS. 12 (a) and 12 (b). Capacitance C per unit area is represented by C = ε'ε ₀ / Tox, where permittivity ε _{0 in} vacuum, film thickness Tox, and relative permittivity ε '. As a conventional example, in FIG. 12A, it is assumed that the passivation film 31 (SiO ₂ ) is 0.3 μm and the sidewall film 32 (Ta ₂ O ₅ ) is 0.3 μm. The capacitance C11 per unit area of the passivation film 31 is C11 = 3.9ε ₀ /
0.3 = 13ε ₀ , and the capacitance C 1 per unit area of the side wall film 32.
2 becomes C12 = 30ε ₀ /0.3=100ε ₀ . The capacitance C10 per unit area of the parasitic between the wirings 10 of the gate electrode 3 is C11 and C12.
C10 = C11xC12 / because it is the capacity of the series capacitor
(C11 + C12) = 11.5ε ₀ .

Next, in FIG. 12B of the present invention example,
The passivation film 31 (SiO 2 ₂) Is 0.3 μm
The first side wall film 33 (Ta₂O_Five) Is 0.15 μm,
Second sidewall film 34 (SiO₂) Is 0.15 μm,
If manufactured according to the same rule, the passivation film 3
The capacitance per unit area C21 is C21 = 13ε₀Same as
Therefore, the capacitance C22 per unit area of the first sidewall film 33 is C
22 = 30ε₀/0.15=200ε₀And the unit of the second sidewall film 34
The capacitance C23 per area is C23 = 3.9ε₀/0.15=26ε₀And
Therefore, the capacitance per unit area of the parasitic between the wirings 10 of the gate electrode 3
The quantity C20 is the capacity of the series capacitor of C21, C22 and C23.
Therefore, C20 = 8.3ε₀Is required. 8.3 / 1
This is 1.5 = 72%, which is an improvement in this embodiment compared to the conventional example.

Further, unlike the conventional example, the thin oxide film 4 is used.
Since the gate oxide film 2 and the gate oxide film 2 are formed in different steps, the respective film thicknesses can be set separately, and optimization can be performed in consideration of hot electron deterioration of the gate-drain breakdown voltage and the gate-drain parasitic capacitance.

Next, the first gate side wall will be described.
The first gate sidewall 5 does not need to be on the N-type high concentration diffusion layer 9. The reason is that since the N-type high-concentration diffusion layer 9 has a high concentration, it is not affected by the gate electrode 3 and is not depleted.
It is not necessary to cover the first gate sidewall 5 on the N-type high concentration diffusion layer 9. On the contrary, if the first gate side wall 5 covers the N-type high-concentration diffusion layer 9, the parasitic capacitance of the fringe increases, which is not preferable.

On the other hand, the first gate side wall 5 needs to be on the N-type low concentration diffusion layer 8. The reason will be described with reference to FIG. In FIG. 13, an N-type low-concentration diffusion layer 8 and an N-type high-concentration diffusion layer 9 are formed on a P-type silicon substrate, and the change of the surface horizontal electric field Ex of the silicon substrate depending on the length of the sidewall formed on the side wall of the gate electrode. Is shown. FIG. 3A shows a structure in which a side wall of an oxide film extends to the N-type high concentration diffusion layer on the side surface of the gate electrode. (b) is Ta2O as the first gate sidewall on the side surface of the gate electrode.
A structure is shown in which five films are covered up to the middle of the N-type low concentration diffusion layer. (c) is Ta2O as the first gate sidewall on the side surface of the gate electrode.
5 shows a structure in which the N type low concentration diffusion layer and the N type high concentration diffusion layer are partially covered. The difference between (a) and (c) is that the sidewall is an oxide film (SiO2) or high dielectric (Ta).
2O5). As shown in (d) of the same figure, it can be seen that a high electric field is generated at the gate electrode end of (a).
In (b) and (c), Ta, which is a high dielectric material, is used for the sidewall.
Since the 2O5 film is used, the horizontal electric field at the edge of the gate electrode is considerably relaxed compared to (a). in this way,
When the horizontal electric field is relaxed by the high-dielectric side wall (Ta2O5), electrons running in the channel direction gain energy by the horizontal electric field. Therefore, generally, hot electron generation is smaller as the horizontal electric field is weaker, and therefore hot electron deterioration is also caused. It will be alleviated.

In (b), a higher electric field is generated at the edge of the Ta2O5 film side wall than in (c), and it is desirable that the side wall has a structure as shown in (c). That is, as shown in FIG. 13C or FIG. 1, the side wall of the first gate, which is a high dielectric material, has a structure covering the low concentration N diffusion layer.

Such a structure can be realized by controlling the position of the N-type high concentration diffusion layer by the thickness of the second gate side wall. This will be described with reference to FIG. Second gate sidewall 7
If the thickness is increased, the end of the N-type high-concentration diffusion layer 9 comes under the second gate side wall 7 as shown in FIG. In this structure, the first gate side wall 5 is not covered with the N-type low-concentration diffusion layer 8, and the horizontal electric field strength at the end of the first gate side wall 5 becomes large. On the other hand, as shown in FIG. 3B, if the second gate side wall 7 is thinned to some extent, the end of the N-type high-concentration diffusion layer 9 can be diffused below the first gate side wall 5. .

(Embodiment 2) FIGS. 3 to 10 show a second embodiment of the present invention.
6A to 6C are cross-sectional views of manufacturing steps of a semiconductor device in the example of FIG. The manufacturing process of the semiconductor device of this embodiment will be described below with reference to FIG.

Process In FIG. 3, Si is formed on the P-type semiconductor substrate 1.
An O ₂ gate oxide film 2 is formed, and a gate electrode layer (for example, polysilicon 300 nm) is formed on the gate oxide film 2.
And a gate electrode 3 is formed by selective etching using a mask.

In the process diagram 4, an ion implantation method (for example, P ⁺
Ion 40 KeV 2x10 ¹³ CM ^- by ^2), to form an N-type low concentration diffusion layer 8 on the P-type semiconductor substrate 1 upper part not covered with the gate electrode 3.

In process step 5, a first thin oxide film 4 (for example, a 20 nm HTO film) is deposited on the gate electrode 3 and the N-type low concentration diffusion layer 8, and a first thin oxide film 4 is deposited on the first thin oxide film 4. One gate sidewall layer 5 (eg, polysilicon 150 nm)
Deposit.

In FIG. 6, the first gate sidewall layer 5 remains lower than the height of the gate electrode 3 in a self-aligned manner on the side portion of the gate electrode 3 by overetching of an etching method having a strong anisotropy in the vertical direction. To do. At this time, the first thin oxide film 4 has a lower etching rate than that of the first gate sidewall 5 and is not so etched.

Process In FIG. 7, a second gate sidewall oxide film 7 is deposited on the first gate sidewall material 5 and the first thin oxide film 4.

In FIG. 8, the second gate side wall oxide film 7 (for example, HTO film 150 nm) is covered on the side surface of the gate electrode 3 and the first gate side wall 5 by an etching method having a strong anisotropy in the vertical direction. So that it remains.

In FIG. 9, the N-type high concentration diffusion layer 9 is formed in the upper layer portion of the P-type semiconductor substrate 1 which is not covered with the gate electrode 3 and the second gate sidewall oxide film 7 by the ion implantation method.

In the process drawing 10, after the process drawing 9, the Al film is removed.
After depositing 500 nm, a contact with the N-type high-concentration diffusion layer 9 is made in a self-aligned manner, and the Al film on the gate electrode is removed by etching by a normal photo process. The feature here is that the N-type high-concentration diffusion layer 9 and the wiring 10 are connected in a self-aligned manner.

As described above, according to this embodiment, the semiconductor device can be easily realized by the current LSI technology, and the semiconductor device can be realized with good self-alignment and without requiring many steps.

(Embodiment 3) FIGS. 11A to 11C are sectional views showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention. The manufacturing process of the semiconductor device of this embodiment will be described below with reference to FIG.

This embodiment is the same as the steps of Embodiment 2 shown in FIGS. In the step (a), after the step of FIG. 6 of the second embodiment, an N-type high concentration diffusion is performed on the upper layer portion of the P-type semiconductor substrate 1 not covered with the gate electrode 3 and the first gate sidewall 5 by the ion implantation method. At the same time as forming the layer 9, the high-concentration N-type first gate sidewall 11 is formed.

In step (b), a second gate sidewall oxide film 7 (eg, HTO film 150 nm) is deposited on the high-concentration N-type first gate sidewall 11 and the first thin oxide film 4.

In step (c), the second gate sidewall oxide film 7 is covered on the side surface of the gate electrode 3 and the high-concentration N-type first gate sidewall 11 by an etching method having a strong vertical anisotropy. To remain.

As described above, according to this embodiment, the semiconductor device can be easily realized by the current LSI technology, and the semiconductor device can be realized with good self-alignment without requiring many steps.

Although polysilicon is used as the first gate sidewall 5 in the first, second and third embodiments, a high dielectric material such as deposited Si ₃ N ₄ or Ta ₂ O ₅ may be used. It goes without saying that it is good.

In the first, second, and third embodiments, instead of the gate oxide film 2, a nitrided oxide insulating film, SiO ₂ / SiN is used.
A MIS transistor using a film or a SiO ₂ / SiN / SiO ₂ film may be used. In the embodiment, the N-channel device has been described, but it goes without saying that the P-channel device has the same effect.

Further, in the process diagram 3 of the second embodiment, after the gate electrode 3 (for example, polysilicon 250 nm) is deposited, a third insulating film (for example, HTO film 150 nm) is deposited, and selective etching with a mask is performed. Therefore, a gate wiring made of the third insulating film 6 may be formed on the gate electrode 3 on the lower portion.

In the process diagram 5 of the second embodiment,
Although the first thin oxide film 4 is deposited on the N-type low-concentration diffusion layer 8, it goes without saying that the first thin oxide film 4 may be formed by an oxidation process.

[0042]

As described above, according to the present invention,
The high electric field near the drain is relaxed by the first gate sidewall layer with a high dielectric constant, and it is resistant to hot electron deterioration, and the second gate sidewall layer made of an insulating film separates the gate electrode and the high-concentration diffusion layer for self-alignment. The process of making contact with the gate electrode can be made possible, and the parasitic capacitance of the wiring running on the gate and the gate electrode can be reduced, which has a great practical effect.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a MIS type transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional structure diagram of a conventional MIS transistor.

FIG. 3 is a sectional view of a first manufacturing process showing a second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 4 is a sectional view of a second manufacturing process showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 5 is a sectional view of a third manufacturing process showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 6 is a sectional view of a fourth manufacturing step showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 7 is a sectional view of a fifth manufacturing step showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 8 is a sectional view of a sixth manufacturing step showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 9 is a sectional view of a seventh manufacturing step showing the second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 10 is an eighth manufacturing step sectional view showing a second embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 11 is a manufacturing process chart showing the third embodiment of the method of manufacturing the MIS transistor semiconductor device of the present invention.

FIG. 12 is a schematic diagram of a conventional example of the capacitance between gate wirings assuming a parallel plate and the present invention.

FIG. 13 is a structural cross-sectional view of a conventional example and the MIS transistor of the present invention, and a Si electric interface horizontal electric field diagram of a channel portion

FIG. 14 is a structural cross-sectional view of a MIS transistor for explaining the difference in the position of the high-concentration diffusion layer due to the difference in the thickness of the second gate sidewall.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Gate oxide film 3 Polysilicon gate electrode 4 Thin oxide film 5 First gate sidewall 6 insulating film 7 Second gate sidewall oxide film 8 N type low concentration diffusion layer 9 N type high concentration diffusion layer 10 wiring 11 High Concentration N-type First Gate Side Wall 31 passivation film 32 sidewall film 33 First sidewall film 34 Second sidewall film

Claims (4)

[Claims] 1. A gate insulating film and a gate electrode selectively formed on a first conductivity type semiconductor substrate, an insulating film provided on the side portion of the gate electrode and on the semiconductor substrate, and an upper portion of the insulating film and A first gate sidewall layer having a higher dielectric constant than the insulating film provided on the side portion and lower than the gate electrode height; and a second gate sidewall layer formed of an insulating film covering the first gate sidewall. MIS type transistor having. 2. The MIS according to claim 1, wherein an end portion of the gate electrode reaches a low concentration second conductivity type source / drain diffusion layer formed on the semiconductor substrate via a gate insulating film. Type transistor. 3. The first gate side wall layer according to claim 1 is in contact with a high-concentration second conductivity type source / drain diffusion layer formed on the semiconductor substrate through the insulating film. MIS type transistor. 4. A step of forming a gate insulating film on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a first step on the gate electrode and the semiconductor substrate. Of the first insulating film, a step of depositing a first gate sidewall layer having a dielectric constant higher than that of the first insulating film, and an etching method having a strong vertical anisotropic property. Selectively etching the gate sidewall layer of to leave the first gate sidewall layer below the gate electrode height in a self-aligned manner on the side portion of the gate electrode; MIS transistor manufacturing method comprising depositing an insulating film, and leaving the second insulating film so as to cover the first gate sidewall by an etching method having a strong vertical anisotropy .