JPH05336513A - Video signal encoding device - Google Patents

Abstract

PURPOSE:To hold an encoding quantity constant by predicting the volume of generated data from a difference absolute sum in a block of an input image signal a dynamic range, etc. CONSTITUTION:This video signal encoding device is equipped with an encoding quantity control circuit 4 which predicts the volume of information for example, in field units while delaying the image data block outputted from a switch circuit 3 until the prediction of the volume of information ends and then outputting the block, and determines a quantization parameter according to the prediction result so that the actual volume of information is less than a desired value. Namely, the video signal which is inputted is divided into blocks, the volume of generated data is predicted for the data into the blocks from the absolute value sum of differences between adjacent pixels in the respective blocks or dynamic ranges in the blocks, and quantization step width is so controlled that the volume of generated data is less than the previously set desired value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal encoding apparatus suitable for compressing information of a moving image signal and recording it on a predetermined recording medium with a constant code amount.

[0002]

2. Description of the Related Art FIG. 21 shows a block diagram of a conventional video signal coding apparatus for controlling the code amount. Reference numeral 1 is a digital video input terminal, 2 is a blocking circuit for blocking the digital video input signal, 8 is a reference field and motion compensation prediction for the video signal block output from the blocking circuit 2, and the input block is referred to A motion compensation circuit that outputs a prediction error from a block in block units, 3 selects the output of the blocking circuit 2 in the case of an intrafield that does not perform motion compensation, and a motion compensation circuit in the case of a prediction field that performs a motion compensation prediction 8 is a switch circuit for selecting 8 outputs. Reference numeral 5 is an orthogonal transformation circuit that performs orthogonal transformation on the image data block output from the switch circuit 3, 10 is a quantization circuit that quantizes the image data output from the orthogonal transformation circuit 5, and 7 is a quantization circuit 10. An encoding circuit for variable-length encoding the output, a buffer memory 11 for storing the output of the encoding circuit in a fixed capacity and outputting the output, and an output terminal 9.

Next, the operation will be described. As the input digital video input signal, for example, a 4: 2: 2 component digital signal is input, and 8 [pixels are output by the blocking circuit 2 regardless of an intra field in which motion compensation prediction is not performed and a prediction field in which motion compensation prediction is performed. ]
It is divided into input blocks in which x8 [line] is one unit. The output of the blocking circuit 2 is input to the motion compensation circuit 8, reconstructed from the past output block, image data of the reference field stored in the motion compensation circuit 8 and motion compensation prediction are performed, and the input block and reference are performed. The prediction error in pixel units with respect to the block is output to the switch circuit 3.
On the other hand, the output of the blocking circuit 2 is also input to the switch circuit 3. The switch circuit 3 selects the output of the blocking circuit 2 in the case of the intra field, and selects the output of the motion compensation circuit 8 in the case of the predictive field. The orthogonal transform circuit 5 performs, for example, discrete cosine transform (hereinafter abbreviated as DCT) on the image data output from the switch circuit 3,
Output to the quantization circuit 10.

The output of the quantization circuit 10 is also input to the motion compensation circuit 8. In the motion compensation circuit 8, after decoding the image data output from the quantization circuit 10 by inverse quantization and inverse orthogonal transform processing, in the case of a predictive field, the reference field used when obtaining the predictive error at the time of encoding is decoded. The reproduced image is restored by adding the data, and this is saved as reference data. In the case of the intra field, the data decoded by the inverse quantization and inverse orthogonal transform processing is stored as it is as the reference data.

On the other hand, in the quantization circuit 10, the buffer memory 11
The image data is quantized by determining the quantization step according to the amount of residual data stored in the memory. That is, when the residual data in the buffer memory 11 has a margin, a small quantization step size is selected so as to increase the amount of generated data. On the other hand, when the buffer memory 11 is likely to exceed the allowable amount, a large quantization step size is controlled so that the data generation amount is reduced.

The image data output from the quantization circuit 10 is variable-length coded in the coding circuit 7, and the coded data is output to the buffer memory 11. The buffer memory 11 stores the encoded image data, reads it out at a predetermined fixed rate, and performs transmission or magnetic recording. At the same time, the buffer memory 11 detects the amount of remaining data and outputs a control signal corresponding to the amount of remaining data to the quantization circuit 10 to control the quantization step of the quantization circuit 10 to generate the data amount. Can be kept constant.

[0007]

Although the conventional video signal coding apparatus is configured as described above, the moving picture to be coded may have an image with a lot of motion or a scene change or the like may cause an image change. In the case where the contents of (1) change significantly, there is a problem that the buffer memory overflows because the generation amount of encoded data changes rapidly.

The present invention has been made in view of the above circumstances. The information amount of image data is trial calculated with simple hardware, and the actual quantization parameter is controlled according to the trial calculation result to make the information amount constant. It is characterized by

[0009]

A video signal encoding apparatus according to the present invention divides an input video signal into blocks, and with respect to the blocked data, the sum of absolute values of differences between adjacent pixels in each block or , A means for predicting the amount of data generated by the dynamic range in each block, and controlling the quantization step width so that the amount of generated data falls within a preset target value.

[0010]

The video signal coding apparatus according to the present invention predicts the amount of data by the sum of absolute differences or the dynamic range in the block of the input image, and keeps the amount of data to be encoded constant. The code amount can be kept constant.

[0011]

EXAMPLES Example 1. 1 is a block diagram showing a video signal encoding apparatus according to a first embodiment of the present invention. In the figure,
Reference numeral 1 is a digital video input terminal, 2 is a blocking circuit for blocking the input digital video signal, and 8 is motion compensation prediction with a reference field for the video signal block output from the blocking circuit 2 and the input A motion compensation circuit 3 that outputs a prediction error between a block and a reference block on a block-by-block basis selects the output of the blocking circuit 2 in the case of an intrafield that does not perform motion compensation, This is a switch circuit that selects the output of the motion compensation circuit 8. Reference numeral 4 delays and outputs the image data block output from the switch circuit 3 until the information amount prediction ends, and at the same time, for example, the information amount prediction is performed on a field-by-field basis, and the actual information amount falls within the target value according to the prediction result. It is a code amount control circuit that determines a quantization parameter that can be accommodated. Reference numeral 5 is an orthogonal transformation circuit that performs orthogonal transformation on the image data delayed by the code amount control circuit 4. 6 is a quantization circuit for quantizing the output of the orthogonal transformation circuit 5 by the quantization parameter obtained by the code amount control circuit 4, 7 is an encoding circuit for encoding the output of the quantization circuit 6 by variable length coding, Reference numeral 12 is a buffer memory, and 9 is an output terminal for outputting encoded image data.

Next, the operation will be described. The input digital video signal is, for example, a component digital signal of 4: 2: 2 and is input by the blocking circuit 2 to, for example, 8 [pixels irrespective of an intra field in which motion compensation prediction is not performed and a prediction field in which motion compensation prediction is performed. ] × 8 [line] is divided into input blocks each having one unit and output. The output of the blocking circuit 2 is input to the motion compensation circuit 8, reconstructed from the past output block, image data of the reference field stored in the motion compensation circuit 8 and motion compensation prediction are performed, and the input block and reference are performed. The prediction error in pixel units with respect to the block is output to the switch circuit 3. On the other hand, the output of the blocking circuit 2 is also input to the switch circuit 3. The switch circuit 3 selects the output of the blocking circuit 2 in the case of the intra field, and selects the output of the motion compensation circuit 8 in the case of the predictive field.

The image data output from the switch circuit 3 is input to the code amount control circuit 4 and trial calculation of the information amount is performed in image block units. Here, the code amount control circuit 4 is configured as shown in FIG. 2, for example. In FIG. 2, 20 is a field memory, 21 is a Y signal difference absolute value sum calculation circuit, 22
Is a BY signal absolute difference value sum calculation circuit, 23 is an RY signal difference absolute value sum calculation circuit, 24 is a Y signal code amount prediction circuit, 25 is a BY signal code amount prediction circuit, and 26 is RY Signal code amount prediction circuit, 27 Y signal addition circuit, 28 BY signal addition circuit,
29 is an RY signal addition circuit, 30 is a quantization level determination circuit,
Reference numeral 31 is a control reference value table.

Next, the operation of the code amount control circuit 4 will be described. The Y signal of the input image data is input to the Y signal difference absolute value sum calculation circuit 21, and the BY and RY signals are respectively the BY signal difference absolute value sum calculation circuit 22 and the RY signal difference absolute calculation circuit 21. It is input to the value sum calculation circuit 23. The Y signal difference absolute value sum calculation circuit 21 calculates the difference between the horizontal direction and the vertical direction in the block with respect to the input block Di (i, j) of 8 pixels × 8 lines (i, j = 1 to 8). Sum of absolute values

[0015]

[Equation 1]

Is output.

Output SY of Y signal difference absolute value sum calculation circuit 21
Is input to the Y signal code amount prediction circuit 24 and the data amount generated in block units is predicted. FIG. 3 shows the relationship between the sum of absolute differences SY within a block and the amount of data generated when each block is orthogonally transformed, standard-quantized, and coded with respect to the Y signal. Here, FIG. 3 shows the amount of data generated in each block unit for the sample image and S in that case.
This is a graph in which the standard deviation and the average value of the Y values are obtained. From this, the data generation amount of the image data when the predetermined sum of absolute differences is given is σ1 and σ in FIG.
It can be considered to be within the range surrounded by 2. Here, the Y signal code amount predicting circuit 24 is constituted by, for example, a ROM, and occurs when the sum of absolute differences between blocks of the Y signal as shown by the solid line in FIG. 3 is quantized by standard quantization. The average amount of data is recorded. That is, Y
The signal code amount prediction circuit 24 outputs the predicted data amount when standard quantization is performed on the output of the Y signal difference absolute value sum calculation circuit 21. The output of the Y signal code amount prediction circuit 24 is
The Y signal adding circuit 27 adds up for one field to obtain a predicted data amount for one field.

Since the data amount predicting means for the BY signal and the RY signal is the same as that for the Y signal, description thereof will be omitted. However, in the case of a 4: 2: 2 component digital signal, the sampling frequency of the color difference signal is half that of the Y signal. For this reason, as shown in FIG. 4, in the case of BY and RY signals, the relationship between the sum of the absolute difference values per block and the amount of generated data is different from that in the case of the Y signal shown in FIG. Therefore, in the BY signal code amount predicting circuit 25 and the RY signal code amount predicting circuit 26, when the quantization is performed by the standard quantization with respect to the sum of absolute differences of the color difference signals per block as shown in FIG. The average amount of data generated in
The predicted data amount for the sum of absolute differences of the respective blocks output by the -Y signal difference absolute value arithmetic circuit 22 and the RY signal difference absolute value sum arithmetic circuit 23 is output.

Y signal addition circuit 27, BY signal addition circuit 28
The predicted data amount per field output by the RY signal adding circuit 29 and the RY signal adding circuit 29 is input to the quantization level determination circuit 30. The quantization level determination circuit 30 adds the predicted data amount per field for the Y, BY and RY signals and calculates the predicted data amount for one field as a whole. Further, the predicted data amount of the entire one field and the target data amount per one field output from the control reference value table 31 are compared to determine and output the quantization step width corresponding to the error. That is, when the predicted data amount is smaller than the target data amount, the quantization step size is reduced to increase the generated data amount. On the contrary, when the predicted data amount is larger than the target data amount, the quantization step width is increased to reduce the generated data amount.

Here, assuming that the predicted data amount is Ap and the target data amount is Ar, the quantization level determination circuit 30 obtains E = Ap / Ar and, for example, in the five steps of quantization steps shown in Table 1. An appropriate quantization level L is selected and output.

[0021]

[Table 1]

On the other hand, the input data is also input to the field memory 20, and after delaying the data until the determination result is output from the quantization level determination circuit 30, the image data is output to the orthogonal transformation circuit 5. .. The orthogonal transform circuit 5 performs, for example, DCT on the input data block. The output of the orthogonal transformation circuit 5 is input to the quantization circuit 6 and is quantized according to the quantization level output from the code amount control circuit 4. That is, in the quantization circuit 6, the code amount control circuit 4
The amount of generated data is controlled to be equal to or less than a predetermined amount of information by quantizing the entire field in the quantization steps corresponding to the five quantization levels output from. However, the quantization levels in Table 1 are set such that the standard quantization level used in the case of code amount prediction is the quantization level 2, and the smaller the quantization level, the smaller the quantization step width.

The output of the quantization circuit 6 is also input to the motion compensation circuit 8. In the motion compensation circuit 8, the quantization circuit 6
After decoding the image data output from the device by inverse quantization and inverse orthogonal transform processing, in the case of a predictive field, reconstruct the reproduced image by adding the data of the reference field used when calculating the predictive error during encoding. Then, this is saved as reference data. In the case of the intra field, the data decoded by the inverse quantization and inverse orthogonal transform processing is stored as it is as the reference data.

On the other hand, the image data output from the quantization circuit 6 is variable-length coded in the coding circuit 7, and the coded data is output to the buffer memory 12. The buffer memory 12 stores encoded image data,
The data is output from the output terminal 9 at a predetermined fixed rate for transmission or magnetic recording.

In the above embodiment, the information amount of image data is controlled in field units when predicting the amount of data, but it is not necessarily in field units, and information amount control is performed in frame units or segment units smaller than fields. You may go. Further, the quantization level is performed in 5 steps, but it is not necessarily required to be 5 steps, and n steps (n ≧
You can do it in 2). Further, although the input data is divided into 8 pixels × 8 lines, it is not always necessary to divide the input data into 8 pixels × 8 lines, and it may be performed with n pixels × m lines (n ≧ 2, m ≧ 2).

Example 2. In the first embodiment, the prediction of the code amount is determined by using the sum of absolute differences in each block, but the code amount may be predicted by using the dynamic range in each block. An example configured in this way is the second embodiment of the present invention.

FIG. 5 shows a block diagram of the information amount prediction circuit 4 in the second embodiment of the present invention. In FIG. 5, 40 is a field memory, 41 is a Y signal dynamic range calculation circuit, 42 is a BY signal dynamic range calculation circuit, 43 is an RY signal dynamic range calculation circuit, 44 is a Y signal code amount prediction circuit, and 45 is BY signal code amount predicting circuit, 46 is R
-Y signal code amount prediction circuit, 47 Y signal addition circuit, 48 B
-Y signal addition circuit, 49 is an RY signal addition circuit, 50 is a quantization level determination circuit, and 51 is a control reference value table.

Next, the operation of the code amount control circuit 4 in the second embodiment of the present invention will be described. The Y signal of the input image data is input to the Y signal dynamic range calculation circuit 41, and the BY and RY signals are input to the BY signal dynamic range calculation circuit 42 and the RY signal dynamic range calculation circuit 43, respectively. Is entered. The Y signal dynamic range calculation circuit 41 calculates the maximum value SYmax and the minimum value SYmin within the block for the input block Di (i, j) of 8 pixels × 8 lines (i, j = 1 to 8). , The dynamic range SYd is calculated and output by the following equation. SYd = SYmax-SYmin

The output SYd of the Y signal dynamic range calculation circuit 41 is input to the Y signal code amount prediction circuit 44 and the data amount generated in block units is predicted. FIG. 6 shows the dynamic range SYd in the block for the Y signal.
And the amount of data generated when each block is orthogonally transformed, standard-quantized, and coded. Here, FIG. 6 is a graph in which the average value of the data amount generated in each block unit and the value of SYd in that case is obtained for the sample image. That is, when the dynamic range for each block is given, the amount of information generated for each block can be almost predicted from FIG. Here, the Y signal code amount prediction circuit 44 is composed of, for example, a ROM, and data generated when the dynamic range per block of the Y signal as shown by the solid line in FIG. 6 is quantized by standard quantization. The average amount is recorded. That is, the Y signal code amount prediction circuit 44 outputs the predicted data amount when standard quantization is performed on the output of the Y signal dynamic range calculation circuit 41. The output of the Y signal code amount prediction circuit 44 is added for one field in the Y signal addition circuit 47 to obtain the predicted data amount of the Y signal for one field.

Since the data amount predicting means for the BY signal and the RY signal is the same as that for the Y signal, description thereof will be omitted. However, in the case of a 4: 2: 2 component digital signal, the sampling frequency of the color difference signal is half that of the Y signal. Therefore, as shown in FIG. 7, in the case of BY and RY signals, the relationship between the dynamic range per block and the amount of generated data is different from that in the case of Y signal shown in FIG. Therefore, the BY signal code amount predicting circuit 45 and the RY signal code amount predicting circuit 46 are generated when the dynamic range per block of the color difference signals as shown in FIG. 7 is quantized by standard quantization. The average of the amount of data to be recorded is recorded, and the BY signal dynamic range calculation circuit 42 and R-
The predicted data amount per block for each addition result output by the Y signal dynamic range calculation circuit 43 is output.

Y signal adder circuit 47, BY signal adder circuit 48
The predicted data amount per field output by the RY signal adding circuit 49 and the RY signal adding circuit 49 is input to the quantization level determining circuit 50. In the quantization level determination circuit 50, the predicted data amount of one field of Y, BY and RY signals is added to obtain the predicted data amount of one field. Further, the predicted data amount per field and the target data amount per field output from the control reference value table 51 are compared to determine and output the quantization step width corresponding to the error. That is, when the predicted data amount is smaller than the target data amount, the quantization step size is reduced to increase the data amount. On the contrary, when the predicted data amount is larger than the target data amount, the quantization step size is increased to reduce the data amount. Further, the operation of the field memory 20 is the same as that of the first embodiment of the present invention, and therefore its explanation is omitted.

Example 3. In the above-mentioned Examples 1 and 2,
Although adaptive quantization was not performed for each block, it is determined whether the image quality deterioration is conspicuous for each block and n
The code amount control may be performed by performing adaptive quantization determination in stages (n ≧ 2) and predicting the amount of generated data in the case of encoding at each adaptive quantization level. In this way, by predicting the amount of generated data in the case of performing adaptive quantization of n stages at each adaptive quantization level, the predicted code amount of the entire field is obtained, and the code amount is controlled. An example is the third embodiment of the present invention.

FIG. 8 is a block diagram showing a video signal encoding apparatus according to the third embodiment of the present invention. In the figure, 1 is a digital video input terminal, 2 is a blocking circuit for blocking an input digital video signal, and 8 is motion compensation prediction with a reference field for a video signal block output from the blocking circuit 2. A motion compensation circuit that outputs a prediction error between an input block and a reference block in block units, and 3 selects an output of the blocking circuit 2 in the case of an intra field that does not perform motion compensation, and a prediction field that performs motion compensation prediction. In the case of, the switch circuit selects the output of the motion compensation circuit 8. Reference numeral 15 is an adaptive quantization determination circuit that determines, for example, three kinds of quantization steps according to the property of the image block output from the block formation circuit 2, and 14 is an information amount prediction of the image data block output from the switch circuit 3. At the same time as delaying and outputting until the end, the amount of data generated when each block is adaptively quantized according to the determination result of the adaptive quantization determination circuit 15 is predicted, for example, in field units, and the actual information amount is calculated according to the prediction result. Is a code amount control circuit that determines a quantization parameter for each field so that is within a target value. Reference numeral 5 is an orthogonal transformation circuit that performs orthogonal transformation on the image data delayed by the code amount control circuit 4. 16 is a code amount control circuit
An adaptive quantization circuit for quantizing the output of the orthogonal transform circuit 5 by the block-by-block quantization parameter obtained by 14 and the block-by-block quantization parameter obtained by the adaptive decision circuit 15, and 7 is an adaptive quantization circuit. An encoding circuit for encoding the output of the encoding circuit 6 by variable-length encoding, 12 is a buffer memory, and 9 is an output terminal for outputting encoded image data.

Next, the operation will be described. The operations of the blocking circuit 2, the switch circuit 3, and the motion compensation circuit 8 are the same as in the case of the first embodiment described above, and will be omitted. The adaptive quantization determination circuit 15 determines whether the input image block is a block in which the image quality deterioration is easily noticed or is a block in which the image quality deterioration is not noticeable, and, for example, a three-step quantization is performed according to the property of the image block. Select the activation level. Here, the image block where image quality degradation is most obvious is a block with fine lines with high contrast on a flat background, and if such a block is roughly quantized, the inverse orthogonal transform is performed on the decoder side. In addition, the quantization error spreads over the entire block, and noise is superimposed on the flat portion where the deterioration of the image quality is easy to see, so the noise in the flat portion becomes visually noticeable. On the other hand, a block in which the deterioration of image quality is not noticeable has no flat portion, and the movement in the block is generally large. Therefore, the adaptive quantization determination circuit 15 performs the adaptive quantization determination by detecting whether or not there is a flat portion and an edge portion in which the image quality deterioration is noticeable in the block to be encoded.

Next, the operation of the adaptive quantization determination circuit 15 will be described. In the adaptive quantization determination circuit 15, the blocking circuit 2
The image block output from is first divided into four sub-blocks. For example, when the input block outputs a block of 8 pixels × 8 lines, as shown in FIG. 9, 4 pixels × 4
Divide the line into four sub-blocks. Here, the four sub-blocks are designated as D1, D2, D3, and D4, and the pixel values of each sub-block are designated as D1 (i, j) and D2, respectively.
(I, j), D3 (i, j), D4 (i, j) (i, j
= 1-4). Next, for the input sub-blocks D1, D2, D3, D4, the sum of absolute differences between the horizontal and vertical directions in the sub-blocks

[0036]

[Equation 2]

Is calculated to obtain the minimum and maximum values of V1, V2, V3 and V4 A = MIN (V1, V2, V3, V4) and C = B-A.

Here, the calculated value A can be regarded as a parameter representing a flat portion in which the image quality deterioration of the image block is easy to understand, and the calculated value C can be regarded as a parameter representing an edge portion of the image block. From this, the adaptive quantization determination circuit 15 uses the calculated values A and C to perform three-step adaptive quantization determination for each block according to the determination diagram as shown in FIG. 10, and obtains the determination result in block units. Output.
That is, in the adaptive quantization determination circuit 15, a fine quantization step is selected for a block in which image quality deterioration is easily noticeable,
A coarse quantization step is selected for a block in which image quality deterioration is not noticeable. However, in FIG. 10, the quantization levels are coarser in the order of the quantization levels 1, 2, and 3.

On the other hand, the image data output from the switch circuit 3 is input to the code amount control circuit 14 and trial calculation of the information amount generated in image block units is performed according to the determination result of the adaptive quantization determination circuit 15. Here, the code amount control circuit 14
Has a configuration as shown in FIG. 11, for example. In FIG. 11, 20 is a field memory, 21 is a Y signal difference absolute value sum calculation circuit, 22 is a BY signal difference absolute value sum calculation circuit, and 23 is R.
-Y signal difference absolute value sum calculation circuit, 64 Y signal code amount prediction circuit, 65 BY signal code amount prediction circuit, 66 RY signal code amount prediction circuit, 27 Y signal addition circuit, 28 A BY signal addition circuit, 29 is an RY signal addition circuit, 30 is a quantization level determination circuit, and 31 is a control reference value table.

Next, the operation of the code amount control circuit 14 will be described. In FIG. 11, a Y signal difference absolute value sum calculation circuit 21,
The operations of the BY signal absolute difference sum calculation circuit 22 and the RY signal difference absolute value sum calculation circuit 23 are the same as those in the first embodiment of the present invention, and will be omitted. The Y signal code amount prediction circuit 64 predicts the code amount per block according to the output of the Y signal difference absolute value sum calculation circuit 21 for each block and the three-step adaptive quantization determination output from the adaptive quantization determination circuit 15.
Here, the Y signal code amount prediction circuit 64 uses, for example, three types of R
The amount of data generated when each ROM is quantized by standard quantization at each adaptive quantization level with respect to the sum of absolute differences of Y signals per block as shown in FIG. 12 in each ROM. The average of is recorded. That is, in the signal code amount prediction circuit 64, the three types of R
A ROM corresponding to the adaptive quantization determination result is selected from the OM, the sum of absolute differences between the blocks is input to the selected ROM, and the predicted data amount per block in that case is output. However, in FIG. 12, (a) corresponds to the quantization level 1 of FIG. 10, and (b) and (c) correspond to the quantization levels 2 and 3 of FIG. 10, respectively. That is, when the quantization level 1 is selected by the adaptive quantization determination in the Y signal code amount prediction circuit 64, the code amount is predicted according to the determination shown in FIG. 12A, and the quantization levels 2 and 3 are similarly selected. In this case, the data generation amount for each block is predicted and output according to the determinations of FIGS. 12B and 12C, respectively.

Since the data amount predicting means for the BY signal and the RY signal is the same as that for the Y signal, the description thereof will be omitted. However, in the case of a 4: 2: 2 component digital signal, the sampling frequency of the color difference signal is half that of the Y signal. Therefore, as shown in FIG. 13, BY, R
In the case of the -Y signal, the relationship between the sum of absolute differences per block and the amount of generated data is different from that in the case of the Y signal.
Signal code amount prediction circuit 65 and RY signal code amount prediction circuit 66
For example, the amount of generated data is predicted based on the criterion shown in FIG. Next, the outputs of the Y signal code amount prediction circuit 64, the BY signal code amount prediction circuit 65, and the RY signal code amount prediction circuit 66 are the Y signal addition circuit 27, BY signal addition circuit 28, and R-, respectively.
The Y signal adding circuit 29 adds the respective signals to obtain the predicted data amount for one field.

Y signal addition circuit 27, BY signal addition circuit 28
The predicted data amount per field output by the RY signal adding circuit 29 and the RY signal adding circuit 29 is input to the quantization level determination circuit 30. The quantization level determination circuit 30 adds the predicted data amount per field for the Y, BY and RY signals and calculates the predicted data amount for one field as a whole. Further, the predicted data amount of the entire one field and the target data amount per one field output from the control reference value table 31 are compared to determine and output the quantization step width corresponding to the error. That is, when the predicted data amount is smaller than the target data amount, the quantization step size is reduced to increase the generated data amount. On the contrary, when the predicted data amount is larger than the target data amount, the quantization step width is increased to reduce the generated data amount.

Here, assuming that the predicted data amount is Ap and the target data amount is Ar, the quantization level determination circuit 30 obtains E = Ap / Ar, and, for example, in the five steps of quantization steps shown in Table 2. An appropriate quantization level L is selected and output.

[0044]

[Table 2]

On the other hand, the input data is also input to the field memory 20, and after delaying the data until the determination result is output from the quantization level determination circuit 30, the image data is output to the orthogonal transformation circuit 5. .. The orthogonal transform circuit 5 performs, for example, DCT on the input data block. The output of the orthogonal transformation circuit 5 is input to the adaptive quantization circuit 16 and is output according to the quantization level of each field output from the code amount control circuit 14 and the quantization level of each block output from the quantization determination circuit 15. Quantize. Here, the quantizing circuit 15 has, for example, seven kinds of quantizing step widths as shown in Table 3, and the quantizing level and the adaptive quantizing decision in the field unit of five stages output from the code amount controlling circuit 14 are performed. The amount of data generated is controlled to be equal to or less than a predetermined amount of information by determining the quantization step in each block by the three-step adaptive quantization determination output from the circuit 15 in block units and performing quantization. be able to. However, in the quantization levels in Table 3, the three standard quantization levels used in the code amount prediction are the quantization levels L in field units.
Is the same as the quantization level when is 2. Further, in Table 3, the smaller the quantization level, the smaller the quantization step width.

[0046]

[Table 3]

In the above embodiment, the information amount of image data is controlled in field units when predicting the amount of data, but it is not necessarily in field units and information amount control is performed in frame units or segment units smaller than fields. You may go. Although the code amount prediction is performed by the sum of absolute differences between adjacent pixels in each block, the generated data amount is predicted by using the dynamic range of each block as shown in the second embodiment of the present invention. Good. Although the quantization level in each field is set to 5 steps, it may be performed in n steps (n ≧ 2). Further, although the determination result of adaptive quantization is set to three stages, it may be performed in m stages (m ≧ 2). Similarly, the number of quantization steps of the adaptive quantization circuit 16 is seven, but may be one (1 ≧ 2). Further, the adaptive quantization determination is made by using the output of the blocking circuit 2, but it is not always necessary to make the determination from the original image data, and it may be made from the orthogonal transform coefficient. Further, although the input data is divided into 8 pixels × 8 lines, it is not always necessary to divide the input data into 8 pixels × 8 lines, and it may be performed with n pixels × m lines (n ≧ 2, m ≧ 2).

Example 4. Although the code amount prediction is not performed in units of a plurality of fields or frames in the first and second embodiments, the code amount prediction may be performed in a unit of a plurality of fields or frames to control the code amount. The fourth embodiment of the present invention is an example in which the code amount is predicted in units of a plurality of fields or frames to control the code amount.

FIG. 14 shows a block diagram of the code amount control circuit 4 in the fourth embodiment of the present invention. In FIG. 14, 32 is a field memory having a capacity of 4 fields, 21 is Y
Signal difference absolute value sum arithmetic circuit, 22 BY signal difference absolute value sum arithmetic circuit, 23 RY signal difference absolute value sum arithmetic circuit, 24
Is a Y signal code amount prediction circuit, 25 is a BY signal code amount prediction circuit, 26 is an RY signal code amount prediction circuit, 27 is a Y signal addition circuit, 28 is a BY signal addition circuit, and 29 is R-. Y signal adding circuit, 33 code amount ratio calculating circuit 34, control reference value generating circuit, 35
Is a quantization level determination circuit.

Next, the operation will be described. Here, 1 field of intra field and 3 field of predictive field (first, second, third inter field)
Consider a case where a video signal is encoded into a predetermined fixed amount of information in units of four fields consisting of. The input image data is in field units, and the Y signal is
It is input to the Y signal difference absolute value sum calculation circuit 21, and BY, R
The −Y signals are respectively the BY signal difference absolute value sum calculation circuit 22.
And the RY signal difference absolute value sum calculation circuit 23.
The prediction of the code amount in the field unit for the Y, BY, and RY signals is the same as that in the first embodiment, and therefore the description thereof is omitted. Next, Y and B-obtained in field units
The predictive coding amount for the Y and RY signals is input to the code amount ratio calculation circuit 33. In the code amount ratio calculation circuit 33, the total data amount of each field is calculated by summing the data amounts of Y, BY and RY for each field, and further, each field (intra field and first, second , Third interfield), and the target data amount for four fields output from the control reference value table 34 is distributed in correspondence with these ratios to determine the amount of information to be assigned to each field. decide.

For example, when the target data amount for 4 fields is 1 Mbits and the result of the code amount prediction performed in field units is 6: 2: 2.5: 1.5, 0.5 Mbits for the intra field, the first 0 in the interfield.
166Mbits, 2nd interfield 0.208Mbits, 3rd
A data amount of 0.125 Mbits is allocated to the interfield.

The information amount assigned to each field and the predicted data amount in each field determined by the code amount ratio calculation circuit 33 are input to the quantization level determination circuit 35. The quantization level determination circuit 35 compares the amount of data assigned to each field with the amount of data predicted for each field, and outputs the quantization step width corresponding to the error. That is, when the predicted data amount of each field is smaller than the target data amount assigned to each field, the quantization step width is reduced to increase the data amount. On the contrary, when the predicted data amount is larger than the target data amount, the quantization step size is increased to reduce the data amount. On the other hand, the input video signal block is input to the field memory 32, and the data for four fields is delayed until the quantization level is determined by the quantization level determination circuit 30. As described above, it is possible to configure the video signal encoding device that performs the code amount prediction and the code amount control in units of four fields.

Although the code amount prediction is performed by the sum of absolute differences in the block in the above embodiment, the code amount prediction may be performed by the dynamic range in the block as shown in the second embodiment. Further, the code amount prediction is performed in units of 4 fields, but it is not necessarily in units of 4 fields and may be performed in units of arbitrary fields or frames.

Example 5. In the first and second embodiments, when the blocking circuit 2 blocks and outputs the input image data, the shuffling process is performed so that adjacent blocks are not as close to each other as possible, but the shuffling process is performed at the time of blocking. Thus, when the code amount is predicted, if the code amount is predicted for a 1 / n block for one field, the data amount for one field can be predicted. A fifth embodiment of the present invention is an example in which the code amount prediction is simplified by performing the shuffling process during blocking in this way.

Next, the operation will be described. When a 4: 2: 2 component signal is input to the input signal, 1
In the field, Y signal is 720 pixels x 240 lines, BY,
The RY signal is composed of data of 360 pixels × 240 lines. Here, 8 pixels of Y signals that are adjacent in the horizontal direction x 8
Two line blocks and their corresponding BY, RY
Each one block of 8 pixels × 8 lines of a signal is collectively referred to as a sub macro block, and block shuffling is performed in units of this sub macro block. In this case, the image data for one field is
It is divided into a total of 1350 sub-macroblocks of 45 and 30 in the vertical direction. Further, for example, a total of 15 sub-macroblocks adjacent to each other, which are 5 in the horizontal direction and 3 in the vertical direction, are called macroblocks, and one field is divided into 225 macroblock units as shown in FIG. Then, a number of 1 to 225 is given to each macroblock. Further, as shown in FIG. 16, the numbers 1 to 15 are given to the 15 sub macroblocks forming each macroblock.

Here, the block shuffling is performed by repeatedly outputting the sub macro blocks one by one from the macro blocks No. 1 to 225 shown in FIG. However, the order of sub-macroblocks output one by one from each macroblock is performed according to the order of 1 to 15 shown in FIG. That is, the operation of first outputting the first sub macroblock from the first macroblock and then outputting the first submacroblock from the second macroblock is sequentially repeated up to the 225th macroblock. After that, the block shuffling is performed by returning to the first macro block again and repeating the operation of sequentially outputting the second sub macro block from each macro block.

When the block shuffling as described above is performed, data for one field is equally divided into 225, and one sub macroblock is sequentially output from each macroblock, so that 225 blocks are obtained. At the time of output, 1 / 15th of the entire data will be output without bias. In this case, 1 / of the whole after shuffling
If the code amount is predicted for the image data block corresponding to 15, the data amount for one field can be sufficiently predicted. Therefore, the block shuffling as described above is performed, and the code amount prediction in the first embodiment and the second embodiment is performed on the image data of 1/15 of one field, so that the data amount of one field can be obtained. It can be roughly predicted. Therefore, in FIG. 1, when the blocking circuit 2 performs the block shuffling as described above when blocking and outputting the input image data, the code amount prediction circuit 4
, The amount of generated data for one field is predicted by predicting the code amount for 1/15 data of one field, the quantization parameter suitable for the predicted data amount is determined, and the entire amount of field is controlled by controlling the code amount. The code amount of can be kept constant.

In the above embodiment, one field
The amount of data for one field was predicted from the data of / 15, but it is not necessarily 1/15 and 1 / n (n ≧ 2)
The total data amount may be predicted by the data amount of. Further, although the data amount control is performed in field units, it is not always necessary to perform it in field units and may be performed in frame units. Further, although the macroblock is composed of 15 sub-macroblocks, it does not necessarily have to be 15. Further, the sub-macroblock is composed of two Y signal blocks and one BY and RY signal block, but it is not always necessary to compose such a unit, and 2n (n ≧ 2) adjacent to each other. ) Y signal blocks and n corresponding RY and RY signal blocks may be included. The reading order of macroblocks and sub-macroblocks is performed in the order shown in FIGS. 15 and 16, but the reading order is not necessarily as shown in FIGS. 15 and 16, and the reading order is not limited to the field and within the macroblock. The reading order may be arbitrary.

Example 6. In the first embodiment described above, the code amount is predicted from the sum of the sums of the absolute differences in the block using the blocked image data, but the sum of the absolute differences is calculated without changing the input data, and the information is calculated. The amount may be predicted. The sixth embodiment of the present invention is an example in which the data amount prediction is calculated from the sum of absolute differences of the input data to control the code amount.

FIG. 17 is a block diagram showing the arrangement of a video signal encoding apparatus according to the fifth embodiment of the present invention. In the figure, 1 is a digital video input terminal, 2 is a blocking circuit for blocking a digital video input signal, 13 is an information amount prediction of input data in field units,
A code amount control circuit that determines a quantization parameter such that the actual information amount falls within a target value according to the prediction result,
Reference numeral 4 is an orthogonal transformation circuit that performs orthogonal transformation on the image data output from the block circuit 2, and 6 is a quantization circuit that quantizes the output of the orthogonal transformation circuit 5 by the quantization parameter obtained by the code amount control circuit 13. , 7 is an encoding circuit for encoding the output of the quantization circuit 6 by variable length encoding, 12 is a buffer memory, and 9 is an output terminal for outputting the encoded image data.

Next, the operation will be described. For example, a 4: 2: 2 component digital signal is input to the input digital video signal, and the blocking circuit 2 divides the input digital video signal into input blocks having, for example, 8 [pixels] × 8 [lines] as one unit. On the other hand, the video signal is also input to the code amount control circuit 13, and the information amount is predicted in field units. Here, the code amount control circuit 13 is configured as shown in FIG. 18, for example. 18, 61 is a Y signal difference absolute value sum calculation circuit, 62 is a BY signal difference absolute value sum calculation circuit, 63 is an RY signal difference absolute value sum calculation circuit, 64 is a Y signal code amount prediction circuit, and 65. Is a BY signal code amount prediction circuit, 66
Is an RY signal code amount prediction circuit, 67 is a quantization level determination circuit, and 68 is a control reference value table.

Next, the operation of the code amount control circuit 4 will be described. The Y signal in the input image data is input to the Y signal difference absolute value sum operation circuit 61, and the BY and RY signals are respectively the BY signal difference absolute value sum operation circuit 62 and the RY signal difference absolute value. It is input to the value sum calculation circuit 63. In the Y signal difference absolute value sum calculation circuit 61, the data 72 for one field inputted
0 pixel × 240 line DY (i, j) (i = 1 to 720,
j = 1 to 240), the absolute value of the difference between the horizontal and vertical directions

[0063]

[Equation 3]

Is output.

Output SY of Y signal difference absolute value sum calculation circuit 21
Is input to the Y signal code amount prediction circuit 64. In FIG.
The relationship between the horizontal and vertical difference absolute value sum SY of the Y signal and the data amount in the field unit generated when the output of the blocking circuit 2 is orthogonally transformed, standardized and quantized is shown. That is, when the difference absolute value sum SY for each field is given, as in the first embodiment, as shown in FIG.
Therefore, the amount of information generated for each field can be almost predicted. Therefore, in the Y signal code amount prediction circuit 64,
The average of the amount of data generated when standard quantization is performed on the total sum of absolute differences of Y signals as shown by the solid line in FIG. Outputs the predicted data amount when standard quantization is performed for.

On the other hand, when the BY signal and the RY signal are component digital signals of 4: 2: 2, since the data number of the color difference signal is half that of the Y signal, the BY absolute difference value In the sum calculation circuit 62 and the RY signal difference absolute value sum calculation circuit 63, image data for one field of BY or RY input 360 pixels × 240 lines of D
Absolute value sum of the difference between the horizontal and vertical directions with respect to C (i, j) (i = 1 to 360, j = 1 to 240)

[0067]

[Equation 4]

Is output. Here, in the case of a 4: 2: 2 component digital signal, the sampling frequency of the color difference signal is half that of the Y signal. Therefore, as in the case of the first embodiment, the total sum of absolute differences of BY and RY signals and the amount of generated data are different from those of the Y signal shown in FIG. 19, as shown in FIG. Therefore, the BY signal code amount prediction circuit
In the 65 and RY signal code amount prediction circuit 66, the standard quantum for each sum of absolute values output by the BY signal difference absolute value sum calculation circuit 65 and the RY signal difference absolute value sum calculation circuit 66 according to FIG. Output the predicted data amount in the case of digitization.

The predicted data amounts output by the Y signal code amount prediction circuit 64, the BY signal code amount prediction circuit 65, and the RY signal code amount prediction circuit 66 are input to the quantization level determination circuit 67, respectively. .. The quantization level determination circuit 67 adds the predicted data amounts of the Y, BY and RY signals, and predicts the predicted data amount of one field and the control reference value table 68.
Then, the target data amount output from is compared and the quantization step width corresponding to the error is determined and output. That is, when the predicted data amount is smaller than the target data amount, the quantization step size is reduced to increase the data amount.
On the contrary, when the predicted data amount is larger than the target data amount, the quantization step size is increased to reduce the data amount. The operations of the orthogonal transformation circuit 4, the quantizing circuit 6, the encoding circuit 7 and the buffer memory 12 are the same as those in the first embodiment and will not be described.

In the above embodiment, the information amount of the image data is controlled in the field unit when the data amount is predicted. However, it is not necessarily in the field unit and the image data is composed of the frame unit or a plurality of adjacent image blocks. The information amount control may be performed in units of macro blocks.

[0071]

As described in detail above, the video signal coding apparatus of the present invention predicts the amount of data to be generated by predicting the sum of absolute differences in the blocks of the input image signal or the dynamic range. An appropriate quantization level can be determined from the data amount and the code amount can be kept constant.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a code amount prediction circuit in the first embodiment of the present invention.

FIG. 3 is a diagram illustrating characteristics of a code amount predictor with respect to a luminance signal according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating characteristics of a code amount predictor with respect to a color difference signal according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a code amount prediction circuit in a second embodiment of the present invention.

FIG. 6 is a diagram for explaining characteristics of a code amount predictor with respect to a luminance signal in the second embodiment of the present invention.

FIG. 7 is a diagram for explaining characteristics of a code amount predictor with respect to color difference signals in the second embodiment of the present invention.

FIG. 8 is a block diagram showing a third embodiment of the present invention.

FIG. 9 is a diagram showing an example of sub-macroblock division in adaptive quantization determination according to the third embodiment of the present invention.

FIG. 10 is a diagram showing an example of adaptive quantization determination according to the third embodiment of the present invention.

FIG. 11 is a block diagram showing a code amount prediction circuit in a third embodiment of the present invention.

FIG. 12 is a diagram for explaining the characteristics of the code amount predictor with respect to the luminance signal in the third embodiment of the present invention.

FIG. 13 is a diagram for explaining the characteristics of the code amount predictor for color difference signals in the third embodiment of the present invention.

FIG. 14 is a block diagram showing a code amount prediction circuit in a fourth embodiment of the present invention.

FIG. 15 is a diagram for explaining shuffling in a field in a fifth embodiment of the present invention.

FIG. 16 is a diagram illustrating shuffling in a macroblock according to the fifth embodiment of the present invention.

FIG. 17 is a block diagram showing a sixth embodiment of the present invention.

FIG. 18 is a block diagram showing a code amount prediction circuit in a sixth embodiment of the present invention.

FIG. 19 is a diagram for explaining the characteristics of the code amount predictor with respect to the luminance signal in the sixth embodiment of the present invention.

FIG. 20 is a diagram for explaining the characteristics of the code amount predictor with respect to color difference signals in the sixth embodiment of the present invention.

FIG. 21 is an explanatory diagram of a conventional encoding device.

[Explanation of symbols]

 1 Input Terminal 2 Blocking Circuit 3 Switch Circuit 4 Code Amount Control Circuit 5 Orthogonal Transform Circuit 6 Quantization Circuit 7 Encoding Circuit 8 Motion Compensation Circuit 9 Output Terminal 12 Buffer Memory

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[Procedure amendment]

[Submission date] September 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

The minimum and maximum values of V1, V2, V3 and V4 are calculated as follows: A = MIN (V1, V2, V3, V4) B = MAX (V1, V2, V3, V4) and C = B-A Ask for.

Claims (6)

[Claims] 1. A video signal coding apparatus which divides an input video signal into blocks for each predetermined pixel, orthogonally transforms it, and then quantizes and codes it for transmission or magnetic recording. Block difference calculation means for obtaining a sum of absolute values of differences between adjacent pixels in each block for the signal; data amount prediction means for predicting a data amount generated in block units from the output of the block difference calculation means; An addition unit that adds the predicted data amount in units of blocks output from the data amount prediction unit for a plurality of blocks, and a preset target value of the data amount for a plurality of blocks and the output of the addition unit are compared. , Quantization step determining means for determining and outputting a quantization step value such that the actual data amount is almost equal to the target value, and the orthogonally transformed data And a quantizing means for quantizing the signal according to the quantization step value. 2. A video signal coding apparatus which divides an input video signal into blocks for each predetermined pixel, orthogonally transforms them, and then quantizes and codes them for transmission or magnetic recording. For the signal, a dynamic range calculating means for obtaining a dynamic range in each block, a data amount predicting means for predicting a data amount generated in block units from the output of the dynamic range calculating means, and an output from the data amount predicting means Addition means for adding the prediction data amount in units of blocks for a plurality of blocks, comparing the target value of the data amount for a plurality of preset blocks and the prediction data amount output by the data amount prediction means, Quantizer step determiner that determines and outputs the quantizer step value so that the actual data amount is almost equal to the target value A video signal coding apparatus comprising: a stage; and a quantizing means for quantizing the orthogonally transformed data corresponding to the quantization step value. 3. A unit for dividing an input video signal into blocks for each predetermined pixel, performing orthogonal transformation, and then performing n-stage (n ≧ 2) adaptive quantization for each block, and adaptive for each block. Predict the amount of data generated when quantized,
3. The video signal coding device according to claim 1, wherein the predicted data amount is obtained by adding a plurality of blocks, and the code amount is controlled. 4. The video signal encoding device according to claim 1, 2 or 3, wherein the code amount control is performed by predicting a data generation amount for a plurality of blocks from a part of the plurality of blocks. 5. When performing code amount control in units of m fields or m frames, the amount of data generated in each field or frame is predicted and the ratio of the predicted data amount of each field or frame is calculated. The target data amount assigned to each field or frame is obtained by dividing the target data amount pre-assigned in units of m fields or m frames by the predicted data amount ratio, and using the target data amount assigned to each field or frame. The video signal encoding device according to claim 1, 2 or 3, wherein the code amount control is performed in units of each field or frame. 6. A video signal coding apparatus which divides an input video signal into blocks of predetermined pixels, orthogonally transforms them, and then quantizes and codes them for transmission or magnetic recording. And a data amount predicting unit for predicting a data amount in units of macro blocks from the output of the difference absolute value sum. , A preset target value of the data amount in units of a plurality of blocks is compared with the predicted data amount output by the data amount predicting means, and a quantization step value such that the data amount is substantially equal to the target value A quantization step determining means for determining and outputting, and a quantization means for quantizing the orthogonally transformed data corresponding to the quantization step value. Video signal encoding device.